HM62W8512ALRR-8SL [RENESAS]
512KX8 STANDARD SRAM, 85ns, PDSO32, 0.400 INCH, PLASTIC, REVERSE, TSOP2-32;
| 型号： | HM62W8512ALRR-8SL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 512KX8 STANDARD SRAM, 85ns, PDSO32, 0.400 INCH, PLASTIC, REVERSE, TSOP2-32 输入元件 静态存储器 光电二极管 输出元件 内存集成电路 |
| 文件： | 总17页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62W8512A Series
4 M SRAM (512-kword × 8-bit)
ADE-203-641B (Z)
Rev. 1.0
Mar. 16, 1998
Description
The Hitachi HM62W8512A is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.5 µm Hi-CMOS process technology. The
device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high
density mounting. The HM62W8512A is suitable for battery backup system.
Features
•
•
•
Single 3.3 V supply: 3.3 V ± 0.3 V
Access time: 85 ns (max)
Power dissipation
_
_
Active: 36 mW/MHz (max)
Standby: 4 µW (typ)
•
•
•
•
•
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly LV-TTL compatible: All inputs and outputs
Battery backup operation
HM62W8512A Series
Ordering Information
Type No.
Access time
85 ns
Package
HM62W8512ALFP-8
525-mil 32-pin plastic SOP (FP-32D)
HM62W8512ALFP-8SL 85 ns
HM62W8512ALTT-8 85 ns
HM62W8512ALTT-8SL 85 ns
HM62W8512ALRR-8 85 ns
400-mil 32-pin plastic TSOP II (TTP-32D)
400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
HM62W8512ALRR-8SL 85 ns
2
HM62W8512A Series
Pin Arrangement
HM62W8512ALFP Series
HM62W8512ALTT Series
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A18
A16
A14
A12
A7
A18
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
2
2
3
3
4
5
4
A6
6
A5
5
7
A9
A4
8
A11
OE
6
A6
A3
9
A2
7
10
11
12
13
14
15
16
A10
CS
A9
A5
A1
8
A11
OE
A10
A4
A0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
VSS
9
A3
10
11
12
13
14
15
16
A2
CS
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
(Top view)
I/O0
I/O1
I/O2
VSS
HM62W8512ALRR Series
VCC
A15
A17
WE
A13
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
A18
A16
A14
A12
A7
2
3
(Top view)
4
5
6
A6
A9
7
A5
A11
OE
8
A4
9
A3
A10
CS
10
11
12
13
14
15
16
A2
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
VSS
(Top view)
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
VCC
VSS
3
HM62W8512A Series
Block Diagram
V CC
V SS
A12
A7
A1
A0
A2
A5
A6
A3
A4
A18
•
•
•
•
•
Memory Matrix
Row
Decoder
×
1,024 4,096
I/O0
I/O7
•
•
•
Column I/O
•
Input
Data
Control
Column Decoder
A13 A17A15A8A9A11A10A14A16
•
•
CS
Timing Pulse Generator
Read/Write Control
WE
OE
4
HM62W8512A Series
Function Table
Mode
VCC current Dout pin Ref. cycle
×
H
L
L
L
L
×
Not selected
ISB, ISB1
High-Z
High-Z
Dout
Din
—
H
H
L
H
L
Output disable ICC
—
Read
Write
Write
ICC
ICC
ICC
Read cycle
Write cycle (1)
Write cycle (2)
H
L
L
Din
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
Power supply voltage
Voltage on any pin relative to VSS
Power dissipation
–0.5 to +4.6
–0.5*1 to VCC + 0.5*2
V
VT
V
PT
1.0
W
°C
°C
°C
Operating temperature
Storage temperature
Storage temperature under bias
Topr
Tstg
Tbias
0 to +70
–55 to +125
–10 to +85
Notes: 1. –3.0 V for pulse half-width ≤ 30 ns
2. Maximum voltage is 4.6 V
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
3.0
Typ
3.3
0
Max
3.6
Unit
V
Supply voltage
VSS
0
0
V
Input high voltage
Input low voltage
VIH
2.0
–0.3*1
—
VCC + 0.3
0.8
V
VIL
—
V
Note: 1. –3.0 V for pulse half-width ≤ 30 ns
5
HM62W8512A Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol Min
Typ*1
—
Max
1
Unit Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
µA Vin = VSS to VCC
|ILO|
—
1
µA
= VIH or
= VIH or
= VIL, VI/O = VSS to VCC
Operating power
supply current: DC
ICC
—
—
—
—
—
—
10
30
10
mA
= VIL,
others = VIH/VIL, II/O = 0
mA
Operating
power supply current
ICC1
mA Min cycle, duty = 100%
= VIL, others = VIH/VIL
II/O = 0 mA
Operating power
supply current
ICC2
mA Cycle time = 1 µs,
duty = 100%
II/O = 0 mA,
≤ 0.2 V
VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V
Standby power supply
current: DC
ISB
—
—
0.1
0.3
mA
= VIH
Standby power supply
current (1): DC
ISB1
1.2*2
70*2
µA Vin ≥ 0 V,
≥ VCC – 0.2 V
—
—
—
1.2*3
—
30*3
0.4
0.2
—
µA
V
Output low voltage
Output high voltage
VOL
VOH
IOL = 2.0 mA
IOL = 100 µA
IOH = –100 µA
IOH = –2.0 mA
—
V
VCC – 0.2 —
2.4
V
—
—
V
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L version.
3. This characteristics is guaranteed only for L-SL version.
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Input capacitance*1
Input/output capacitance*1 CI/O
Symbol
Typ
Max
8
Unit
pF
Test conditions
Vin = 0 V
Cin
—
—
10
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
6
HM62W8512A Series
AC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ±0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
•
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 0.8 V/2.0 V
Output load (Including scope & jig)
Ω
500
Dout
1.4 V
50 pF
Read Cycle
HM62W8512A
-8
Parameter
Symbol
Min
85
—
—
—
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
tRC
tAA
—
85
85
45
—
—
35
35
—
Address access time
Chip select access time
tCO
tOE
tLZ
Output enable to output valid
Chip selection to output in low-Z
Output enable to output in low-Z
Chip deselection to output in high-Z
Output disable to output in high-Z
Output hold from address change
2
tOLZ
tHZ
tOHZ
tOH
2
0
1, 2
1, 2
0
10
7
HM62W8512A Series
Write Cycle
HM62W8512A
-8
Parameter
Symbol
tWC
Min
85
75
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
—
—
—
—
—
—
35
—
—
—
35
Chip selection to end of write
Address setup time
tCW
4
5
tAS
Address valid to end of write
Write pulse width
tAW
75
55
0
tWP
3, 12
6
Write recovery time
tWR
to output in high-Z
tWHZ
tDW
0
1, 2, 7
Data to write time overlap
Data hold from write time
Output active from output in high-Z
Output disable to output in high-Z
35
0
tDH
tOW
5
2
tOHZ
0
1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low
transition of going low or going low. A write ends at the earlier transition of
or going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of or going high to the end of write cycle.
and a low
. A write begins at the later
going high
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. If the
low transition occurs simultaneously with the
low transition or after the
transition, the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with
low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. tWP ³ tDW min + tWHZ max
8
HM62W8512A Series
Timing Waveforms
Read Timing Waveform (
= VIH)
tRC
Address
tAA
tCO
CS
tLZ
tHZ
tOE
tOLZ
OE
tOHZ
Dout
Valid Data
tOH
9
HM62W8512A Series
Write Timing Waveform (1) (
Clock)
tWC
Address
tAW
tWR
OE
CS
tCW
*8
tWP
tAS
WE
Dout
Din
tOHZ
tDW
tDH
Valid Data
10
HM62W8512A Series
Write Timing Waveform (2) (
Low Fixed)
tWC
Address
tCW
tWR
CS
*8
tAW
tWP
tOH
WE
tAS
tOW
tWHZ
*10
*9
Dout
Din
tDW
tDH
*11
Valid Data
11
HM62W8512A Series
Low V Data Retention Characteristics
(Ta = 0 to +70°C)
CC
Parameter
Symbol Min
Typ Max
Unit
Test conditions*3
VCC for data retention
Data retention current
VDR
2
—
1*4
—
50*1
V
≥ VCC – 0.2 V, Vin ≥ 0 V
ICCDR
—
µA
VCC = 3.0 V, Vin ≥ 0 V
≥ VCC – 0.2 V
—
0
1*4
—
—
15*2
—
µA
ns
Chip deselect to data retention time tCDR
Operation recovery time tR
See retention waveform
5
—
ms
Notes: 1. For L-version and 20 µA (max.) at Ta = 0 to 40°C.
2. For SL-version and 3 µA (max.) at Ta = 0 to 40°C.
3.
controls address buffer,
buffer,
buffer, and Din buffer. In data retention mode, Vin
levels (address, , I/O) can be in the high impedance state.
,
4. Typical values are at VCC = 3.0 V, Ta = 25°C and specified loading, and not guaranteed.
Low VCC Data Retention Timing Waveform ( Controlled)
Data retention mode
tR
tCDR
VCC
3.0 V
2.0 V
VDR
CS
0 V
CS ≥ VCC – 0.2 V
12
HM62W8512A Series
Package Dimensions
HM62W8512ALFP Series (FP-32D)
Unit: mm
20.45
20.95 Max
17
32
1
16
14.14 ± 0.30
1.00 Max
1.42
0° – 8°
0.10
0.80 ± 0.20
1.27
0.40 ± 0.08
0.38 ± 0.06
0.15
M
Hitachi Code
JEDEC
EIAJ
FP-32D
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.3 g
13
HM62W8512A Series
Package Dimensions
(cont.)
HM62W8512ALTT Series (TTP-32D)
Unit: mm
20.95
21.35 Max
32
17
16
1
1.27
0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32D
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
14
HM62W8512A Series
Package Dimensions
(cont.)
HM62W8512ALRR Series (TTP-32DR)
Unit: mm
20.95
21.35 Max
1
16
32
17
1.27
0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32DR
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
15
HM62W8512A Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
16
HM62W8512A Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
0.0
0.1
0.2
1.0
Oct. 3, 1996
Oct. 21, 1997
Nov. 1997
Initial issue
K. Imato
K. Imato
Deletion of HM62W8512-7 Series
Change of Subtitle
M. Higuchi K. Imato
M. Higuchi K. Imato
Mar. 16, 1998
DC Characteristics
ICC1 (max): 27mA to 30 mA
17
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