HM62W8512BI [HITACHI]
4 M SRAM (512-kword x 8-bit); 的4M SRAM（ 512千字×8位）的
| 型号： | HM62W8512BI |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 4 M SRAM (512-kword x 8-bit) |
| 文件： | 总14页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62W8512BI Series
4 M SRAM (512-kword × 8-bit)
ADE-203-1086A (Z)
Rev. 1.0
Jul. 13, 1999
Description
The Hitachi HM62W8512BI is a 4-Mbit static RAM organized 512-kword × 8-bit. HM62W8512BI Series
has realized higher density, higher performance and low power consumption by employing Hi-CMOS process
technology. The HM62W8512BI Series offers low power standby power dissipation; therefore, it is suitable
for battery backup systems. It is packaged in standard 32-pin TSOP II.
Features
•
•
•
Single 3.3 V supply: 3.3 V ± 0.3V
Access time: 70/85 ns (max)
Power dissipation
Active: 16.5 mW/MHz (typ)
Standby: 3.3 µW (typ)
•
•
•
•
•
•
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly LV-TTL compatible: All inputs and outputs
Battery backup operation
Operating temperature: –40 to +85˚C
Ordering Information
Type No.
Access time
Package
HM62W8512BLTTI-7
HM62W8512BLTTI-8
70 ns
85 ns
400-mil 32-pin plastic TSOP II (TTP-32D)
HM62W8512BI Series
Pin Arrangement
32-pin TSOPII (Normal Type TSOP)
32
A18
A16
A14
A12
A7
1
VCC
A15
A17
WE
A13
A8
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
4
5
A6
6
A5
7
A9
A4
8
A11
OE
A3
9
A2
10
11
12
13
14
15
16
A10
CS
A1
A0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
VSS
(Top view)
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CS
Function
Address input
Data input/output
Chip select
OE
Output enable
Write enable
Power supply
Ground
WE
VCC
VSS
2
HM62W8512BI Series
Block Diagram
V CC
V SS
A18
A16
A1
•
•
•
•
•
A0
Memory Matrix
A2
Row
Decoder
×
1,024 4,096
A12
A14
A3
A7
A6
I/O0
I/O7
•
•
•
•
Column I/O
Input
Data
Control
Column Decoder
A11A10A4 A5
A13A17A15
A8 A9
•
•
CS
Timing Pulse Generator
Read/Write Control
WE
OE
3
HM62W8512BI Series
Function Table
WE
×
CS
H
L
OE
×
Mode
VCC current
Dout pin
High-Z
High-Z
Dout
Ref. cycle
—
Not selected
Output disable
Read
ISB, ISB1
ICC
H
H
L
H
L
—
L
ICC
Read cycle
Write cycle (1)
Write cycle (2)
L
H
L
Write
ICC
Din
L
L
Write
ICC
Din
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Power supply voltage
Voltage on any pin relative to VSS
Power dissipation
–0.5 to +4.6
–0.5*1 to VCC + 0.5*2
1.0
VT
V
PT
W
Operating temperature
Storage temperature
Storage temperature under bias
Topr
Tstg
Tbias
–40 to +85
–55 to +125
–40 to +85
°C
°C
°C
Notes: 1. –3.0 V for pulse half-width ≤ 30 ns
2. Maximum voltage is 4.6 V
Recommended DC Operating Conditions (Ta = –40 to +85°C)
Parameter
Symbol
VCC
Min
3.0
0
Typ
3.3
0
Max
3.6
0
Unit
V
Supply voltage
VSS
V
Input high voltage
Input low voltage
VIH
2.4
–0.3*1
—
VCC + 0.3
0.6
V
V
VIL
—
Note: 1. –3.0 V for pulse half-width ≤ 30 ns
4
HM62W8512BI Series
DC Characteristics (Ta = –40 to +85°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol Min
Typ*1
—
Max
1
Unit Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
µA
µA
Vin = VSS to VCC
|ILO|
—
1
CS = VIH or OE = VIH or
WE = VIL, VI/O = VSS to VCC
Operating power
supply current: DC
ICC
—
—
—
—
10
45
mA CS = VIL,
others = VIH/VIL, II/O = 0 mA
Operating power supply current ICC1
mA Min cycle, duty = 100%
CS = VIL, others = VIH/VIL
II/O = 0 mA
Operating power
supply current
ICC2
—
5
10
mA Cycle time = 1 µs,
duty = 100%
II/O = 0 mA, CS ≤ 0.2 V
VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V
Standby power supply
current: DC
ISB
—
—
0.1
1*2
0.3
mA CS = VIH
Standby power supply
current (1): DC
ISB1
VOL
40*2
µA
Vin ≥ 0 V,
CS ≥ VCC – 0.2 V
Output low voltage
—
—
—
—
0.4
0.2
—
V
V
V
V
IOL = 2.0 mA
IOL = 100 µA
IOH = –100 µA
IOH = –2.0 mA
Output high voltage
VOH
VCC – 0.2 —
2.4
—
—
Note: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L-version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Cin
Typ
—
Max
8
Unit
pF
Test conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
CI/O
—
10
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
5
HM62W8512BI Series
AC Characteristics (Ta = –40 to +85°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
•
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 0.8 V/2.0 V
Output load (Including scope & jig)
Ω
500
Dout
1.4 V
50 pF
Read Cycle
HM62W8512BI
-7
-8
Min
85
—
—
—
10
5
Parameter
Symbol
tRC
Min
70
—
—
—
10
5
Max
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
Address access time
tAA
70
70
35
—
85
85
45
—
Chip select access time
tCO
Output enable to output valid
Chip selection to output in low-Z
Output enable to output in low-Z
Chip deselection to output in high-Z
Output disable to output in high-Z
Output hold from address change
tOE
tLZ
2
tOLZ
tHZ
tOHZ
tOH
—
—
2
0
30
30
—
0
35
35
—
1, 2
1, 2
0
0
10
10
6
HM62W8512BI Series
Write Cycle
HM62W8512BI
-7
-8
Min
85
75
0
Parameter
Symbol
tWC
Min
70
60
0
Max
—
—
—
—
—
—
30
—
—
—
30
Max
—
—
—
—
—
—
35
—
—
—
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Chip selection to end of write
Address setup time
tCW
4
5
tAS
Address valid to end of write
Write pulse width
tAW
60
50
0
75
55
0
tWP
3, 12
6
Write recovery time
tWR
WE to output in high-Z
Data to write time overlap
Data hold from write time
Output active from output in high-Z
Output disable to output in high-Z
tWHZ
tDW
0
0
1, 2, 7
30
0
35
0
tDH
tOW
5
5
2
tOHZ
0
0
1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high
or WE going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. tWP ≥ tDW min + tWHZ max
7
HM62W8512BI Series
Timing Waveforms
Read Timing Waveform (WE = VIH)
tRC
Address
tAA
tCO
CS
tLZ
tHZ
tOE
tOLZ
OE
tOHZ
Dout
Valid Data
tOH
8
HM62W8512BI Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
tAW
tWR
OE
tCW
CS
*8
tWP
tAS
WE
tOHZ
Dout
Din
tDW
tDH
Valid Data
9
HM62W8512BI Series
Write Timing Waveform (2) (OE Low Fixed)
tWC
Address
tCW
tWR
CS
*8
tAW
tWP
tOH
WE
tAS
tOW
tWHZ
*10
*9
Dout
Din
tDW
tDH
*11
Valid Data
10
HM62W8512BI Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol Min
Typ Max
Unit
V
Test conditions*2
VCC for data retention
Data retention current
VDR
2
—
—
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
ICCDR
—
0.8*3 20*1
µA
VCC = 3.0 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
Chip deselect to data retention time tCDR
Operation recovery time tR
0
tRC*4
—
—
—
—
ns
ns
See retention waveform
Notes: 1. For L-version and 10 µA (max.) at Ta = –40 to +40°C.
2. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
3. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
4. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS Controlled)
tR
tCDR
Data retention mode
VCC
3.0 V
2.4 V
VDR
CS
0 V
CS ≥ VCC – 0.2 V
11
HM62W8512BI Series
Package Dimensions
HM62W8512BLTTI Series (TTP-32D)
Unit: mm
20.95
21.35 Max
32
17
16
1
1.27
*0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32D
Conforms
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
12
HM62W8512BI Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
13
HM62W8512BI Series
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
1.0 Jul. 13, 1999 Initial issue
14
相关型号：
©2020 ICPDF网 联系我们和版权申明