HM62V8100LTTI-5 [RENESAS]
Wide Temperature Range Version 8 M SRAM (1024-kword x 8-bit); 宽温度范围版本的8M SRAM （ 1024 -千字×8位）
| 型号： | HM62V8100LTTI-5 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Wide Temperature Range Version 8 M SRAM (1024-kword x 8-bit) |
| 文件： | 总21页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
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names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
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these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
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contained therein.
HM62V8100I Series
Wide Temperature Range Version
8 M SRAM (1024-kword × 8-bit)
ADE-203-1278B (Z)
Rev. 1.0
Mar. 12, 2002
Description
The Hitachi HM62V8100I Series is 8-Mbit static RAM organized 1,048,576-word × 8-bit. HM62V8100I
Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS
process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup
systems. It is packaged in 48 bumps chip size package with 0.75 mm bump pitch or standard 44-pin TSOP II
for high density surface mounting.
Features
•
•
•
Single 3.0 V supply: 2.7 V to 3.6 V
Fast access time: 55 ns (Max)
Power dissipation:
Active: 6.0 mW/MHz (Typ)
Standby: 1.5 µW (Typ)
•
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
•
•
•
•
Battery backup operation.
2 chip selection for battery backup
Temperature range: –40 to +85°C
HM62V8100I Series
Ordering Information
Type No.
Access time Package
HM62V8100LTTI-5
HM62V8100LTTI-5SL
HM62V8100LBPI-5
HM62V8100LBPI-5SL
55 ns
55 ns
55 ns
55 ns
400-mil 44pin plastic TSOP II (normal-bend type) (TTP-44DE)
48-bumps CSP with 0.75 mm bump pitch (TBP-48A)
2
HM62V8100I Series
Pin Arrangement
44-pin TSOP
44
1
A5
A4
A3
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A6
3
A7
A2
4
OE
CS2
A1
5
A0
6
A8
CS1
NC
7
NC
8
NC
NC
9
I/O7
I/O6
VSS
VCC
I/O5
I/O4
NC
I/O0
I/O1
VCC
VSS
I/O2
I/O3
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
A9
WE
A19
A18
A17
A16
A15
A10
A11
A12
A13
A14
(Top view)
Pin Description (TSOP)
Pin name
A0 to A19
I/O0 to I/O7
CS1
Function
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
Output enable
Power supply
Ground
CS2
WE
OE
VCC
VSS
NC
No connection
3
HM62V8100I Series
48-bumps CSP
1
2
3
4
5
6
A
NC
OE
A0
A1
A2
CS2
NC
NC
NC
A3
A5
A4
A6
CS1
NC
B
C
I/O0
NC
I/O4
D
E
F
V
V
I/O1
I/O2
A17
NC
A7
I/O5
I/O6
V
CC
SS
A16
V
SS
CC
I/O3
NC
NC
NC
A8
A14
A12
A9
A15
A13
A10
NC
WE
A11
I/O7
NC
G
A18
A19
H
(Top view)
Pin Description (CSP)
Pin name
A0 to A19
I/O0 to I/O7
CS1
Function
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
Output enable
Power supply
Ground
CS2
WE
OE
VCC
VSS
NC
No connection
4
HM62V8100I Series
Block Diagram (TSOP)
LSB
A5
V CC
V SS
A6
A7
A4
•
•
•
•
•
A3
Memory matrix
2,048 x 4,096
Row
decoder
A9
A10
A11
A12
A13
MSB
A14
I/O0
I/O7
•
•
•
•
Column I/O
Input
data
control
Column decoder
LSB
MSB
A16 A17A18A19A0
A2
A15A8
A1
•
•
CS2
CS1
Control logic
WE
OE
5
HM62V8100I Series
Block Diagram (CSP)
LSB
A6
V CC
V SS
A15
A11
A16
A7
•
•
•
•
•
Memory matrix
2,048 x 4,096
Row
decoder
A13
A10
A2
A4
A1
MSB
A3
I/O0
I/O7
•
•
•
•
Column I/O
Input
data
control
Column decoder
LSB
MSB
A12 A9 A18 A8A14
A17 A0A19
A5
•
•
CS2
CS1
Control logic
WE
OE
6
HM62V8100I Series
Operation Table
CS1
H
CS2
×
WE
×
OE
×
I/O0 to I/O7
High-Z
High-Z
Dout
Operation
Standby
Standby
Read
×
L
×
×
L
H
H
L
L
L
H
×
Din
Write
L
H
H
H
High-Z
Output disable
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
Power supply voltage relative to VSS
–0.5 to + 4.6
–0.5*1 to VCC + 0.3*2
1.0
V
Terminal voltage on any pin relative to VSS
Power dissipation
VT
V
PT
W
°C
°C
Storage temperature range
Tstg
Tbias
–55 to +125
–40 to +85
Storage temperature range under bias
Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter
Symbol Min
Typ
Max
3.6
Unit
Note
Supply voltage
VCC
VSS
VIH
VIL
2.7
0
3.0
0
V
0
V
Input high voltage
2.2
–0.3
–40
—
—
—
VCC + 0.3
0.6
V
Input low voltage
V
1
Ambient temperature range
Ta
85
°C
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.
7
HM62V8100I Series
DC Characteri stics
Parameter
Symbol Min
Typ*1 Max
Unit
µA
Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
—
—
1
1
Vin = VSS to VCC
|ILO|
µA
CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL, or
VI/O = VSS to VCC
Operating current
ICC
—
—
—
20
25
mA
mA
CS1 = VIL, CS2 = VIH,
Others = VIH/VIL, II/O = 0 mA
Average operating current
ICC1
14
Min. cycle, duty = 100%,
II/O = 0 mA, CS1 = VIL, CS2 = VIH,
Others = VIH/VIL
ICC2
—
2
4
mA
Cycle time = 1 µs, duty = 100%,
II/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ VCC – 0.2 V
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
Standby current
Standby current
ISB
—
—
0.1
0.5
0.3
25
mA
CS2 = VIL
2
3
ISB1
*
µA
0 V ≤ Vin
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V
ISB1
*
—
0.5
—
10
—
µA
V
Output high voltage
Output low voltage
VOH
VOL
2.2
—
IOH = –1 mA
IOL = 2 mA
—
0.4
V
Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.
2. This characteristic is guaranteed only for L version.
3. This characteristic is guaranteed only for L-SL version.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
8
Unit
pF
Test conditions Note
Input capacitance
Input/output capacitance
Vin = 0 V
VI/O = 0 V
1
1
CI/O
—
—
10
pF
Note: 1. This parameter is sampled and not 100% tested.
8
HM62V8100I Series
AC Characteristics (Ta = –40 to +85°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: VIL = 0.4 V, VIH = 2.2 V
Input rise and fall time: 5 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
VTM
R1
R2
Dout
R1 = 3070 Ω
30pF
R2 = 3150 Ω
VTM = 2.8 V
9
HM62V8100I Series
Read Cycle
HM62V8100I
-5
Parameter
Symbol
tRC
Min
55
—
—
—
—
10
10
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
—
55
55
55
35
—
—
—
—
20
20
20
Address access time
Chip select access time
tAA
tACS1
tACS2
tOE
Output enable to output valid
Output hold from address change
Chip select to output in low-Z
tOH
tCLZ1
tCLZ2
tOLZ
2, 3
2, 3
Output enable to output in low-Z
Chip deselect to output in high-Z
2, 3
tCHZ1
tCHZ2
tOHZ
0
1, 2, 3
1, 2, 3
1, 2, 3
0
Output disable to output in high-Z
0
10
HM62V8100I Series
Write Cycle
HM62V8100I
-5
Parameter
Symbol
tWC
Min
55
50
50
40
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
—
—
—
—
—
—
—
—
—
20
20
Address valid to end of write
Chip selection to end of write
Write pulse width
tAW
tCW
5
4
6
7
tWP
Address setup time
tAS
Write recovery time
tWR
0
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in High-Z
Write to output in high-Z
tDW
25
0
tDH
tOW
5
2
tOHZ
tWHZ
0
1, 2
1, 2
0
Notes: 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device
and from device to device.
4. A write occures during the overlap of a low CS1, a high CS2, a low WE. A write begins at the latest
transition among CS1 going low, CS2 going high, WE going low. A write ends at the earliest
transition among CS1 going high, CS2 going low, WE going high. tWP is measured from the
beginning of write to the end of write.
5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
11
HM62V8100I Series
Timing Waveform
Read Cycle
tRC
Address
Valid address
tAA
tACS1
CS1
2, 3
2, 3
1, 2, 3
tCLZ1
*
tCHZ1
*
CS2
tACS2
tCLZ2
1, 2, 3
*
tCHZ2
*
1, 2, 3
tOHZ
*
tOE
OE
2, 3
tOLZ
*
tOH
High impedance
Dout
Valid data
12
HM62V8100I Series
Write Cycle (1) (WE Clock)
tWC
Valid address
Address
7
tWR
*
5
5
tCW
*
CS1
tCW
*
CS2
tAW
4
tWP
*
6
WE
tAS*
tDW
Valid data
tDH
Din
1, 2
tWHZ
*
2
tOW
*
High impedance
Dout
13
HM62V8100I Series
Write Cycle (2) (CS Clock, OE= VIH)
tWC
Valid address
tAW
Address
6
7
5
5
tAS
*
tWR*
tCW
*
CS1
tCW
*
CS2
4
tWP
*
WE
tDW
Valid data
tDH
Din
High impedance
Dout
14
HM62V8100I Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ*4
Max
Unit
Test conditions*3
VCC for data retention
VDR
2.0
—
3.6
V
Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC – 0.2 V
CS1 ≥ VCC – 0.2 V
1
Data retention current
ICCDR
*
*
—
0.5
25
µA
VCC = 3.0 V, Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC – 0.2 V,
CS1 ≥ VCC – 0.2 V
2
ICCDR
tCDR
—
0
0.5
—
10
—
µA
Chip deselect to data
retention time
ns
See retention waveform
Operation recovery time
tR
tRC*5
—
—
ns
Notes: 1. This characteristic is guaranteed only for L version.
2. This characteristic is guaranteed only for L-SL version.
3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1
controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other
input levels (address, WE, OE, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed.
5. tRC = read cycle time.
15
HM62V8100I Series
Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)
Data retention mode
tCDR
tR
VCC
2.7 V
2.2 V
VDR
CS1
0 V
≥
CS1 VCC – 0.2 V
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
tCDR
Data retention mode
tR
VCC
2.7 V
CS2
VDR
0.6 V
0 V
<
<
0 V CS2 0.2 V
16
HM62V8100I Series
Package Dimensions
HM62V8100LTTI Series (TTP-44DE)
As of July, 2001
Unit: mm
18.41
18.81 Max
44
23
22
1
0.80
0.13
0.80
*0.27 ± 0.07
0.25 ± 0.05
M
11.76 ± 0.20
1.005 Max
0˚ – 5˚
0.50 ± 0.10
0.10
Hitachi Code
TTP-44DE
JEDEC
JEITA
Mass (reference value)
—
—
0.43 g
*Dimension including the plating thickness
Base material dimension
17
HM62V8100I Series
HM62V8100LBPI Series (TBP-48A)
As of July, 2001
Unit: mm
INDEX
MARK
A
6.50
A
0.20 S A
6
5
4
3
2
1
Pin#1 INDEX
A
B
B
C
D
E
F
G
H
0.75
1.375
0.15
4×
0.2 S
48 × φ0.35 ± 0.05
φ0.08 M S A B
S
S
0.10
Details of the part A
Hitachi Code
JEDEC
TBP-48A
–
JEITA
–
Mass (reference value)
0.13 g
18
HM62V8100I Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor
(America) Inc.
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Hitachi Europe Ltd.
Electronic Components Group
Hitachi Asia Ltd.
Hitachi Tower
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Singapore 049318
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Group III (Electronic Components)
7/F., North Tower
San Jose,CA 95134
Lower Cookham Road
World Finance Centre,
Tel: <1> (408) 433-1990 Maidenhead
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Tel: <44> (1628) 585000
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Fax : <65>-538-6933/538-3877
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Tel : <852>-(2)-735-9218
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URL : http://semiconductor.hitachi.com.hk
Fax: <44> (1628) 585200
Hitachi Asia Ltd.
(Taipei Branch Office)
4/F, No. 167, Tun Hwa North Road
Hung-Kuo Building
Hitachi Europe GmbH
Electronic Components Group
Dornacher Straße 3
D-85622 Feldkirchen
Postfach 201,D-85619 Feldkirchen
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
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Tel : <886>-(2)-2718-3666
Fax : <886>-(2)-2718-8180
Telex : 23222 HAS-TP
URL : http://www.hitachi.com.tw
Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 5.0
19
相关型号：
HM62V8100LTTI-5SL#BT
1MX8 STANDARD SRAM, 55ns, PDSO44, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-44
RENESAS
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