HD74LVC125A [RENESAS]
Quad. Bus Buffer Gates with 3-state Outputs; 四。总线缓冲器门与3态输出
| 型号： | HD74LVC125A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Quad. Bus Buffer Gates with 3-state Outputs |
| 文件： | 总7页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LVC125A
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0348–0400Z
(Previous ADE-205-108C (Z))
Rev.4.00
Jul. 23, 2004
Description
The HD74LVC125A has four bus buffer gates in a 14 pin package. The device require the three state control input C to
be taken high to put the output into the high impedance condition, whereas the device requires the control input to be
low to put the output into high impedance. Low voltage and high-speed operation is suitable at the battery drive
product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off st
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta =
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta =
High output current ±24 mA (@VCC = 3.0 V to 5.5
Ordering Information
Part Name
Package Type
ckage
Abbreviation
Taping Abbreviation
(Quantity)
HD74LVC125AFPEL
HD74LVC125ATELL
SOP–14 pin (J
TSSOP–14
FP
T
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales officilability.
Function Table
Inputs
Outputs Y
C
H
L
L
Z
L
L
H
H
H:
L:
X:
Z:
High level
Low level
Immaterial
High impedance
Rev.4.00 Jul. 23, 2004 page 1 of 6
HD74LVC125A
Pin Arrangement
VCC
4C
4A
4Y
3C
3A
3Y
1
2
3
14
13
12
11
10
9
1C
1A
1Y
2C 4
5
6
7
2A
2Y
GND
8
(Top view)
Absolute Maximum Ratings
Item
Symbol
VCC
IIK
Ratings
itions
Supply voltage
Input diode current
Input voltage
–0.5 to 6.0
–50
VI = –0.5 V
VI
–0.5 to 6.
–50
Output diode current
IOK
A
VO = –0.5 V
50
VO = VCC +0.5 V
Output "H" or "L"
Output "Z" or VCC:OFF
Output voltage
VO
IO
V
Output current
mA
mA
°C
VCC, GND current / pin
Storage temperature
I
Note: The absolute maximmust not individually be exceeded, and furthermore, no two of
which may be rea
Rev.4.00 Jul. 23, 2004 page 2 of 6
HD74LVC125A
Recommended Operating Conditions
Item
Symbol
Ratings
1.5 to 5.5
2.0 to 5.5
0 to 5.5
0 to VCC
0 to 5.5
–40 to 85
–12
Unit
Conditions
Data hold
Supply voltage
VCC
V
At operation
C, A
Input / output voltage
VI
V
V
VO
Output "H" or "L"
Output "Z" or VCC:OFF
Operating temperature
Output current
Ta
IOH
°C
mA
VCC = 2.7 V
–24*2
VCC = 3.0 V to 5.5 V
VCC = 2.7 V
IOL
12
24*2
mA
VCC = 3.0 V to 5.5 V
Input rise / fall time *1
tr, tf
10
ns/V
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
2. Duty cycle ≤ 50%
Electrical Characteristics
Ta = –40 to
Item
Symbol
V
CC (V)
onditions
Min
Input voltage
VIH
2.7 to 3.6 2.0
4.5 to 5.5
2.7 to 3.6
4.5 to 5.5
V
CC
VIL
Output voltage
VOH
2.7 to
IOH = –100 µA
IOH = –12 mA
2.7
IOH = –24 mA
—
0.2
0.4
0.55
0.55
±5.0
±5.0
V
IOL = 100 µA
IOL = 12 mA
IOL = 24 mA
—
—
Input current
IIN
5.5
.7 to 5.5
—
µA
µA
VIN = 5.5 VCC GND
VIN = VCC, GND,
Off state output current
IIOZ
—
V
OUT = 5.5 V or GND
Output leak current
IOFF
ICC
0
—
—
—
—
20
µA
µA
VIN / VOUT = 5.5 V
Quiescent supply current
2.7 to 3.6
2.7 to 5.5
3.0 to 3.6
±10
10
VIN / VOUT = 3.6 to 5.5 V
VIN = VCC or GND
∆ICC
500
µA
VIN = one input at (VCC –0.6) V,
other inputs at VCC or GND
Rev.4.00 Jul. 23, 2004 page 3 of 6
HD74LVC125A
Switching Characteristics
Ta = –40 to 85°C
From
To
Item
Symbol VCC (V)
Unit
(Input)
(Output)
Min
—
Typ
—
Max
Propagation delay time
tPLH
tPHL
2.7
6.5
6.0
5.0
8.0
7.0
6.0
6.5
5.5
4.5
—
ns
A
C
C
Y
Y
Y
3.3±0.3
5.0±0.5
2.7
1.5
—
—
—
Output enable time
Output disable time
tZH
tZL
—
—
ns
ns
ns
3.3±0.3
5.0±0.5
2.7
1.5
—
—
—
tHZ
tLZ
—
—
3.3±0.3
5.0±0.5
2.7
1.5
—
—
—
Between output pins skew *1 tOSLH
tOSHL
—
—
3.3±0.3
5.0±0.5
2.7
—
—
1.0
1.0
—
—
—
Input capacitance
Output capacitance
CIN
CO
—
3.0
15.0
2.7
—
—
Note: 1. This parameter is characterized but not tested.
tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn
|
Test Circuit
VCC
VC
Input
Pulse Generator
Zout = 50 Ω
500Ω
S1
OPEN
*1 See under table
GND
450Ω
CL=
50 pF
50 Ω Scope
S1
Symbol
Vcc=2.7V,
3.3±0.3V
Vcc=5.0±0.5V
tPLH/ tPHL
OPEN
GND
6 V
OPEN
tZH/ tHZ
tZL / tLZ
GND
2×Vcc
Note:
1. CL includes probe and jig capacitance.
Rev.4.00 Jul. 23, 2004 page 4 of 6
HD74LVC125A
Waveforms – 1
tr
tf
VIH
90 %
Vref
90 %
Vref
Input A
10 %
10 %
tPHL
GND
tPLH
VOH
Vref
Vref
Output Y
VOL
Notes:
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform : PRR = 10 MHz, duty cycle 50%
Waveforms – 2
tf
tr
V
IH
90 %
Vref
Input C
10 %
GND
tZL
≈VOH1
Vref
Waveform - A
Waveform - B
VOL + 0.3 V
VOH– 0.3 V
VOL
VOH
tZ
Z
≈VOL1
Vcc=2.7V,
3.3±0.3V
Vcc=5.0±0.5V
TEST
VIH
2.7 V
1.5 V
3 V
Vcc
50%Vcc
Vcc
Vref
VOH1
VOL1
GND
GND
Notes:
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform : PRR = 10 MHz, duty cycle 50%
3. Waveform – A shows input conditions such that the output is "L" level when enable by the
output control.
4. Waveform – B shows input conditions such that the output is "H" level when enable by the
output control.
Rev.4.00 Jul. 23, 2004 page 5 of 6
HD74LVC125A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
8
14
1
7
+ 0.20
7.80
– 0.30
1.42 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
P-14DAV
—
ue)
Conforms
0.23 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
5.0
5.3
14
1.0
*0.20 ± 0.05
13 M
6.40 ± 0.20
0.83 Max
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-14DV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.4.00 Jul. 23, 2004 page 6 of 6
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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