HD74LV245AFPEL [RENESAS]

Octal Bus Transceivers with 3-state Outputs; 八路总线收发器与3态输出
HD74LV245AFPEL
型号: HD74LV245AFPEL
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

Octal Bus Transceivers with 3-state Outputs
八路总线收发器与3态输出

总线驱动器 总线收发器 逻辑集成电路 光电二极管
文件: 总10页 (文件大小:85K)
中文:  中文翻译
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HD74LV245A  
Octal Bus Transceivers with 3-state Outputs  
REJ03D0329–0300Z  
(Previous ADE-205-247A (Z))  
Rev.3.00  
Jun. 24, 2004  
Description  
The HD74LV245A has eight buffers with three-state outputs in a 20-pin package. When DIR is high, data is  
transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs to the A  
outputs. The A and B buses are separated by making the enable input (OE) high level. Low-voltage operation is  
suitable for battery-powered products (e.g., notebook computers), and the low power consumption extends the battery  
life.  
Features  
VCC = 2.0 V to 5.5 V operation  
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)  
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)  
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)  
Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)  
Ordering Information  
Part Name  
Package Type  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
HD74LV245AFPEL  
HD74LV245ARPEL  
HD74LV245ATELL  
SOP–20 pin (JEITA)  
SOP–20 pin (JEDEC)  
TSSOP–20 pin  
FP–20DAV  
FP–20DBV  
TTP–20DAV  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
ELL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Operation  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Note: H: High level  
L: Low level  
X: Immaterial  
Rev.3.00 Jun. 24, 2004 page 1 of 9  
HD74LV245A  
Pin Arrangement  
1
2
3
4
5
6
7
8
9
20 VCC  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
GND 10  
(Top view)  
Absolute Maximum Ratings  
Item  
Symbol  
VCC  
Ratings  
Unit  
Conditions  
Supply voltage range  
Input voltage range*1  
Output voltage range*1, *2  
–0.5 to 7.0  
–0.5 to 7.0  
–0.5 to VCC + 0.5  
–0.5 to 7.0  
–20  
V
V
V
VI  
VO  
Output: H or L  
VCC: OFF or Output: Z  
VI < 0  
Input clamp current  
IIK  
IOK  
IO  
mA  
mA  
mA  
mA  
Output clamp current  
±50  
VO < 0 or VO > VCC  
VO = 0 to VCC  
Continuous output current  
Continuous current through  
±35  
ICC or  
IGND  
±70  
VCC or GND  
Maximum power dissipation at PT  
Ta = 25°C (in still air)*3  
835  
mW  
SOP  
757  
TSSOP  
Storage temperature  
Tstg  
–65 to 150  
°C  
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of  
which may be realized at the same time.  
1. The input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are  
observed.  
2. This value is limited to 5.5 V maximum.  
3. The data above are measured by VBE method mounting on glass epoxy board (40 × 40 × 1.6 mm) with 10%  
of wiring density.  
Rev.3.00 Jun. 24, 2004 page 2 of 9  
HD74LV245A  
Recommended Operating Conditions  
Item  
Symbol  
VCC  
Min  
2.0  
0
Max  
5.5  
5.5  
VCC  
5.5  
–50  
–2  
Unit  
V
Conditions  
Supply voltage range  
Input voltage range  
Output voltage range  
VI  
V
VO  
0
V
Output: H or L  
0
High impedance state  
VCC = 2.0 V  
Output current  
IOH  
0
µA  
mA  
VCC = 2.3 to 2.7 V  
VCC = 3.0 to 3.6 V  
VCC = 4.5 to 5.5 V  
VCC = 2.0 V  
–8  
–16  
50  
IOL  
µA  
2
mA  
VCC = 2.3 to 2.7 V  
VCC = 3.0 to 3.6 V  
VCC = 4.5 to 5.5 V  
VCC = 2.3 to 2.7 V  
VCC = 3.0 to 3.6 V  
8
16  
Input transition rise or fall rate  
Operating free-air temperature  
t /v  
200  
100  
20  
ns/V  
°C  
0
0
VCC = 4.5 to 5.5 V  
Ta  
–40  
85  
Note: Unused or floating inputs must be held high or low.  
Logic Diagram  
1
DIR  
19  
18  
OE  
2
A1  
B1  
Other seven channels  
Rev.3.00 Jun. 24, 2004 page 3 of 9  
HD74LV245A  
DC Electrical Characteristics  
Ta = –40 to 85°C  
Unit Test Conditions  
V
Item  
Symbol  
V
CC (V)*1  
Min  
Typ Max  
Input voltage  
VIH  
2.0  
1.5  
0.5  
2.3 to 2.7  
3.0 to 3.6  
4.5 to 5.5  
2.0  
V
V
V
CC × 0.7  
CC × 0.7  
CC × 0.7  
VIL  
2.3 to 2.7  
3.0 to 3.6  
4.5 to 5.5  
V
V
V
CC × 0.3  
CC × 0.3  
CC × 0.3  
Output voltage  
VOH  
Min to Max VCC –0.1  
V
IOH = –50 µA  
IOH = –2 mA  
IOH = –8 mA  
IOH = –16 mA  
IOL = 50 µA  
2.3  
2.0  
2.48  
3.8  
3.0  
4.5  
VOL  
Min to Max  
2.3  
0.1  
0.4  
0.44  
0.55  
±1  
IOL = 2 mA  
3.0  
IOL = 8 mA  
4.5  
IOL = 16 mA  
Input current  
IIN  
0 to 5.5  
5.5  
µA  
µA  
VIN = 5.5 V or GND  
VO = VCC or GND  
2
Off-state output  
current  
IOZ  
*
±5  
Quiescent supply  
current  
ICC  
5.5  
0
20  
5
µA  
µA  
VIN = VCC or GND, IO = 0  
VI or VO = 0 V to 5.5 V  
Output leakage  
current  
IOFF  
Input capacitance  
CIN  
3.3  
3.3  
3.0  
5.5  
pF  
pF  
VI = VCC or GND  
VO = VCC or GND  
Output capacitance CO  
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.  
2. For I/O ports, the parameter IOZ includes the input leakage current.  
Rev.3.00 Jun. 24, 2004 page 4 of 9  
HD74LV245A  
Switching Characteristics  
VCC = 2.5 ± 0.2 V  
TO  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
FROM  
(Input)  
Item  
Symbol  
Unit  
Conditions  
(Output)  
Min Typ Max Min  
Max  
15.0  
18.0  
22.0  
26.0  
20.0  
25.0  
Propagation  
delay time  
tPLH  
tPHL  
8.3  
13.0 1.0  
ns  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
A or B  
B or A  
A or B  
A or B  
11.2 15.9 1.0  
11.8 19.9 1.0  
14.1 22.7 1.0  
11.8 18.1 1.0  
17.6 23.1 1.0  
Enable time  
tZH  
tZL  
ns  
ns  
OE  
Disable time  
tHZ  
tLZ  
OE  
VCC = 3.3 ± 0.3 V  
TO  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
FROM  
(Input)  
Item  
Symbol  
Unit  
Conditions  
(Output)  
Min Typ Max Min  
Max  
10.0  
13.5  
15.5  
19.0  
19.5  
22.0  
Propagation  
delay time  
tPLH  
tPHL  
5.9  
7.9  
8.2  
9.9  
9.6  
8.4  
1.0  
ns  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
A or B  
B or A  
A or B  
A or B  
11.9 1.0  
13.2 1.0  
16.7 1.0  
16.5 1.0  
Enable time  
tZH  
tZL  
ns  
ns  
OE  
Disable time  
tHZ  
tLZ  
OE  
13.9 19.8 1.0  
VCC = 5.0 ± 0.5 V  
TO  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
FROM  
(Input)  
Item  
Symbol  
Unit  
Conditions  
(Output)  
Min Typ Max Min  
Max  
6.5  
Propagation  
delay time  
tPLH  
tPHL  
4.3  
5.6  
5.7  
7.0  
7.8  
5.5  
7.5  
8.5  
1.0  
1.0  
1.0  
ns  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
A or B  
B or A  
A or B  
A or B  
8.5  
Enable time  
tZH  
tZL  
10.0  
12.0  
14.2  
16.0  
ns  
ns  
OE  
10.6 1.0  
12.8 1.0  
Disable time  
tHZ  
tLZ  
OE  
10.9 14.7 1.0  
Output-skew Characteristics  
CL = 50 pF  
Ta = 25°C  
Ta = –40 to 85°C  
Item  
Symbol  
VCC (V)  
Unit  
Min  
Max  
2.0  
1.5  
1.0  
Min  
Max  
Output skew  
tsk (O)  
2.3 to 2.7  
3.0 to 3.6  
4.5 to 5.5  
2.0  
1.5  
1.0  
ns  
Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted  
but not production tested.  
Rev.3.00 Jun. 24, 2004 page 5 of 9  
HD74LV245A  
Operating Characteristics  
CL = 50 pF  
Ta = 25°C  
Item  
Symbol  
VCC (V)  
Unit  
Test Conditions  
f = 10 MHz  
Min  
Typ  
20.0  
25.0  
Max  
Power dissipation capacitance CPD  
3.3  
5.0  
pF  
Noise Characteristics  
CL = 50 pF  
Ta = 25°C  
Min  
Item  
Symbol  
VCC (V)  
Unit  
Test Conditions  
Typ  
Max  
Quiet output, maximum  
dynamic VOL  
VOL (P)  
VOL (V)  
VOH (V)  
VIH (D)  
VIL (D)  
3.3  
0.5  
0.8  
V
Quiet output, minimum  
dynamic VOL  
3.3  
3.3  
3.3  
3.3  
–0.4  
2.9  
–0.8  
V
V
V
V
Quiet output, minimum  
dynamic VOH  
High-level dynamic input  
voltage  
2.31  
Low level dynamic input  
voltage  
0.99  
Test Circuit  
VCC  
VCC  
OE  
Input  
Output  
S1  
A1  
Pulse generator  
Zout  
= 50  
1 k  
OPEN  
GND  
VCC  
S2  
B1  
CL=  
15 or 50 pF  
DIR  
TEST  
S2  
OPEN  
GND  
VCC  
tPLH/tPHL  
tZH/tHZ  
tZL /tLZ  
Notes : 1. CL includes the probe and jig capacitance.  
2. A2B2 to A8B8 are identical to above load circuit.  
3. S1 : InputOutput change switch.  
Rev.3.00 Jun. 24, 2004 page 6 of 9  
HD74LV245A  
Waveform 1  
tr  
tf  
VCC  
0 V  
90%  
50% VCC  
90%  
50% VCC  
Input  
10%  
10%  
tPHL  
tPLH  
VOH  
In phase output  
50% VCC  
50% VCC  
VOL  
Wareform 2  
tf  
tr  
VCC  
0 V  
90%  
90%  
50% VCC  
10%  
50% VCC  
OE  
10%  
tZL  
tLZ  
VCC  
VOL  
VOH  
0 V  
50% VCC  
Waveform  
Waveform  
A
B
V
OL + 0.3 V  
tZH  
tHZ  
VOH0.3 V  
50% VCC  
Notes:  
1. Input waveform: PRR 1 MHz, Zo = 50 , tr 3 ns, tf 3 ns  
2. WaveformA is for an output with internal conditions such that the output is low except when disabled  
by the output control.  
3. WaveformB is for an output with internal conditions such that the output is high except when disabled  
by the output control.  
4. The output are measured one at a time with one transition per measurement.  
Rev.3.00 Jun. 24, 2004 page 7 of 9  
HD74LV245A  
Package Dimensions  
As of January, 2002  
Unit: mm  
12.6  
13 Max  
11  
10  
20  
1
+ 0.20  
7.80  
– 0.30  
0.80 Max  
1.15  
0˚ – 8˚  
1.27  
0.70 ± 0.20  
*0.40 ± 0.06  
0.15  
0.12 M  
Package Code  
JEDEC  
FP–20DAV  
JEITA  
Mass (reference value)  
Conforms  
0.31 g  
*Pd plating  
As of January, 2003  
Unit: mm  
12.8  
13.2 Max  
11  
10  
20  
1
+ 0.25  
– 0.40  
10.40  
0.935 Max  
1.45  
0˚ – 8˚  
+ 0.57  
– 0.30  
1.27  
0.70  
*0.40 ± 0.06  
0.15  
M
0.12  
Package Code  
JEDEC  
JEITA  
FP-20DBV  
Conforms  
*Ni/Pd/Au plating  
Mass (reference value)  
0.52 g  
Rev.3.00 Jun. 24, 2004 page 8 of 9  
HD74LV245A  
As of January, 2002  
Unit: mm  
6.50  
6.80 Max  
20  
11  
1
10  
0.65  
1.0  
*0.20 ± 0.05  
0.13  
M
6.40 ± 0.20  
0.65 Max  
0˚ – 8˚  
0.50 ± 0.10  
0.10  
Package Code  
JEDEC  
TTP–20DAV  
JEITA  
*Pd plating  
Mass (reference value)  
0.07 g  
Rev.3.00 Jun. 24, 2004 page 9 of 9  
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