HD74AC194T-EL [RENESAS]
AC SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, TTP-16DA;型号: | HD74AC194T-EL |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | AC SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, TTP-16DA 移位寄存器 |
文件: | 总8页 (文件大小:214K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HD74AC194
4-bit Bidirectional Unviersal Shift Register
REJ03D0259–0200Z
(Previous ADE-205-379 (Z))
Rev.2.00
Jul.16.2004
Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a
shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control
inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load,
shift right (in the direction Q0 toward Q3); shift left; inhibit clock (do nothing).
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0
and S1, high. The data are loaded into their respective flip-flops and appear at the out after the positive transition of
the clock input. During loading, serial data flow is inhibited. Shift right is accosynchronously with the rising
edge of the clock pulse when S0 is high and S1 is low. Serial date for this mothe shift right data input.
When S0 is low and S1 is high, data shifts left synchronously and new data s left serial input.
Clocking of the flip-flops is inhibited when both mode control inputs anputs should be
changed only when the clock input is high.
Features
•
•
•
Asynchronous Master Reset
Hole (Do Nothing) Mode
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
Package Typ
e Abbreviation Taping Abbreviation (Quantity)
HD74AC194FPEL SOP-16 pin (J
HD74AC194RPEL SOP-16 pi
P
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Notes: 1. Please consult thkage availability.
2. The packages ished from the conventional products by adding V at the end of
the packag
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC194
Pin Arrangement
1
2
3
4
5
6
7
8
16 VCC
MR
DSR
15 Q
0
1
2
3
P0
P1
P2
P3
14
13
Q
Q
12 Q
11 CP
10 S
1
0
DSL
GND
9
S
(Top view)
Logic Symbol
DSR
S0
S
Q2
Q3
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC194
Pin Names
S0, S1
P0 to P3
DSR
DSL
CP
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
MR
Q0 to Q3
Logic Diagram
D
SL
P3
P
2
P
1
P
0
DSR
S
S
0
1
D
C
C
D
C
D
C
C
Q
Q
CL CL
CL CL
CP
MR
Q1
Q0
Mode Select Table
SR
Output
Operating Mode
DSL
Pn
Q0
Q1
Q2
Q3
Reset
Hold
X
X
X
X
L
X
X
L
X
X
X
X
X
X
pn
L
L
L
L
H
H
H
H
H
q0
q1
q1
L
q1
q2
q2
q0
q0
p1
q2
q3
q3
q1
q1
p2
q3
L
Shift Left
L
L
H
X
X
X
H
q2
q2
p3
Shift Right
H
H
H
L
H
X
H
p0
Parallel Load
H
H
L
: HIGH Voltage Level
: LOW Voltage Level
pn (qn) : Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH
clock transition
X
: Immaterial
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC194
Timing Diagram
CP
Mode
S0
Control
Inputs
S1
MR
Parallel
Data
D
D
SH
SL
Inputs
H
L
P0
P1
P2
P3
Parallel
Data
H
L
Inputs
Q0
Q1
Q2
Outputs
Q3
Shift Right
Sh
Clear
Load
Clear
Absolute Maximum Ratings
Item
Supply voltage
Symb
Unit
Condition
VCC
I
V
DC input diode current
mA
mA
V
VI = –0.5V
VI = Vcc+0.5V
DC input voltage
+0.5
DC output diode current
mA
mA
V
VO = –0.5V
VO = Vcc+0.5V
DC output voltage
0.5 to Vcc+0.5
±50
DC output source or sink c
DC VCC or ground curre
Storage temperature
mA
mA
°C
±50
–65 to +150
Recommended Opeditions
Item
Symbol
Ratings
2 to 6
Unit
Condition
Supply voltage
VCC
V
Input and output voltage
Operating temperature
VI, VO
Ta
0 to VCC
–40 to +85
8
V
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
tr, tf
VCC = 3.0V
VCC = 4.5 V
VCC = 5.5 V
VIN 30% to 70% VCC
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC194
DC Characteristics
Item
Sym-
bol
Vcc
(V)
Ta = 25°C
Ta = –40 to
Unit
Condition
+85°C
min.
2.1
3.15
3.85
—
typ.
1.5
max.
—
min.
2.1
3.15
3.85
—
max.
—
Input Voltage
VIH
VIL
3.0
V
VOUT = 0.1 V or VCC –0.1 V
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
—
—
0.9
1.35
1.65
—
0.9
1.35
1.65
—
VOUT = 0.1 V or VCC –0.1 V
—
—
—
—
Output voltage
VOH
2.9
4.4
5.4
2.58
3.94
4.94
—
2.9
4.4
5.4
2.48
3.80
4.80
—
V
VIN = VIL or VIH
IOUT = –50 µA
—
—
—
—
—
—
VIN = VIL or VIH
IOH = –12 mA
—
—
—
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.002 0.1
0.001 0.1
0.001 0.1
0.1
0.1
0
N = VIL or VIH
= 50 µA
—
—
—
—
—
—
—
—
—
0.32
—
VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
—
0.32
0.32
±0.1
—
—
Input leakage
current
IIN
—
= VCC or GND
Dynamic output
current*
IOLD
IOHD
ICC
5.5
5.5
5.5
—
—
—
—
—
mA
µA
VOLD = 1.1 V
VOHD = 3.85 V
Quiescent supply
current
VIN = VCC or ground
*Maximum test duration 2.0 ms, one outp
AC Characteristics
+25°C
L = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Item
Maximum clock
frequency
n
5
Typ
—
Max
Min
Max
Unit
.3
5.0
3.3
5.0
65
MHz
ns
100
1.0
1.0
1.0
1.0
1.0
1.0
—
85
Propagation delay
CP to Qn
tPLH
tPHL
tPHL
—
—
—
—
—
—
13.0
10.0
1.0
1.0
1.0
1.0
1.0
1.0
15.0
11.5
15.0
11.5
12.5
9.0
Propagation delay
CP to Qn
13.0
10.0
10.5
8.0
ns
Propagation delay
MR to Qn
ns
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 7
HD74AC194
AC Operating Requirements
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Setup time, HIGH or LOW
Pn or DSR or DSL to CP
Hold time, HIGH or LOW
Pn or DSR or DSL to CP
Setup time, HIGH or LOW
Sn to CP
Symbol VCC (V)*1
Typ
Guaranteed Minimum
Unit
tsu
th
tsu
th
trec
tw
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
—
—
—
—
—
—
—
—
—
—
—
—
5.5
7.0
5.0
3.0
2.0
7.5
5.5
0.0
0.0
0.5
0.5
7.
ns
ns
ns
ns
ns
ns
4.0
2.0
1.5
6.0
4.5
0.0
0.0
0.5
0.5
5.5
4.5
Hold time, HIGH or LOW
Sn to CP
Recovery time
MR to CP
Pulse width
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Symbol
Typ
Condition
CIN
4.5
5 V
= 5.0 V
Power dissipation capacitance
CPD
1
Rev.2.00, Jul.16.2004, page 6 of 7
HD74AC194
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
orms
24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
+ 0.10
6.10
– 0.30
1.08
Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 7 of 7
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