HD74AC195 [RENESAS]
4-bit Parallel-Access Shift Register; 4位并行存取移位寄存器
| 型号： | HD74AC195 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4-bit Parallel-Access Shift Register |
| 文件： | 总8页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AC195
4-bit Parallel-Access Shift Register
REJ03D0260–0200Z
(Previous ADE-205-380 (Z))
Rev.2.00
Jul.16.2004
Description
This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct
overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q0 towards Q3.
Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low. The data is loaded into
the associated flip-flops and appears at the outputs after the positive transition of the CP input. During parallel loading,
serial data flow is inhibited. Serial shifting occurs synchronously when the PE input is high. Serial data for this mode
is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K oggle flip-flop as shown in the
function table.
Features
•
•
•
•
•
Shift Right and Parallel Load Capability
J-K (D-Type) Inputs to First Stage
Complement Output from Last Stage
Asynchronous Master Reset
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
Package Type
bbreviation Taping Abbreviation (Quantity)
HD74AC195FPEL SOP-16 pin (JEITA
HD74AC195RPEL SOP-16 pin (JE
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Notes: 1. Please consult the saavailability.
2. The packages witd from the conventional products by adding V at the end of
the package co
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC195
Pin Arrangement
1
2
3
4
5
6
7
8
16 VCC
MR
J
15 Q
0
1
2
3
3
K
14
13
Q
Q
D
D
D
D
0
1
2
3
12 Q
11 Q
10 CP
GND
9
PE
(Top view)
Logic Symbol
PE
J
3
2
Q3
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC195
Pin Names
CP
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input
Asynchronous Master Reset
J-K or D Type Serial Inputs
Outputs
D0 to D3
PE
MR
J, K
Q0 to Q3, Q3
Timing Diagram
CP
MR
J
K
PE
H
L
D0
D1
D2
H
L
D3
Q0
Q1
Q2
Q3
Serial S
Serial Shift
Clear
Mode Select-Function Table
Outputs
Q2
Operating Modes
Asynchronous Reset
Shift, Set First Stage
Shift, Reset First Stage
Shift, Toggle First Sta
Shift, Retain First Sta
Parallel Load
MR
Dn
Q0
Q1
Q3
Q3
L
L
X
X
X
X
X
dn
L
L
L
L
H
H
L
q0
q0
q0
q0
d1
q1
q1
q1
q1
d2
q2
q2
q2
q2
d3
q2
q2
q2
q2
d3
L
L
q0
q0
d0
H
X
X
H : HIGH Voltage Level
L
:
:
LOW Voltage Level
Immaterial
X
Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH
transition.
:
LOW-to-HIGH clock transition.
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC195
Logic Diagram
K
VCC
J
D
3
D
2
D
1
D0
V
CC
PE
CP
MR
Q3
Q3
Q2
Absolute Maximum Ratings
Item
Supply voltage
Sym
VC
Unit
Condition
V
DC input diode current
mA
mA
V
VI = –0.5V
VI = Vcc+0.5V
DC input voltage
+0.5
DC output diode current
mA
mA
V
VO = –0.5V
VO = Vcc+0.5V
DC output voltage
0.5 to Vcc+0.5
±50
DC output source or sink
DC VCC or ground curr
Storage temperature
mA
mA
°C
±50
–65 to +150
Recommended Operditions
Item
Symbol
Ratings
2 to 6
Unit
Condition
Supply voltage
VCC
V
Input and output voltage
Operating temperature
VI, VO
Ta
0 to VCC
–40 to +85
8
V
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
tr, tf
VCC = 3.0V
VCC = 4.5 V
VCC = 5.5 V
VIN 30% to 70% VCC
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC195
DC Characteristics
Item
Sym-
bol
Vcc
(V)
Ta = 25°C
Ta = –40 to
Unit
Condition
+85°C
min.
2.1
3.15
3.85
—
typ.
1.5
max.
—
min.
2.1
3.15
3.85
—
max.
—
Input Voltage
VIH
VIL
3.0
V
VOUT = 0.1 V or VCC –0.1 V
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
—
—
0.9
1.35
1.65
—
0.9
1.35
1.65
—
VOUT = 0.1 V or VCC –0.1 V
—
—
—
—
Output voltage
VOH
2.9
4.4
5.4
2.58
3.94
4.94
—
2.9
4.4
5.4
2.48
3.80
4.80
—
V
VIN = VIL or VIH
IOUT = –50 µA
—
—
—
—
—
—
VIN = VIL or VIH
IOH = –12 mA
—
—
—
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.002 0.1
0.001 0.1
0.001 0.1
0.1
0.1
0
N = VIL or VIH
= 50 µA
—
—
—
—
—
—
—
—
—
0.32
—
VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
—
0.32
0.32
±0.1
—
—
Input leakage
current
IIN
—
= VCC or GND
Dynamic output
current*
IOLD
IOHD
ICC
5.5
5.5
5.5
—
—
—
—
—
mA
µA
VOLD = 1.1 V
VOHD = 3.85 V
Quiescent supply
current
VIN = VCC or ground
*Maximum test duration 2.0 ms, one outp
AC Characteristics
+25°C
L = 50 pF
Typ
Ta = –40°C to +85°C
CL = 50 pF
Item
Maximum clock
frequency
n
5
Max
Min
Max
Unit
.3
5.0
3.3
5.0
3.3
5.0
—
—
65
—
—
MHz
ns
100
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
—
85
Propagation delay
CP to Qn or Q3
Propagation delay
CP to Qn or Q2
Propagation delay
MR to Q2
tPLH
tPHL
tPLH
tPHL
9.0
5.5
9.0
6.5
7.5
5.5
6.0
5.0
13.0
10.0
13.0
10.0
10.5
8.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
15.0
11.5
15.0
11.5
12.0
9.5
ns
ns
Propagaion delay
9.0
10.5
8.0
ns
MR to Qn
7.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 7
HD74AC195
AC Operating Requirements
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Setup time, HIGH or LOW
J, K or Dn to CP
Hold time, HIGH or LOW
J, K or Dn to CP
Setup time, HIGH or LOW
PE to CP
Symbol VCC (V)*1
Typ
Guaranteed Minimum
Unit
tsu
th
tsu
th
trec
tw
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.0
5.5
7.0
5.0
3.5
2.0
7.0
5.0
0.0
0.0
0.5
0.5
7.
ns
ns
ns
ns
ns
ns
2.0
4.0
2.0
1.5
5.0
4.0
0.0
0.0
0.5
0.5
5.5
4.5
–0.5
0.5
3.5
2.5
Hold time, HIGH or LOW
–2.0
–1.5
–1.5
–1.0
–3.0
–3.0
PE to CP
Recovery time
MR to CP
Pulse width
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Symbol
Typ
Condition
CIN
4.5
5 V
= 5.0 V
Power dissipation capacitance
CPD
1
Rev.2.00, Jul.16.2004, page 6 of 7
HD74AC195
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
orms
24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
+ 0.10
6.10
– 0.30
1.08
Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 7 of 7
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