HD74AC175AFPEL [RENESAS]

Quad D-Type Flip-Flop; 四D型触发器


型号：	HD74AC175AFPEL
厂家：	RENESAS TECHNOLOGY CORP
描述：	Quad D-Type Flip-Flop 四D型触发器触发器
文件：	总8页 (文件大小：206K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD74AC175

Quad D-Type Flip-Flop

REJ03D0257–0200Z

(Previous ADE-205-377 (Z))

Rev.2.00

Jul.16.2004

Description

The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock

and clear inputs are common. The information on the D inputs is stored during the Low-to-High clock transition. Both

true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of

the Clock or D inputs, when Low.

Features

•

Edge-Triggered D-Type Inputs

Buffered Positive Edge-Triggered Clock

Asynchronous Common Reset

True and Complement Output

Outputs Source/Sink 24 mA

•

Ordering Information

Part Name

Package Type

Package Code Package Abbreviation Taping Abbreviation (Quantity)

HD74AC175AFPEL SOP-16 pin (JEITA) FP-16DAV

HD74AC175ARPEL SOP-16 pin (JEDEC) FP-16DNV

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

ELL(2,000 pcs/reel)

HD74AC175TELL TSSOP-16 pin

TTP-16DAV

Notes: 1. Please consult the sales office for the above package availability.

2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of

the package code.

Pin Arrangement

16 VCC

15 Q

12 D

11 Q

10 Q

GND

(Top view)

Rev.2.00, Jul.16.2004, page 1 of 7

HD74AC175

Logic Symbol

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3

Pin Names

D₀to D₃

Data Inputs

Clock Pulse Input

Master Reset Input

True Outputs

Q₀to Q₃

Q₀to Q ₃Complement Outputs

Functional Description

The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock

and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the Low-to-High

clock (CP) transition, causing individual Q and Q outputs to follow. A Low input on the Master Reset (MR) will force

all Q outputs Low and Q outputs High independent of Clock or Data inputs. The HD74AC175 is useful for general

logic applications where a common Master Reset and Clock are acceptable.

Truth Table

Inputs

Outputs

@ t_n+1

@ t_n, MR = H

H : High Voltage Level

Low Voltage Level

t_n

Bit Time before Clock Pulse

: Bit Time after Clock Pulse

t_{n + 1}

Rev.2.00, Jul.16.2004, page 2 of 7

HD74AC175

Logic Diagram

MR CP D3

Q3Q3

Q2Q2

Q1Q1

Q0Q0

Please note that this diagram is provided only for the understanding of logic operations and should not be

used to estimate propagation delays.

Absolute Maximum Ratings

Item

Symbol

V_CC

Ratings

–0.5 to 7

Unit

Condition

V_I= –0.5V

Supply voltage

DC input diode current

I_IK

–20

V_I= Vcc+0.5V

DC input voltage

V_I

–0.5 to Vcc+0.5

DC output diode current

I_OK

–50

V_O= –0.5V

V_O= Vcc+0.5V

DC output voltage

V_O

–0.5 to Vcc+0.5

±50

DC output source or sink current

DC V_CCor ground current per output pin

Storage temperature

I_O

°C

I_CC, I_GND

Tstg

±50

–65 to +150

Recommended Operating Conditions

Item

Symbol

Ratings

2 to 6

Unit

Condition

Supply voltage

V_CC

Input and output voltage

Operating temperature

V_I, V_O

0 to V_CC

–40 to +85

°C

ns/V

Input rise and fall time

(except Schmitt inputs)

tr, tf

V_CC= 3.0V

V_CC= 4.5 V

V_CC= 5.5 V

V_IN30% to 70% V_CC

Rev.2.00, Jul.16.2004, page 3 of 7

HD74AC175

DC Characteristics

Item

Sym-

bol

Vcc

(V)

Ta = 25°C

Ta = –40 to

Unit

Condition

+85°C

min.

2.1

3.15

3.85

—

typ.

1.5

max.

—

min.

2.1

3.15

3.85

—

max.

—

Input Voltage

V_IH

V_IL

3.0

V_OUT= 0.1 V or V_CC–0.1 V

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

2.25

2.75

1.50

2.25

2.75

2.99

4.49

5.49

—

0.9

1.35

1.65

—

0.9

1.35

1.65

—

V_OUT= 0.1 V or V_CC–0.1 V

—

Output voltage

V_OH

2.9

4.4

5.4

2.58

3.94

4.94

—

2.9

4.4

5.4

2.48

3.80

4.80

—

V_IN= V_ILor V_IH

I_OUT= –50 µA

—

V_IN= V_ILor V_IH

I_OH= –12 mA

—

I_OH= –24 mA

—

V_OL

0.002 0.1

0.001 0.1

0.1

0.37

±1.0

V_IN= V_ILor V_IH

I_OUT= 50 µA

—

0.32

—

V_IN= V_ILor V_IH

I_OL= 12 mA

I_OL= 24 mA

—

0.32

±0.1

—

Input leakage

current

I_IN

—

µA

V_IN= V_CCor GND

Dynamic output

current*

I_OLD

I_OHD

I_CC

5.5

—

µA

V_OLD= 1.1 V

—

–75

—

V_OHD= 3.85 V

Quiescent supply

current

8.0

V_IN= V_CCor ground

*Maximum test duration 2.0 ms, one output loaded at a time.

AC Characteristics

Ta = +25°C

C_L= 50 pF

Typ

Ta = –40°C to +85°C

C_L= 50 pF

Item

Maximum clock

frequency

Symbol V_CC(V)*¹

Min

149

Max

Min

Max

Unit

f_max

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

—

139

187

1.0

—

MHz

187

1.0

—

Propagation delay

CP to Q_nor Q_n

Propagation delay

CP to Q_nor Q_n

Propagation delay

MR to Q_n

t_PLH

t_PHL

t_PLH

t_PHL

9.5

7.0

8.5

6.0

7.5

5.5

8.5

6.0

12.0

9.0

13.5

9.5

13.0

9.5

14.5

10.5

13.5

10.0

12.5

9.0

12.5

9.0

Propagation delay

11.0

8.5

MR to Q_n

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

Rev.2.00, Jul.16.2004, page 4 of 7

HD74AC175

AC Operating Requirements

Ta = –40°C

to +85°C

C_L= 50 pF

Ta = +25°C

C_L= 50 pF

Item

Set-up time, HIGH or LOW

D_nto CP

Symbol V_CC(V)*¹

Typ

Guaranteed Minimum

Unit

t_su

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

2.0

1.0

4.5

3.0

1.0

4.5

3.5

5.0

3.5

0.0

3.0

1.0

4.5

3.5

4.5

3.5

0.0

Hold time, HIGH or LOW

D_nto CP

t_h

CP pulse width HIGH or LOW t_w

2.5

2.0

2.5

2.0

–2.0

–1.0

MR pulse width, LOW

t_w

Recovery time MR to CP

t_rec

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

Capacitance

Item

Input capacitance

Symbol

Typ

Unit

Condition

C_IN

4.5

V_CC= 5.5 V

V_CC= 5.0 V

Power dissipation capacitance

C_PD

45.0

Rev.2.00, Jul.16.2004, page 5 of 7

HD74AC175

Package Dimensions

As of January, 2003

Unit: mm

10.06

10.5 Max

+ 0.20

7.80

– 0.30

0.80 Max

1.15

0˚ – 8˚

1.27

0.70 ± 0.20

*0.40 ± 0.06

0.15

0.12

Package Code

JEDEC

FP-16DAV

—

JEITA

Mass (reference value)

Conforms

0.24 g

*Ni/Pd/Au plating

As of January, 2003

Unit: mm

9.9

10.3 Max

1.27

+ 0.10

6.10

– 0.30

1.08

0.635 Max

0˚ – 8˚

+ 0.67

0.60

– 0.20

*0.40 ± 0.06

0.15

0.25

Package Code

JEDEC

JEITA

FP-16DNV

Conforms

0.15 g

*Ni/Pd/Au plating

Mass (reference value)

Rev.2.00, Jul.16.2004, page 6 of 7

HD74AC175

As of January, 2003

Unit: mm

5.00

5.30 Max

0.65

0.13 M

0.65 Max

1.0

*0.20 ± 0.05

6.40 ± 0.20

0˚ – 8˚

0.50 ± 0.10

0.10

Package Code

JEDEC

TTP-16DAV

—

JEITA

—

*Ni/Pd/Au plating

Mass (reference value)

0.05 g

Rev.2.00, Jul.16.2004, page 7 of 7

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

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Colophon .1.0

HD74AC175AFPEL [RENESAS]

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