HB28J1000CFC [RENESAS]
512MX16 FLASH 3.3V PROM CARD, 250ns, XMA50, CARD-50;
| 型号： | HB28J1000CFC |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 512MX16 FLASH 3.3V PROM CARD, 250ns, XMA50, CARD-50 可编程只读存储器 内存集成电路 |
| 文件： | 总67页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HB28J1000CFC/HB28J512CFC
HB28J256CFC/HB28J128CFC
CompactFlash
1 GByte/512 MByte/256 MByte/128 MByte
REJ03C0205-0100Z
Rev. 1.00
Mar. 16. 2004
Description
HB28J1000CFC, HB28J512CFC, HB28J256CFC, HB28J128CFC are CompactFlash. This card complies
with CompactFlash specification (CFA2.0), and is suitable for the usage of data storage memory medium
for PC or any other electric equipment and digital still camera. This card is equipped with 0.13 µm CMOS
1Giga bit AG-AND Flash memory. This card is suitable for ISA (Industry Standard Architecture) bus
interface standard, and read/write unit is 1 sector (512 bytes) sequential access. By using this card it is
possible to operate good performance for the system which have CompactFlash slots.
Notes: 1. CompactFlash is a trademark of SanDisk Corporation and is licensed royalty-free to the CFA
which in turn will license it royalty-free to CFA members.
*CFA: CompactFlash Association.
2. These products are authorized for use in consumer applications such as digital still cameras.
Therefore, please contact Renesas Technology’s Sales Dept. before using these products in
industrial applications.
Features
•
CompactFlash specification standard
50 pin two pieces connector and Type I (3.3 mm)
3.3 V / 5 V single power supply operation
Card density is 1 Giga bytes maximum
This card is equipped with 0.13 µm CMOS 1 Giga bit AG-AND Flash memory
3 variations of mode access
•
•
•
Memory card mode
I/O card mode
True IDE mode
PIO mode4
Rev.1.00, Mar.16.2004, page 1 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
•
•
•
•
Internal self-diagnostic program operates at VCC power on
High reliability based on internal ECC (Error Correcting Code) function
Auto sleep mode
Data write is 100,000 cycles/block.*1
Note: 1. One block consists of eight sectors (512 byte × 8).
Card Line Up*1
Total sectors/ Sectors/ Number of Number of
Type No.
Card density Capacity*4
card*3
1,025,482,752 byte 2,002,896
512,483,328 byte 1,000,944
256,204,800 byte 500,400
128,188,416 byte 250,368
track*2
63
head
cylinder
1987
993
HB28J1000CFC 1 GB
HB28J512CFC 512 MB
HB28J256CFC 256 MB
HB28J128CFC 128 MB
16
63
16
48
15
695
32
8
978
Notes: 1. These data are written in ID.
2. Total tracks = number of head × number of cylinder.
3. Total sectors/card = sectors/track × number of head × number of cylinder.
4. It is the logical address capacity including the area which is used for file system.
Rev.1.00, Mar.16.2004, page 2 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Card Pin Assignment
Memory card mode
I/O card mode
True IDE mode
Pin No.
1
Signal name
GND
D3
I/O
Signal name
GND
D3
I/O
I/O
I/O
I/O
I/O
I/O
I
Signal name
GND
D3
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
2
3
D4
D4
D4
4
D5
D5
D5
5
D6
D6
D6
6
D7
D7
D7
7
-CE1
A10
-OE
A9
-CE1
A10
-OE
A9
-CS0
A10
-ATASEL
A9
8
I
I
I
9
I
I
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I
I
I
A8
I
A8
I
A8
I
A7
I
A7
I
A7
I
VCC
A6
I
VCC
A6
I
VCC
A6
I
A5
I
A5
I
A5
I
A4
I
A4
I
A4
I
A3
I
A3
I
A3
I
A2
I
A2
I
A2
I
A1
I
A1
I
A1
I
A0
I
A0
I
A0
I
D0
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
D0
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
D0
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
D1
D1
D1
D2
D2
D2
WP
-CD2
-CD1
D11
D12
D13
D14
-IOIS16
-CD2
-CD1
D11
D12
D13
D14
-IOIS16
-CD2
-CD1
D11
D12
D13
D14
Rev.1.00, Mar.16.2004, page 3 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Memory card mode
I/O card mode
Signal name
D15
True IDE mode
Signal name
D15
Pin No.
31
Signal name
D15
I/O
I/O
I/O
I
I/O
I/O
I
I/O
I
32
-CE2
-CE2
-CS1
33
-VS1
O
I
-VS1
O
I
-VS1
O
I
34
-IORD
-IOWR
-WE
-IORD
-IOWR
-WE
-IORD
-IOWR
-WE
35
36
37
38
I
I
I
I
I
I
RDY/-BSY
VCC
O
I
-IREQ
VCC
O
I
INTRQ
VCC
O
I
39
-CSEL
-VS2
-CSEL
-VS2
-CSEL
-VS2
40
O
I
O
I
O
I
41
RESET
-WAIT
-INPACK
-REG
BVD2
BVD1
D8
RESET
-WAIT
-INPACK
-REG
-RESET
IORDY
RFU*1
RFU*1
-DASP
-PDIAG
D8
42
43
O
O
I
O
O
I
O
O
I
44
45
46
47
48
49
I/O
I/O
I/O
I/O
I/O
-SPKR
-STSCHG
D8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D9
D9
D9
D10
D10
D10
50
GND
GND
GND
Note: 1. RFU is Reserved for Future Use.
Rev.1.00, Mar.16.2004, page 4 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Card Pin Explanation
Signal name
Direction Pin No.
Description
A10 to A0
I
8, 10, 11, 12, 14, Address bus is A10 to A0. A10 is MSB and A0 is
(PC Card Memory
mode)
15, 16, 17, 18,
19, 20
LSB.
A10 to A0
(PC Card I/O mode)
A2 to A0
(True IDE mode)
18, 19, 20
46
Address bus is A10 to A0. Only A2 to A0 are used,
A10 to A3 should be grounded by the host.
BVD1
(PC Card Memory
mode)
I/O
I/O
BVD1 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-STSCHG
(PC Card I/O mode)
-STSCHG is used for changing the status of
Configuration and status register in attribute area.
-PDIAG
(True IDE mode)
-PDIAG is the Pass Diagnostic signal in
Master/Slave handshake protocol.
BVD2
(PC Card Memory
mode)
45
BVD2 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-SPKR
(PC Card I/O mode)
-SPKR outputs speaker signals. This output line is
constantly driven to a high state since this product
does not support the audio function.
-DASP
(True IDE mode)
-DASP is the Disk Active/Slave Present signal in the
Master/Slave handshake protocol.
-CD1, -CD2
(PC Card Memory
mode)
O
26, 25
-CD1 and -CD2 are the card detection signals. -CD1
and -CD2 are connected to ground in this card, so
host can detect that the card is inserted or not.
-CD1, -CD2
(PC Card I/O mode)
-CD1, -CD2
(True IDE mode)
-CE1, -CE2
(PC Card Memory
mode)
I
7, 32
-CE1 and -CE2 are low active card select signals.
Byte/Word/Odd byte modes are defined by
combination of -CE1, -CE2 and A0.
Card Enable
-CE1, -CE2
(PC Card I/O mode)
Card Enable
-CS0, -CS1
(True IDE mode)
-CS1 is used for select the Alternate Status Register
and the Device Control Register -CS0 is the chip
select for the other task file registers.
Rev.1.00, Mar.16.2004, page 5 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Signal name
Direction Pin No.
Description
-CSEL
I
39
This signal is not used.
(PC Card Memory
mode)
-CSEL
(PC Card I/O mode)
-CSEL
(True IDE mode)
This signal is used to configure this device as a
Master or a Slave when configured in the True IDE
mode. When this pin is grounded, this device is
configured as a Master. When the pin is open, this
device is configured as a Slave.
D15 to D0
I/O
31, 30, 29, 28,
Data bus is D15 to D0. D0 is the LSB of the even
(PC Card Memory
mode)
27, 49, 48, 47, 6, byte of the word. D8 is the LSB of the odd byte of
5, 4, 3, 2, 23, 22, the word.
21
D15 to D0
(PC Card I/O mode)
D15 to D0
(True IDE mode)
GND
1, 50
Ground
(PC Card Memory
mode)
GND
(PC Card I/O mode)
GND
(True IDE mode)
-INPACK
(PC Card Memory
mode)
O
43
This signal is not used and should not be connected
at the host.
-INPACK
(PC Card I/O mode)
Input Acknowledge
This signal is asserted low by this card when the card
is selected and responding to an I/O read cycle at
the address that is on the address bus during -CE
and
-IORD are low. This signal is used for the input data
buffer control.
RFU
(True IDE mode)
This signal is not used and should not be connected
at the host.
-IORD
I
34
This signal is not used.
(PC Card Memory
mode)
-IORD
(PC Card I/O mode)
-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until I/O
card interface setting up.
-IORD
(True IDE mode)
-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until
True IDE interface setting up.
Rev.1.00, Mar.16.2004, page 6 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Signal name
Direction Pin No.
Description
-IOWR
I
35
This signal is not used.
(PC Card Memory
mode)
-IOWR
(PC Card I/O mode)
-IOWR is used for control of data write in I/O task file
area. This card does not respond to -IOWR until I/O
card interface setting up.
-IOWR
(True IDE mode)
-IOWR is used for control of data write in I/O task file
area. This card does not respond to -IOWR until
True IDE interface setting up.
-OE
I
9
-OE is used for the control of reading register’s data
in attribute area or task file area.
(PC Card Memory
mode)
-OE
-OE is used for the control of reading register’s data
in attribute area.
(PC Card I/O mode)
-ATASEL
(True IDE mode)
To enable True IDE mode this input should be
grounded by the host.
RDY/-BSY
(PC Card Memory
mode)
O
37
The signal is RDY/-BSY pin. RDY/-BSY pin turns low
level during the card internal initialization operation at
VCC applied or reset applied, so next access to the
card should be after the signal turned high level.
-IREQ
(PC Card I/O mode)
This signal is active low -IREQ pin. The signal of low
level indicates that the card is requesting software
service to host, and high level indicates that the card
is not requesting.
INTRQ
(True IDE mode)
This signal is the active high Interrupt Request to the
host.
-REG
(PC Card Memory
mode)
I
44
-REG is used during memory cycles to distinguish
between task file and attribute memory accesses.
High for task file, Low for attribute memory is
accessed.
Attribute memory select
-REG
(PC Card I/O mode)
-REG is constantly low when task file or attribute
memory is accessed.
RFU
(True IDE mode)
This input signal is not used and should be
connected to VCC by the host.
Rev.1.00, Mar.16.2004, page 7 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Signal name
Direction Pin No.
Description
RESET
(PC Card Memory
mode)
I
41
This signal is active high RESET pin. If this signal is
asserted high, the card internal initialization begins to
operate. During the card internal initialization
RDY/-BSY is low. After the card internal initialization
RDY/-BSY is high.
RESET
(PC Card I/O mode)
This signal is active high RESET pin. If this signal is
asserted high, the card internal initialization begins to
operate. In this mode, RDY/-BSY signal cannot be
used, so using Status Register the Ready/Busy
status can be confirmed.
-RESET
(True IDE mode)
This signal is active low -RESET pin. If this signal is
asserted low, all the registers in this card are reset.
In this mode, RDY/-BSY signal cannot be used, so
using status register the Ready/Busy status can be
confirmed.
VCC
(PC Card Memory
mode)
O
O
I
13, 38
33, 40
42
+5 V, +3.3 V power.
VCC
(PC Card I/O mode)
VCC
(True IDE mode)
-VS1, -VS2
(PC Card Memory
mode)
These signals are intended to notify VCC
requirement to host. -VS1 is held grounded and -
VS2 is nonconnected in this card.
-VS1, -VS2
(PC Card I/O mode)
-VS1, -VS2
(True IDE mode)
-WAIT
(PC Card Memory
mode)
This signal is active low -WAIT pin. In this card this
signal is constantly high level.
-WAIT
(PC Card I/O mode)
IORDY
(True IDE mode)
This output signal may be used as IORDY. In this
card this signal is constantly high impedance.
-WE
36
-WE is used for the control of writing register’s data
in attribute memory area or task file area.
(PC Card Memory
mode)
-WE
-WE is used for the control of writing register’s data
in attribute memory area.
(PC Card I/O mode)
-WE
(True IDE mode)
This input signal is not used and should be
connected to VCC by the host.
Rev.1.00, Mar.16.2004, page 8 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Signal name
Direction Pin No.
24
Description
WP
O
WP is held low because this card does not have write
protect switch.
(PC Card Memory
mode)
Write Protect
-IOIS16
(PC Card I/O mode)
-IOIS16 is asserted when task file registers are
accessed in 16-bit mode.
-IOIS16
(True IDE mode)
This output signal is asserted low when this device is
expecting a word data transfer cycle. Initial mode is
16-bit. If the user issues a Set Feature Command to
put the device in Byte access mode, the card permits
8-bit accesses.
Rev.1.00, Mar.16.2004, page 9 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Card Block Diagram
internal VCC
V
CC
GND
A0 to A10
Reset IC
X'tal
-CE1,-CE2
-OE/-ATASEL
-WE
-IORD
-IOWR
-REG
Flash
memory
bus
RESET/-RESET
-CSEL
Controller
Flash memory
D0 to D15
BVD1/-STSCHG/-PDIAG
BVD2/-SPKR/-DASP
Control signal
RDY/-BSY/-IREQ/INTRQ
WP/-IOIS16
-INPACK
-WAIT/IORDY
-VS1
-VS2
OPEN
-CD1
-CD2
Note: -CE1, -CE2, -OE, -WE, -IORD, -IOWR, -REG, RESET, -CSEL, -PDIAG, -DASP pins are
pulled up in card.
-CE1, -CE2, -OE, -WE, -IORD, -IOWR, -REG pins are schmitt trigger type input buffer.
Rev.1.00, Mar.16.2004, page 10 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Card Function Explanation
Register construction
•
Attribute region
Configuration register
•
•
•
•
Configuration Option register
Configuration and Status register
Pin Replacement register
Socket and Copy register
CIS (Card Information Structure)
Task File region
•
Data register
Error register
Feature register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Drive Head register
Status register
Alternate Status register
Command register
Device Control register
Drive Address register
Rev.1.00, Mar.16.2004, page 11 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Host access specifications
1. Attribute access specifications
When CIS-ROM region or Configuration register region is accessed, read and write operations are
executed under the condition of -REG = “L” as follows. That region can be accessed by
Byte/Word/Odd-byte modes which are defined by PC card standard specifications.
Attribute Read Access Mode
Mode
-REG
-CE2
-CE1
A0
×
-OE
×
-WE
×
D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
L
L
L
L
H
H
H
L
H
L
High-Z
High-Z
High-Z
invalid
invalid
High-Z
L
L
H
even byte
invalid
L
H
×
L
H
Word access (16-bit)
Odd byte access (8-bit)
Note: ×: L or H
L
L
H
even byte
High-Z
L
H
×
L
H
Attribute Write Access Mode
Mode
-REG
-CE2
-CE1
A0
×
-OE
×
-WE
D8 to D15 D0 to D7
Don’t care Don’t care
Don’t care even byte
Don’t care Don’t care
Don’t care even byte
Don’t care Don’t care
Standby mode
Byte access (8-bit)
×
L
L
L
L
H
H
H
L
H
L
×
L
L
L
L
L
H
L
H
×
H
Word access (16-bit)
Odd byte access (8-bit)
Note: ×: L or H
L
H
L
H
×
H
Attribute Access Timing Example
A0 to A10
-REG
-CE2/-CE1
-OE
-WE
D0 to D15
Dout
Din
read cycle
write cycle
Rev.1.00, Mar.16.2004, page 12 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
2. Task File register access specifications
There are two cases of Task File register mapping, one is mapped I/O address area, and the other is
mapped Memory address area. Each case of Task File register read and write operations are executed
under the condition as follows. That area can be accessed by Byte/Word/Odd Byte modes which are
defined by PC card standard specifications.
(1) I/O address map
Task File Register Read Access Mode (1)
Mode
-REG -CE2 -CE1 A0
-IORD -IOWR -OE
-WE D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
L
L
L
H
H
H
L
H
L
×
L
H
×
×
×
L
L
L
L
×
×
×
High-Z
High-Z
High-Z
High-Z
H
H
H
H
H
H
H
H
H
H
H
H
even byte
odd byte
L
Word access (16-bit)
L
odd byte even byte
odd byte High-Z
Odd byte access (8-bit) L
L
H
Note: ×: L or H
Task File Register Write Access Mode (1)
Mode
-REG -CE2 -CE1 A0
-IORD -IOWR -OE
-WE D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
L
L
L
H
H
H
L
H
L
×
L
H
×
×
×
×
L
L
L
L
×
×
Don’t care Don’t care
Don’t care even byte
Don’t care odd byte
odd byte even byte
odd byte Don’t care
H
H
H
H
H
H
H
H
H
H
H
H
L
Word access (16-bit)
L
Odd byte access (8-bit) L
L
H
Note: ×: L or H
Task File Register Access Timing Example (1)
A0 to A10
-REG
-CE2/-CE1
-IORD
- IOWR
D0 to D15
Dout
Din
read cycle
write cycle
Rev.1.00, Mar.16.2004, page 13 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
(2) Memory address map
Task File Register Read Access Mode (2)
Mode
-REG -CE2 -CE1 A0
-OE
×
-WE -IORD -IOWR D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
H
H
H
L
H
L
×
L
H
×
×
×
×
×
High-Z
High-Z
High-Z
High-Z
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
even byte
odd byte
L
L
Word access (16-bit)
L
L
odd byte even byte
odd byte High-Z
Odd byte access (8-bit) H
L
H
L
Note: ×: L or H
Task File Register Write Access Mode (2)
Mode
-REG -CE2 -CE1 A0
-OE
×
-WE -IORD -IOWR D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
H
H
H
L
H
L
×
L
H
×
×
×
L
L
L
L
×
×
Don’t care Don’t care
Don’t care even byte
Don’t care odd byte
odd byte even byte
odd byte Don’t care
H
H
H
H
H
H
H
H
H
H
H
H
L
H
Word access (16-bit)
L
H
Odd byte access (8-bit) H
L
H
H
Note: ×: L or H
Task File Register Access Timing Example (2)
A0 to A10
-REG
-CE2/-CE1
-OE
-WE
D0 to D15
Dout
Din
read cycle
write cycle
Rev.1.00, Mar.16.2004, page 14 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
3. True IDE Mode
The card can be configured in a True IDE mode of operation. This card is configured in this mode only
when the -OE input signal is asserted GND by the host. In this True IDE mode Attribute Registers are
not accessible from the host. Only I/O operation to the task file and data register is allowed. If this
card is configured during power on sequence, data register is accessed in word (16-bit). The card
permits 8-bit accesses if the user issues a Set Feature Command to put the device in 8-bit mode.
True IDE Mode Read I/O Function
Mode
-CS1
-CS0
A0 to A2 -IORD
-IOWR
D8 to D15 D0 to D7
Invalid mode
L
L
×
×
×
L
L
L
×
High-Z
High-Z
odd byte
High-Z
High-Z
High-Z
Standby mode
H
H
L
H
L
×
×
High-Z
Data register access
Alternate status access
Other task file access
Note: ×: L or H
0
H
H
H
even byte
status out
data
H
L
6H
1-7H
H
True IDE Mode Write I/O Function
Mode
-CS1
-CS0
A0 to A2 -IORD
-IOWR
D8 to D15 D0 to D7
don’t care don’t care
don’t care don’t care
Invalid mode
L
L
×
×
×
×
L
L
L
Standby mode
H
H
L
H
L
×
×
Data register access
Control register access
Other task file access
Note: ×: L or H
0
H
H
H
odd byte
even byte
H
L
6H
1-7H
don’t care control in
don’t care data
H
True IDE Mode I/O Access Timing Example
A0 to A2
-CS
-IORD
-IOWR
-IOIS16
D0 to D15
Dout
Din
read cycle
write cycle
Rev.1.00, Mar.16.2004, page 15 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Configuration register specifications
This card supports four Configuration registers for the purpose of the configuration and observation of this
card. These registers can be used in memory card mode and I/O card mode. In True IDE mode, these
registers cannot be used.
1. Configuration Option register (Address 200H)
This register is used for the configuration of the card configuration status and for the issuing soft reset
to the card.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SRESET
LevlREQ
INDEX
Note: initial value: 00H
Name
R/W Function
SRESET
(HOST->)
R/W Setting this bit to “1”, places the card in the reset state (Card Hard Reset). This
operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to “0”,
places the card in the reset state of Hard Reset (This bit is set to “0” by Hard Reset) .
Card configuration status is reset and the card internal initialized operation starts when
Card Hard Reset is executed, so next access to the card should be the same sequence
as the power on sequence.
LevlREQ
(HOST->)
R/W This bit sets to “0” when pulse mode interrupt is selected, and “1” when level mode
interrupt is selected.
INDEX
(HOST->)
R/W This bit is used for select operation mode of the card as follows.
When Power on, Card Hard Reset and Soft Reset, this data is “000000” for the purpose
of Memory card interface recognition.
INDEX bit assignment
INDEX bit
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
Card mode
Task File register address
Mapping mode
Memory card 0H to FH, 400H to 7FFH
memory mapped
I/O card
I/O card
I/O card
xx0H to xxFH
contiguous I/O mapped
primary I/O mapped
secondary I/O mapped
1F0H to 1F7H, 3F6H to 3F7H
170H to 177H, 376H to 377H
Rev.1.00, Mar.16.2004, page 16 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
2. Configuration and Status register (Address 202H)
This register is used for observing the card state.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CHGED
SIGCHG
IOIS8
0
0
PWD
INTR
0
Note: initial value: 00H
Name
R/W Function
CHGED
(CARD->)
R
This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to “1”. When
CHGED bit is set to “1”, -STSCHG pin is held “L” at the condition of SIGCHG bit set to
“1” and the card configured for the I/O interface.
SIGCHG
(HOST->)
R/W This bit is set or reset by the host for enabling and disabling the status-change signal (-
STSCHG pin). When the card is configured I/O card interface and this bit is set to “1”, -
STSCHG pin is controlled by CHGED bit. If this bit is set to “0”, -STSCHG pin is kept
“H”.
IOIS8
(HOST->)
R/W The host sets this field to “1” when it can provide I/O cycles only with on 8-bit data bus
(D7 to D0).
PWD
(HOST->)
R/W When this bit is set to “1”, the card enters sleep state (Power Down mode). When this
bit is reset to “0”, the card transfers to idle state (active mode). RRDY/-BSY bit on Pin
Replacement Register becomes BUSY when this bit is changed. RRDY/-BSY will not
become Ready until the power state requested has been entered. This card
automatically powers down when it is idle, and powers back up when it receives a
command.
INTR
(CARD->)
R
This bit indicates the internal state of the interrupt request. This bit state is available
whether I/O card interface has been configured or not. This signal remains true until
the condition which caused the interrupt request has been serviced. If interrupts are
disabled by the -IEN bit in the Device Control Register, this bit is a zero.
Rev.1.00, Mar.16.2004, page 17 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
3. Pin Replacement register (Address 204H)
This register is used for providing the signal state of -IREQ signal when the card configured I/O card
interface.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
CRDY/-BSY 0
1
1
RRDY/-BSY 0
Note: initial value: 0CH
Name
CRDY/-BSY R/W This bit is set to “1” when the RRDY/-BSY bit changes state. This bit may also be
(HOST->) written by the host.
RRDY/-BSY R/W When read, this bit indicates +READY pin states. When written, this bit is used for
(HOST->) CRDY/-BSY bit masking.
R/W Function
4. Socket and Copy register (Address 206H)
This register is used for identification of the card from the other cards. Host can read and write this
register. This register should be set by host before this card’s Configuration Option register set.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
DRV#
0
0
0
0
Note: initial value: 00H
Name
R/W Function
DRV#
(HOST->)
R/W These fields are used for the configuration of the plural cards. When host configures
the plural cards, written the card’s copy number in this field. In this way, host can
perform the card’s master/slave organization.
Rev.1.00, Mar.16.2004, page 18 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
CIS informations
CIS informations are defined as follows. By reading attribute address from “0000 H”, card CIS
informations can be confirmed.
Address Data 7
6
5
4
3
2
1
0
Description of contents
Device info tuple
CIS function
Tuple code
000H 01H CISTPL_DEVICE
002H 04H TPL_LINK
Link length is 4 byte
Link to next tuple
004H DFH Device type
W Device speed Device type = DH: I/O device Device type, WPS, speed
WPS = 1: No WP
P
S
Device speed = 7: ext speed
006H 4AH EXT Speed
mantissa
Speed
exponent
400 ns if no wait
Extended speed
008H 01H 1x
2k units
2k byte of address space
End of device
Device size
END marker
00AH FFH List end marker
00CH 1CH CISTPL_DEVICE_OC
Other conditions device info Tuple code
tuple
00EH 04H TPL_LINK
Link length is 4 bytes
Link to next tuple
Other conditions info field
010H 02H EXT Reserved
012H D9H Device type
VCC
MWAIT 3 V, wait is not used
W Device speed Device type = DH: I/O device Device type, WPS, speed
P
S
WPS = 1: No WP
Device speed = 1: 250 ns
014H 01H 1x
2k units
2k byte of address space
End of device
Device size
END marker
016H FFH List end marker
018H 18H CISTPL_JEDEC_C
01AH 02H TPL_LINK
JEDEC ID common memory Tuple code
Link length is 2 bytes Link to next tuple
01CH DFH PCMCIA’s manufacturer’s JEDEC Manufacturer’s ID code
ID code
JEDEC ID of PC Card ATA
01EH 01H PCMCIA JEDEC device code
020H 20H CISTPL_MANFID
022H 04H TPL_LINK
2nd byte of JEDEC ID
Manufacturer’s ID code
Link length is 4 bytes
Tuple code
Link to next tuple
024H 07H Low byte of PCMCIA
manufacturer’s code
HITACHI JEDEC
manufacturer’s ID
Low byte of manufacturer’s
ID code
026H 00H High byte of PCMCIA
manufacturer’s code
Code of 0 because other byte High byte of manufacturer’s
is JEDEC 1 byte
manufacture’s ID
ID code
028H 00H Low byte of product code
02AH 00H High byte of product code
HITACHI code for PC CARD Low byte of product code
ATA
High byte of product code
Rev.1.00, Mar.16.2004, page 19 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
02CH 15H CISTPL_VERS_1
02EH 15H TPL_LINK
030H 04H TPPLV1_MAJOR
032H 01H TPPLV1_MINOR
034H 48H
Level 1 version/product info Tuple code
Link length is 15h bytes
Link to next tuple
PCMCIA2.0/JEIDA4.1
Major version
Minor version
Info string 1
PCMCIA2.0/JEIDA4.1
‘ H ’
036H 49H
‘ I ’
038H 54H
‘ T ’
03AH 41H
‘ A ’
03CH 43H
‘ C ’
03EH 48H
‘ H ’
040H 49H
‘ I ’
042H 00H
Null terminator
044H 46H
‘ F ’
Info string 2
046H 4CH
‘ L ’
048H 41H
‘ A ’
04AH 53H
‘ S ’
04CH 48H
‘ H ’
04EH 00H
Null terminator
‘ 5 ’
050H 35H
Vender specific strings
052H 2EH
‘ . ’
054H 30H
‘ 0 ’
056H 00H
Null terminator
End of device
Function ID tuple
Link length is 2 bytes
058H FFH List end marker
05AH 21H CISTPL_FUNCID
05CH 02H TPL_LINK
END marker
Tuple code
Link to next tuple
05EH 04H TPLFID_FUNCTION = 04H
Disk function, may be silicon, PC card function code
may be removable
060H 01H Reserved R P
R = 0: No BIOS ROM
P = 1: Configure card at
power on
System initialization byte
Rev.1.00, Mar.16.2004, page 20 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
Function extension tuple
Link length is 2 bytes
CIS function
062H 22H CISTPL_FUNCE
064H 02H TPL_LINK
Tuple code
Link to next tuple
Extension tuple type for disk
Interface type
066H 01H Disk function extension tuple type Disk interface type
068H 01H Disk interface type
06AH 22H CISTPL_FUNCE
06CH 03H TPL_LINK
PC card ATA interface
Function extension tuple
Link length is 3 bytes
Tuple code
Link to next tuple
Extension tuple type for disk
06EH 02H Disk function extension tuple type Single drive
070H 0CH Reserved D U S
V
No VPP, silicon, single drive Basic ATA option parameters
V = 0: No VPP required
S = 1: Silicon
byte 1
U = 1: Unique serial #
D = 0: Single drive on card
072H 0FH
R
I
E
N P3 P2 P1 P0
P0: Sleep mode supported Basic ATA option parameters
P1: Standby mode supported byte 2
P2: Idle mode supported
P3: Drive auto power control
N: Some config excludes
3X7
E: Index bit is emulated
I: Twin IOIS16# data reg only
R: Reserved
074H 1AH CISTPL_CONFIG
076H 05H TPL_LINK
Configuration tuple
Tuple code
Link length is 5 bytes
Link to next tuple
078H 01H RFS
RMS
RAS
RFS: Reserved
Size of fields byte TPCC_SZ
RMS: TPCC_RMSK size - 1 = 0
RAS: TPCC_RADR size - 1 = 1
1 byte register mask
2 byte config base address
07AH 03H TPCC_LAST
Entry with config index of 03H Last entry of config registers
is final entry in table
07CH 00H TPCC_RADR (LSB)
Configuration registers are
located at 200H in REG
space
Location of config registers
07EH 02H TPCC_RADR (MSB)
080H 0FH Reserved
S
P
C I
I: Configuration index
Configuration registers
C: Configuration and status present mask
P: Pin replacement
S: Socket and copy
TPCC_RMSK
Rev.1.00, Mar.16.2004, page 21 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
082H 1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
084H 08H TPL_LINK
Link length is 8 bytes
Link to next tuple
086H C0H I
D Configuration index
Memory mapped I/O
configuration
Configuration table index
byte
I = 1: Interface byte follows TPCE_INDX
D = 1: Default entry
Configuration index = 0
088H 40H
W
R P
B
Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVD1 and BVD2 not
used
Interface description field
TPCE_IF
IF type = 0: Memory
interface
08AH A1H
M
R
X
MS
IR IO T
P
M = 1: Misc info present
MS = 01: Memory space info TPCE_FS
single 2-byte length
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
Feature selection byte
T = 0: No timing info present
P = 1: VCC only info
08CH 01H
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
08EH 55H
Mantissa
Exponent
Nominal voltage = 5 V
VCC nominal value
090H 08H Length in 256 bytes pages (LSB)
Length of memory space is 2 Memory space description
kB
structures (TPCE_MS)
092H 00H Length in 256 bytes pages (MSB)
094H 20H
X
R P RO A
T
X = 0: No more misc fields
R: Reserved
Miscellaneous features field
TPCE_MI
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
Rev.1.00, Mar.16.2004, page 22 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
096H 1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
098H 06H TPL_LINK
Link length is 6 bytes
Link to next tuple
09AH 00H
09CH 01H
I
D Configuration index
Memory mapped I/O
configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 0
Configuration table index
byte
TPCE_INDX
M
MS
IR IO T
P
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
09EH 21H
R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0A0H B5H
0A2H 1EH
X
X
Mantissa
Extension
Mantissa
Exponent
Exponent
Nominal voltage = 3.0 V
+0.3 V
VCC nominal value
Extension byte
0A4H 4DH X
Max average current over 10 Max. average current
msec is 45 mA
Rev.1.00, Mar.16.2004, page 23 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0A6H 1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
0A8H 0AH TPL_LINK
Link length is 10 bytes
Link to next tuple
0AAH C1H I
D Configuration INDEX
Contiguous I/O mapped ATA Configuration table index
registers configuration
I = 1: Interface byte follows
D = 1: Default entry
byte TPCE_INDX
Configuration index = 1
0ACH 41H
W
R P
B
Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
Interface description field
TPCE_IF
IF type = 1: I/O interface
0AEH 99H
M
R
MS
IR IO T
P
M = 1: Misc info present
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: VCC only info
Feature selection byte
0B0H 01H
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0B2H 55H
0B4H 64H
X
R
Mantissa
Exponent
Nominal voltage = 5 V
VCC nominal value
S
E
IO AddrLine
S = 1: 16-bit hosts supported I/O space description field
E = 1: 8-bit hosts supported TPCE_IO
IO AddrLines: 4 lines
decoded
0B6H F0H
S
P
L
M V
B
I
N
S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
Interrupt request description
structure
TPCE_IR
L = 1: Level mode IRQ
supported
M = 1: Bit mask of IRQs
present
V = 0: No vender unique IRQ
B = 0: No bus error IRQ
I = 0: No IO check IRQ
N = 0: No NMI
Rev.1.00, Mar.16.2004, page 24 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
0B8H FFH IRQ IR IR IR IR IR IR IRQ0 IRQ level to be routed 0 to 15 Mask extension byte 1
Q Q Q Q Q Q recommended TPCE_IR
6
5
4
3
2
1
0
Description of contents
CIS function
7
6
5
4
3
2
1
0BAH FFH IRQ IR IR IR IR IR IR IRQ8 Recommended routing to any Mask extension byte 2
15 Q Q Q Q Q Q
14 13 12 11 10 9
“normal, maskable” IRQ.
TPCE_IR
0BCH 20H
X
R P RO A
T
X = 0: No more misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
Rev.1.00, Mar.16.2004, page 25 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0BEH 1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
0C0H 06H TPL_LINK
Link length is 6 bytes
Link to next tuple
0C2H 01H
0C4H 01H
I
D Configuration index
Contiguous I/O mapped ATA Configuration table index
registers configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 1
byte
TPCE_INDX
M
MS
IR IO T
P
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
0C6H 21H
R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0C8H B5H
0CAH 1EH
X
X
Mantissa
Extension
Mantissa
Exponent
Exponent
Nominal voltage = 3.0 V
+0.3 V
VCC nominal value
Extension byte
0CCH 4DH X
Max average current over 10 Max. average current
msec is 45 mA
Rev.1.00, Mar.16.2004, page 26 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0CEH 1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
0D0H 0FH TPL_LINK
Link length is 15 bytes
Link to next tuple
0D2H C2H I
D Configuration INDEX
ATA primary I/O mapped
configuration
Configuration table index
byte TPCE_INDX
I = 1: Interface byte follows
D = 1: default entry follows
Configuration index = 2
0D4H 41H
W
R P
B
Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
Interface description field
TPCE_IF
IF type = 1: I/O interface
0D6H 99H
M
R
MS
IR IO T
P
M = 1: misc info present
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: VCC only info
Feature selection byte
0D8H 01H
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0DAH 55H
X
Mantissa
Exponent
Nominal voltage = 5 V
VCC nominal value
0DCH EAH R
S
E
IO AddrLine
R = 1: Range follows
I/O space description field
S = 1: 16-bit hosts supported TPCE_IO
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded
0DEH 61H LS
AS
N range
LS = 1: Size of lengths is 1 I/O range format description
byte
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1
Rev.1.00, Mar.16.2004, page 27 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
0E0H F0H
0E2H 01H
0E4H 07H
0E6H F6H
0E8H 03H
0EAH 01H
0ECH EEH S
6
5
4
3
2
1
0
Description of contents
1st I/O base address (LSB)
1st I/O base address (MSB)
1st I/O length - 1
2nd I/O base address (LSB)
2nd I/O base address (MSB)
2nd I/O length - 1
CIS function
1st I/O range address
1st I/O range length
2nd I/O range address
2nd I/O range length
P
L
M
IRQ level
S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
Interrupt request description
structure
TPCE_IR
L = 1: Level mode IRQ
supported
M = 0: Bit mask of IRQs
present
IRQ level is IRQ14
0EEH 20H
X
R P RO A
T
X = 0: No more misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
Rev.1.00, Mar.16.2004, page 28 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0F0H 1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
0F2H 06H TPL_LINK
Link length is 6 bytes
Link to next tuple
0F4H 02H
0F6H 01H
I
D Configuration index
ATA primary I/O mapped
configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 2
Configuration table index
byte
TPCE_INDX
M
MS
IR IO T
P
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
0F8H 21H
R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0FAH B5H
0FCH 1EH
X
X
Mantissa
Extension
Mantissa
Exponent
Exponent
Nominal voltage = 3.0 V
+0.3 V
VCC nominal value
Extension byte
0FEH 4DH X
Max average current over 10 Max. average current
msec is 45 mA
Rev.1.00, Mar.16.2004, page 29 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
100H 1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
102H 0FH TPL_LINK
Link length is 15 bytes
Link to next tuple
104H C3H I
D Configuration INDEX
ATA secondary I/O mapped Configuration table index
configuration
byte TPCE_INDX
I = 1: Interface byte follows
D = 1: default entry
Configuration index = 3
106H 41H
W
R P
B
Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
Interface description field
TPCE_IF
IF type = 1: I/O interface
108H 99H
M
R
MS
IR IO T
P
M = 1: misc info present
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: VCC only info
Feature selection byte
10AH 01H
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
10CH 55H
X
Mantissa
Exponent
Nominal voltage = 5 V
VCC nominal value
10EH EAH R
S
E
IO AddrLine
R = 1: Range follows
I/O space description field
S = 1: 16-bit hosts supported TPCE_IO
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded
110H 61H LS
AS
N range
LS = 1: Size of lengths is 1 I/O range format description
byte
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1
Rev.1.00, Mar.16.2004, page 30 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
112H 70H
114H 01H
116H 07H
118H 76H
11AH 03H
11CH 01H
11EH EEH S
6
5
4
3
2
1
0
Description of contents
1st I/O base address (LSB)
1st I/O base address (MSB)
1st I/O length - 1
2nd I/O base address (LSB)
2nd I/O base address (MSB)
2nd I/O length - 1
CIS function
1st I/O range address
1st I/O range length
2nd I/O range address
2nd I/O range length
P
L
M
IRQ level
S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
Interrupt request description
structure
TPCE_IR
L = 1: Level mode IRQ
supported
M = 0: Bit mask of IRQs
present
IRQ level is IRQ14
120H 20H
X
R P RO A
T
X = 0: No more misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
Rev.1.00, Mar.16.2004, page 31 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
122H 1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
124H 06H TPL_LINK
Link length is 6 bytes
Link to next tuple
126H 03H
128H 01H
I
D Configuration index
ATA secondary I/O mapped Configuration table index
configuration
byte
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 3
TPCE_INDX
M
MS
IR IO T
P
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
12AH 21H
R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
12CH B5H
12EH 1EH
X
X
Mantissa
Extension
Mantissa
Exponent
Exponent
Nominal voltage = 3.0 V
+0.3 V
VCC nominal value
Extension byte
130H 4DH X
Max average current over 10 Max. average current
msec is 45 mA
132H 14H CISTPL_NO_LINK
134H 00H
No link control tuple
Link is 0 bytes
Tuple code
Link to next tuple
Tuple code
136H FFH CISTPL_END
End of list tuple
Rev.1.00, Mar.16.2004, page 32 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Task File register specification
These registers are used for reading and writing the storage data in this card. These registers are mapped
five types by the configuration of INDEX in Configuration Option register. The decoded addresses are
shown as follows.
Memory map (INDEX = 0)
-REG A10 A9 to A4 A3 A2 A1 A0 Offset -OE = L
-WE = L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
0
0
0
0
0
0
1
1
1
1
1
×
×
0
0
0
0
1
1
1
1
0
0
1
1
1
×
×
0
0
1
1
0
0
1
1
0
0
0
1
1
×
×
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
DH
EH
FH
8H
9H
Data register
Data register
Error register
Feature register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Status register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Command register
Dup. even data register
Dup. odd data register
Dup. feature register
Device control register
Reserved
Dup. even data register
Dup. odd data register
Dup. error register
Alt. status register
Drive address register
Even data register
Odd data register
Even data register
Odd data register
Rev.1.00, Mar.16.2004, page 33 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Contiguous I/O map (INDEX = 1)
-REG A10 to A4
A3 A2 A1 A0 Offset -IORD = L
-IOWR = L
0
0
0
0
0
0
0
0
0
0
0
0
0
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
DH
EH
FH
Data register
Data register
Error register
Feature register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Status register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Command register
Dup. even data register
Dup. odd data register
Dup. feature register
Device control register
Reserved
Dup. even data register
Dup. odd data register
Dup. error register
Alt. status register
Drive address register
Primary I/O map (INDEX = 2)
-REG A10 A9 to A4
A3 A2 A1 A0 -IORD = L
-IOWR = L
0
0
0
0
0
0
0
0
0
0
×
×
×
×
×
×
×
×
×
×
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
3FH
3FH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
Data register
Data register
Error register
Feature register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Status register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Command register
Device control register
Reserved
Alt. status register
Drive address register
Rev.1.00, Mar.16.2004, page 34 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Secondary I/O map (INDEX = 3)
-REG A10 A9 to A4
A3 A2 A1 A0 -IORD = L
-IOWR = L
0
0
0
0
0
0
0
0
0
0
×
×
×
×
×
×
×
×
×
×
17H
17H
17H
17H
17H
17H
17H
17H
37H
37H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
Data register
Data register
Error register
Feature register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Status register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Command register
Device control register
Reserved
Alt. status register
Drive address register
True IDE Mode I/O map
-CS1
-CS0
A2 A1 A0 -IORD = L
-IOWR = L
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
Data register
Data register
Error register
Feature register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Status register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Command register
Device control register
Reserved
Alt. status register
Drive address register
Rev.1.00, Mar.16.2004, page 35 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
1. Data register: This register is a 16-bit register that has read/write ability, and it is used for transferring
1 sector data between the card and the host. This register can be accessed in word mode and byte
mode. This register overlaps the Error or Feature register.
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
D0 to D15
2. Error register: This register is a read only register, and it is used for analyzing the error content at the
card accessing. This register is valid when the BSY bit in Status register and Alternate Status register
are set to “0” (Ready).
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BBK
UNC
“0”
IDNF
“0”
ABRT
“0”
AMNF
bit
7
Name
Function
BBK (Bad BlocK detected)
UNC (Data ECC error)
This bit is set when a Bad Block is detected in requested ID field.
6
This bit is set when Uncorrectable error is occurred at reading the
card.
4
2
IDNF (ID Not Found)
The requested sector ID is in error or cannot be found.
ABRT (ABoRTed command)
This bit is set if the command has been aborted because of the
card status condition. (Not ready, Write fault, Invalid command,
etc.)
0
AMNF (Address Mark Not Found) This bit is set in case of a general error.
3. Feature register: This register is a write only register, and provides information regarding features of
the drive which the host wishes to utilize.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Feature byte
4. Sector count register: This register contains the numbers of sectors of data requested to be transferred
on a read or write operation between the host and the card. If the value of this register is zero, a count
of 256 sectors is specified. In plural sector transfer, if not successfully completed, the register contains
the number of sectors which need to be transferred in order to complete the request. This register’s
initial value is “01H”.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Sector count byte
Rev.1.00, Mar.16.2004, page 36 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
5. Sector number register: This register contains the starting sector number which is started by
following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Sector number byte
6. Cylinder low register: This register contains the low 8-bit of the starting cylinder address which is
started by following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Cylinder low byte
7. Cylinder high register: This register contains the high 8-bit of the starting cylinder address which is
started by following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Cylinder high byte
8. Drive head register: This register is used for selecting the Drive number and head number for the
following command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
1
LBA
1
DRV
Head number
Note: DRV: Drive number
Head number: Head number
bit
7
Name
Function
1
This bit is set to “1”.
6
LBA
LBA is a flag to select either Cylinder / Head / Sector (CHS) or
Logical Block Address (LBA) mode. When LBA = 0, CHS mode is
selected. When LBA = 1, LBA mode is selected. In LBA mode, the
Logical Block Address is interrupted as follows:
LBA07 - LBA00: Sector Number Register D7 - D0.
LBA15 - LBA08: Cylinder Low Register D7 - D0.
LBA23 - LBA16: Cylinder High Register D7 - D0.
LBA27 - LBA24: Drive / Head Register bits HS3 - HS0.
5
4
1
This bit is set to “1”.
DRV (DRiVe select)
This bit is used for selecting the Master (Card 0) and Slave (Card
1) in Master/Slave organization. The card is set to be Card 0 or 1
by using DRV# of the Socket and Copy register.
3 to 0 Head number
This bit is used for selecting the Head number for the following
command. Bit 3 is MSB.
Rev.1.00, Mar.16.2004, page 37 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
9. Status register: This register is read only register, and it indicates the card status of command
execution. When this register is read in configured I/O card mode (INDEX = 1, 2, 3) and level
interrupt mode, -IREQ is negated. This register should be accessed in byte mode. In word mode, it is
recommended that Alternate status register may be used as this register.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BSY
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
bit
Name
BSY (BuSY)
Function
7
This bit is set when the card internal operation is executing. When
this bit is set to “1”, other bits in this register are invalid.
6
DRDY (Drive ReaDY)
If this bit and DSC bit are set to “1”, the card is capable of
receiving the read or write or seek requests. If this bit is set to “0”,
the card prohibits these requests.
5
4
3
DWF (Drive Write Fault)
DSC (Drive Seek Complete)
DRQ (Data ReQuest)
This bit is set if this card indicates the write fault status.
This bit is set when the drive seek complete.
This bit is set when the information can be transferred between the
host and Data register. This bit is cleared when the card receives
the other command.
2
CORR (CORRected data)
This bit is set when a correctable data error has been occurred
and the data has been corrected.
1
0
IDX (InDeX)
This bit is always set to “0”.
ERR (ERRor)
This bit is set when the previous command has ended in some
type of error. The error information is set in the other Status
register or Error register. This bit is cleared by the next command.
10. Alternate status register: This register is the same as Status register in physically, so the bit
assignment refers to previous item of Status register. But this register is different from Status register
that -IREQ is not negated when data read.
11. Command register: This register is write only register, and it is used for writing the command at
executing the drive operation. The command code written in the command register, after the parameter
is written in the Task File during the card is Ready state.
Parameter
FR: Feature register
SC: Sector Count register
SN: Sector Number register
CY: Cylinder register
DR: DRV bit of Drive Head register
HD: Head Number of Drive Head register
LBA: Logical Block Address Mode Supported
Rev.1.00, Mar.16.2004, page 38 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
12. Device control register: This register is write only register, and it is used for controlling the card
interrupt request and issuing an ATA soft reset to the card.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
×
×
×
1
SRST
nIEN
0
bit
Name
Function
7 to 4 ×
don’t care
3
2
1
This bit is set to “1”.
SRST (Software ReSeT)
This bit is set to “1” in order to force the card to perform Task File
Reset operation. This does not change the Card Configuration
registers as a Hardware Reset does. The card remains in Reset
until this bit is reset to “0”.
1
0
nIEN (Interrupt ENable)
0
This bit is used for enabling -IREQ. When this bit is set to “0”, -
IREQ is enabled. When this bit is set to “1”, -IREQ is disabled.
This bit is set to “0”.
13. Drive Address register: This register is read only register, and it is used for confirming the drive
status. This register is provides for compatibility with the AT disk drive interface. It is recommended
that this register is not mapped into the host’s I/O space because of potential conflicts on bit7.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
nWTG
nHS3
nHS2
nHS1
nHS0
nDS1
nDS0
bit
7
Name
Function
×
This bit is unknown.
This bit is unknown.
6
nWTG (WriTing Gate)
5 to 2 nHS3-0 (Head Select3-0)
These bits are the negative value of Head Select bits (bit 3 to 0) in
Drive/Head register.
1
0
nDS1 (Idrive Select1)
nDS0 (Idrive Select0)
This bit is unknown.
This bit is unknown.
Rev.1.00, Mar.16.2004, page 39 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
ATA Command specifications
This table summarizes the ATA command set with the paragraphs. Following shows the support
commands and command codes which are written in command registers.
ATA Command Set
No.
1
Command set
Check power mode
Execute drive diagnostic
Erase sector(s)
Format track
Code
FR
Y
SC
Y
SN
Y
CY
Y
DR
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HD
Y
LBA
Y
E5H or 98H
90H
2
3
C0H
4
50H
Y
Y
Y
Y
Y
5
Identify Drive
ECH
Y
Y
Y
Y
6
Idle
E3H or 97H
E1H or 95H
91H
7
Idle immediate
Initialize drive parameters
Read buffer
Y
8
9
E4H
Y
Y
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Read multiple
Read long sector
Read sector (s)
Read verify sector (s)
Recalibrate
C4H
22H, 23H
20H, 21H
40H, 41H
1XH
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Request sense
Seek
03H
7XH
Set features
EFH
Y
Y
Y
Y
Set multiple mode
Set sleep mode
Stand by
C6H
E6H or 99H
E2H or 96H
E0H or 94H
87H
Y
Stand by immediate
Translate sector
Wear level
F5H
Y
Rev.1.00, Mar.16.2004, page 40 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
No.
24
25
26
27
28
29
30
Command set
Write buffer
Code
FR
SC
Y
SN
Y
CY
Y
DR
Y
HD
Y
LBA
Y
E8H
Write long sector
Write multiple
32H or 33H
C5H
Y
Y
Y
Y
Y
Y
Write multiple w/o erase
Write sector
CDH
Y
Y
Y
Y
Y
Y
30H or 31H
38H
Y
Y
Y
Y
Y
Y
Write sector(s) w/o erase
Write verify
Y
Y
Y
Y
Y
Y
3CH
Y
Y
Y
Y
Y
Y
Note: FR: Feature Register
SC: Sector Count register
(00H to FFH)
SN: Sector Number register (01H to 20H)
CY: Cylinder Low/High register (to)
DR: Drive bit of Drive/Head register
HD: Head No. (0 to 3) of Drive/Head register
NH: No. of Heads
Y: Set up
: Not set up
1. Check Power Mode (code: E5H or 98H): This command checks the power mode.
2. Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests
implemented by the Card.
3. Erase Sector(s) (code: C0H): This command is used to erase data sectors.
4. Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive.
But selected sector data is not exchange. This card excepts a sector buffer of data from the host to
follow the command with same protocol as the Write Sector command.
5. Identify Drive (code: ECH): This command enables the host to receive parameter information from
the Card
Rev.1.00, Mar.16.2004, page 41 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Identify Drive Information
Word address Default value Total bytes Data field type information
0
848AH
XXXXH
0000H
00XXH
0000H
XXXXH
XXXXH
XXXXH
0000H
XXXXH
0002H
0002H
0004H
XXXXH
XXXXH
2
General configuration bit-significant information
1
2
Default number of cylinders
2
2
Reserved
3
2
Default number of heads
4
2
Obsolete
5
2
Obsolete
6
2
Default number of sectors per track
Number of sectors per card (Word7 = MSW, Word8 = LSW)
Obsolete
7 to 8
9
4
2
10 to 19
20
20
2
Serial number in ASCII (Right justified)
Obsolete
21
2
Obsolete
22
2
# of ECC bytes passed on Read/Write Long Commands
Firmware revision in ASCII. Big Endian Byte Order in Word
23 to 26
27 to 46
8
40
Model number in ASCII (Left justified) Big Endian Byte Order
in Word
47
0001H
2
Maximum number of sectors on Read/Write Multiple
command
48
49
50
51
52
53
0000H
0200H
0000H
0200H
0000H
0003H
2
2
2
2
2
2
Reserved
Capabilities: LBA supported (bit9)
Reserved
PIO data transfer cycle timing mode
Obsolete
Translation Parameters Valid (bit0: Word54 to 58 are valid,
bit1: Word64 to 70 are valid)
54
XXXXH
XXXXH
XXXXH
XXXXH
2
2
2
4
Current numbers of cylinders
Current numbers of heads
Current numbers per track
55
56
57 to 58
Current capacity in sectors (LBAs) (Word57 = LSW, Word58
= MSW)
59
010XH
XXXXH
0000H
2
4
4
Multiple sector setting
60 to 61
62 to 63
Total number of sectors addressable in LBA Mode
Reserved
Rev.1.00, Mar.16.2004, page 42 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Word address Default value Total bytes Data field type information
64
0003H
2
Advanced PIO Modes supported (bit0: PIO-3, bit1: PIO-4
supported)
65 to 66
67
0000H
0078H
0078H
0000H
0000H
7000H
4
Reserved
2
Minimum PIO transfer cycle time without flow control
Minimum PIO transfer cycle time with IORDY flow control
Reserved
68
2
69 to 79
80 to 81
82
20
4
Reserved for CFA
2
Features/command sets supported
15: Obsolete
14: 1 = NOP command supported
13: 1 = Read buffer command supported
12: 1 = Write buffer command supported
11: Obsolete
10: 0 = Host protected area feature set not supported
9: 0 = Device reset command not supported
8: 0 = Service interrupt not supported
7: 0 = Release interrupt not supported
6: 0 = Look-ahead not supported
5: 0 = Write cache not supported
4: 0 = PACKET command feature set not supported
3: 0 = Power management feature set not supported
2: 0 = Removable media feature set not supported
1: 0 = Security mode feature set not supported
0: 0 = Smart feature set not supported
83
4004H
2
Features/command sets supported
15: Shall be cleared to zero
14: Shall be set to one
13 to 7: Reserved
6: 0 = Set features subcommand required to spin up after
power-up (not supported)
5: 0 = Power-up in standby feature set not supported
4: 0 = Removable media status notification feature set not
supported
3: Advanced power management feature set not supported
2: 1 = CFA feature set supported
1: 0 = Read/Write DMA queued command not supported
0: 0 = Download microcode command not supported
84
4000H
2
Features/command sets supported
Rev.1.00, Mar.16.2004, page 43 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Word address Default value Total bytes Data field type information
85
7000H
2
Features/command sets enabled
15: Obsolete
14: 1 = NOP command supported
13: 1 = Read buffer command supported
12: 1 = Write buffer command supported
11: Obsolete
10: 0 = Host protected area feature set not supported
9: 0 = Device reset command not supported
8: 0 = Service interrupt disabled
7: 0 = Release interrupt disabled
6: 0 = Look-ahead not supported
5: 0 = Write cache not supported
4: 0 = PACKET command feature set not supported
3: 0 = Power management feature set not supported
2: 0 = Removable media feature set not supported
1: 0 = Security mode feature set disabled
0: 0 = Smart feature set enabled disabled
86
0004H
2
Features/command sets enabled
15 to 7: Reserved
6: 0 = Set features subcommand required to spin up after
power-up (not supported)
5: 0 = Power-up in standby feature set disabled
4: 0 = Removable media status notification feature set
disabled
3: 0 = Advanced power management feature set disabled
2: 1 = CFA feature set supported
1: 0 = Read/Write DMA queued command not supported
0: 0 = Download microcode command not supported
87
4000H
2
Features/command sets enabled
15: Shall be cleared to zero
14: Shall be set to one
13 to 0: Reserved
88
0000H
0000H
0000H
XXXXH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
2
Reserved
89
2
Time required for Security erase unit completion
Time required for Enhanced security erase unit completion
Current Advanced power management value
Reserved
90
2
91
2
92 to 127
128
72
2
Security status
129 to 159
160
64
2
Vendor unique bytes
Power requirement description
Reserved
161
2
162
2
Key management schemes supported
Reserved
163 to 255
166
Rev.1.00, Mar.16.2004, page 44 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
6. Idle (code: E3H or 97H): This command causes the PC Card to set BSY, enter the Idle mode, clear
BSY and generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled.
If the sector count is zero, the automatic power down mode is disabled.
7. Idle Immediate (code: E1H or 95H): This command causes the Card to set BSY, enter the Idle (Read)
mode, clear BSY and generate an interrupt.
8. Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors
per track and the number of heads per cylinder.
9. Read Buffer (code: E4H): This command enables the host to read the current contents of the PC card’s
sector buffer.
10. Read Multiple (code: C4h): This command performs similarly to the Read Sectors command.
Interrupts are not generated on each sector, but on the transfer of a block which contains the number of
sectors defined by a Set Multiple command.
11. Read Long Sector (code: 22h or 23h): This command performs similarly to the Read Sector(s)
command except that it returns 516 bytes of data instead of 512 bytes.
12. Read Sector(s) (code: 20h, 21h): This command reads from 1 to 256 sectors as specified in the Sector
Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in
the Sector Number register.
13. Read Verify Sector(s) (code: 40h or 41h): This command is identical to the Read Sectors command,
except that DRQ is never set and no data is transferred to the host.
14. Recalibrate (code: 1Xh): This command is effectively a NOP command to the Card and is provided
for compatibility purposes.
15. Request Sense (code: 03h): This command requests an extended error code after command ends with
an error.
16. Seek (code: 7Xh): This command is effectively a NOP command to the Card although it does perform
a range check.
17. Set Features (code: EFH): This command is used by the host to establish or select certain features.
Feature
01H
Operation
Enable 8-bit data transfers.
55H
Disable Read Look Ahead.
66H
Disable Power on Reset(POR) establishment of defaults at Soft Reset.
Disable 8-bit data transfer.
81H
BBH
CCH
4bytes of data apply on Read/Write Long commands.
Enable Power on Reset(POR) establishment of default at Soft Reset.
Rev.1.00, Mar.16.2004, page 45 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
18. Set Multiple Mode (code: C6h): This command enables the Card to perform Read and Write Multiple
operations and establishes the block count for these commands.
19. Set Sleep Mode (code: E6h or 99h): This command causes the Card to set BSY, enter the Sleep mode,
clear BSY and generate an interrupt.
20. Stand By (code: E2h or 96h): This command causes the Card to set BSY, enter the Sleep mode (which
corresponds to the ATA “Standby” Mode), clear BSY and return the interrupt immediately.
21. Stand By Immediate (code: E0h or 94h): This command causes the Card to set BSY, enter the Sleep
mode (which corresponds to the ATA “Standby” Mode), clear BSY and return the interrupt
immediately.
22. Translate Sector (code: 87h): This card does not support by this command the function of determining
the exact number of times a user sector has been erased and programmed because this card always
responds with “00H”, though this command could provide information containing the desired cylinder,
head and sector, including its Logical Address, etc.
23. Wear level (code: F5h): This command is effectively a NOP command and only implemented for
backward compatibility. The Sector Count Register will always be returned with an 00H indicating
Wear Level is not needed.
24. Write Buffer (code: E8h): This command enables the host to overwrite contents of the Card’s sector
buffer with any data pattern desired.
25. Write Long Sector (code: 32h or 33h): This command is provided for compatibility purposes and is
similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes.
26. Write Multiple (code: C5h): This command is similar to the Write Sectors command. Interrupts are
not presented on each sector, but on the transfer of a block which contains the number of sectors
defined by Set Multiple command.
27. Write Multiple without Erase (code: CDh): This command is similar to the Write Multiple command
with the exception that an implied erase before write operation is not performed.
28. Write Sector(s) (code: 30h or 31h): This command writes from 1 to 256 sectors as specified in the
Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector
specified in the Sector Number register.
29. Write Sector(s) without Erase (code: 38h): This command is similar to the Write Sector(s) command
with the exception that an implied erase before write operation is not performed.
30. Write Verify (code: 3Ch): This command is similar to the Write Sector(s) command, except each
sector is verified immediately after being written.
Rev.1.00, Mar.16.2004, page 46 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Sector Transfer Protocol
1. Sector read: 1 sector read procedure after the card configured I/O interface is shown as follows.
Start
I/O Access, INDEX=1
Set the cylinder low / high register
Set the head No. of drive head register
(1)Set the logical sector number
Set the sector number register
Set "01H" in sector count register
Set "20H" in Command register
Read the status register
(2)
(3)
N
"58H"?
Y
Read 256 times the data register
(512 bytes)
(4)Burst data transfer
Read the status register
(5)
N
"50H"?
Y
Wait the command input
Rev.1.00, Mar.16.2004, page 47 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
(1)
(2)
(3)
(4)
(5)
4H 5H 6H 3H 2H 7H
7H 7H
0H
0H
7H 7H
A0 to A10
-CE1
-CE2
-IOWR
-IORD
Data transfer
01H20H 80H 58H
80H 50H
D0 to D15
-IREQ
Rev.1.00, Mar.16.2004, page 48 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
2. Sector write: 1 sector write procedure after the card configured I/O interface is shown as follows.
Start
I/O Access, INDEX=1
Set the cylinder low / high register
Set the head No. of drive head register
(1) Set the logical sector number
Set the sector number register
Set "01H" in sector count register
Set "30H" in command register
Read the status register
(2)
(3)
N
"58H"?
Y
Write 256 times the data register
(512 bytes)
(4) Burst data transfer
Read the status register
(5)
N
"50H"?
Y
Wait the command input
Rev.1.00, Mar.16.2004, page 49 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
(1)
(2)
(3)
(4)
(5)
A0 to A10
-CE1
4H 5H 6H 3H 2H 7H
7H 7H
0H
0H
7H 7H
-CE2
-IOWR
-IORD
Data transfer
01H30H 80H 58H
80H 50H
D0 to D15
-IREQ
Rev.1.00, Mar.16.2004, page 50 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Absolute Maximum Ratings
Parameter
Symbol
Vin, Vout
VCC
Value
Unit
V
Note
All input/output voltages
VCC voltage
−0.3 to VCC + 0.3
−0.3 to +6.5
0 to +60
1
V
Operating temperature range
Storage temperature range
Topr
°C
°C
Tstg
−20 to +65
Note: 1. Vin, Vout min = −2.0 V for pulse width ≤ 20 ns.
Recommended Operating Conditions
Parameter
Symbol
Ta
Min
Typ
Max
Unit
Operating temperature
VCC voltage
0
+25
+60
°C
V
VCC
5.0 − 10%
3.3 − 5%
5.0
3.3
5.0 + 10%
3.3 + 5%
V
Capacitance (Ta = +25°C, f = 1MHz)
Parameter
Symbol
Cin
Min
Typ
Max
Unit
pF
Test conditions
Vin = 0 V
Input capacitance
Output capacitance
35
35
Cout
pF
Vout = 0 V
System Performance
Item
Performance
100 ms (max)
2 ms (max)
Set up times (Reset to ready)
Set up times (Sleep to idle)
Data transfer rate to/from host
16.6 MB/s burst
2 ms (max)
Controller overhead (Command to DRQ)
Data transfer cycle end to ready (Sector write)
2 ms (typ)
Rev.1.00, Mar.16.2004, page 51 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
DC Characteristics-1 (Ta = 0 to +60°C, VCC = 5 V 10%, 3.3 V 5%)
Parameter
Symbol Min
Typ
Max
1
Unit Test conditions
Note
Input leakage current
Output voltage
ILI
µA
V
Vin = GND to VCC
IOL = 8 mA
1
VOL
VOH
0.4
VCC − 0.8
V
IOH = −8 mA
Note: 1. Except pulled up input pin.
3.3 V
5 V
Min
Parameter
Symbol Min
Typ
Max
Typ
Max
Unit Test conditions
Input voltage
(CMOS)
VIL
0.6
0.8
V
VIH
VIL
2.4
4.0
V
V
Input voltage
(Schmitt trigger)
1.0
2.0
VIH
1.8
2.8
V
DC Characteristics-2 (Ta = 0 to +60°C, VCC = 5.0 V 10%)
128MB/
256MB
512MB/
1GB
Parameter Symbol
Typ
Max
Typ
Max
Unit
Test conditions
Sleep/
ISP1
1.0
1.5
1.0
1.5
mA
CMOS level
standby
current
(control signal = VCC − 0.2 V)
(In Memory card mode and I/O
card mode)
Sector read ICCR
current
40
50
100
100
45
55
100
100
mA
mA
CMOS level
(control signal = VCC − 0.2 V)
during sector read transfer
(RMS)*1
Sector write ICCW
CMOS level
(control signal = VCC − 0.2 V)
during sector write transfer
current
(RMS)*1
Read/Write ICC
current peak (Peak)
120mA/
120mA/
CMOS level
(control signal = VCC − 0.2 V)
50µs*2
50µs*2
Note: 1. Average value of the RMS operation current at the time of 128 sector transfer.
2. Reference value.
Rev.1.00, Mar.16.2004, page 52 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
DC Characteristics-3 (Ta = 0 to +60°C, VCC = 3.3 V 5%)
128MB/
256MB
512MB /
1GB
Parameter Symbol
Typ
Max
Typ
Max
Unit
Test conditions
Sleep/
ISP1
1.0
1.5
1.0
1.5
mA
CMOS level
standby
current
(control signal = VCC − 0.2 V)
(In Memory card mode and I/O
card mode)
Sector read ICCR
current
40
50
75
75
45
55
75
75
mA
mA
CMOS level
(control signal = VCC − 0.2 V)
during sector read transfer
(RMS)*1
Sector write ICCW
CMOS level
(control signal = VCC − 0.2 V)
during sector write transfer
current
(RMS)*1
Read/Write ICC
current peak (Peak)
120mA/
120mA/
CMOS level
(control signal = VCC − 0.2 V)
50µs*2
50µs*2
Note: 1. Average value of the RMS operation current at the time of 128 sector transfer.
2. Reference value.
Rev.1.00, Mar.16.2004, page 53 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
AC Characteristics (Ta = 0 to +60°C, VCC = 5.0 V 10%, 3.3 V 5%)
Attribute Memory Read AC Characteristics
250 ns
Parameter
Symbol
tCR
Min
250
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
Address access time
-CE access time
ta(A)
250
250
125
100
100
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tv(A)
-OE access time
Output disable time (-CE)
Output disable time (-OE)
Output enable time (-CE)
Output enable time (-OE)
Data valid time (A)
Address setup time
Address hold time
-CE setup time
5
0
tsu(A)
th(A)
30
20
0
tsu(CE)
th(CE)
-CE hold time
20
Attribute Memory Read Timing
t
CR
A0 to A10
-REG
t
a(A)
t
h(A)
t
v(A)
t
a(CE)
-CE2/-CE1
t
h(CE)
t
su(CE)
t
dis(CE)
t
su(A)
t
a(OE)
-OE
t
en(OE)
t
dis(OE)
t
en(CE)
D0 to D15
Valid Output
-WE, -IOWR, -IORD : High Fix
Rev.1.00, Mar.16.2004, page 54 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Attribute Memory Write AC Characteristics
250 ns
Parameter
Symbol
tCW
Min
250
150
30
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Write pulse time
tw(WE)
tsu(A)
Address setup time
Address setup time (-WE)
-CE setup time (-WE)
Data setup time (-WE)
Data hold time
tsu(A-WEH)
180
tsu(CE-WEH) 180
tsu(D-WEH)
th(D)
80
30
30
5
Write recover time
trec(WE)
tdis(WE)
tdis(OE)
ten(WE)
ten(OE)
Output disable time (-WE)
Output disable time (-OE)
Output enable time (-WE)
Output enable time (-OE)
Output enable setup time (-WE)
Output enable hold time (-WE)
-CE setup time
100
100
5
tsu(OE-WE)
th(OE-WE)
tsu(CE)
10
10
0
-CE hold time
th(CE)
20
Attribute Memory Write Timing
t
CW
A0 to A10
-REG
t
su(CE-WEH)
-CE2/-CE1
-OE
t
su(A-WEH)
t
h(CE)
t
su(CE)
t
su(A)
t
rec(WE)
t
w(WE)
su(D-WEH)
-WE
t
h(OE-WE)
t
su(OE-WE)
t
t
h(D)
D0 to D15(Din)
Input Data
tdis(WE)
t
en(OE)
t
dis(OE)
D0 to D15(Dout)
ten(WE)
-IOWR, -IORD : High Fix
Rev.1.00, Mar.16.2004, page 55 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
I/O Access Read AC Characteristics
Parameter
Symbol
Min
0
Typ
Max
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data delay after -IORD
td(IORD)
Data hold following -IORD
-IORD pulse width
th(IORD)
tw(IORD)
165
70
20
5
Address setup before -IORD
Address hold following -IORD
-CE setup before -IORD
tsuA(IORD)
thA(IORD)
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
-CE hold following -IORD
-REG setup before -IORD
-REG hold following -IORD
-INPACK delay falling from -IORD
-INPACK delay rising from -IORD
-IOIS16 delay falling from address
-IOIS16 delay rising from address
20
5
0
tdfINPACK(IORD) 0
45
45
35
35
tdrINPACK(IORD)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
I/O Access Read Timing
A0 to A10
thA(IORD)
tsuREG(IORD)
thREG(IORD)
-REG
thCE(IORD)
tsuCE(IORD)
-CE2/-CE1
-IORD
tw(IORD)
tdrINPACK(IORD)
tsuA(IORD)
-INPACK
tdfIOIS16(ADR)
tdrIOIS16(ADR)
tdfINPACK(IORD)
-IOIS16
th(IORD)
D0 to D15
Valid Output
td(IORD)
-WE, -OE, -IOWR : High Fix
Rev.1.00, Mar.16.2004, page 56 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
I/O Access Write AC Characteristics
Parameter
Symbol
Min
60
30
165
70
20
5
Typ
Max
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data setup before -IOWR
Data hold following -IOWR
-IOWR pulse width
tsu(IOWR)
th(IOWR)
tw(IOWR)
Address setup before -IOWR
Address hold following -IOWR
-CE setup before -IOWR
-CE hold following -IOWR
-REG setup before -IOWR
-REG hold following -IOWR
-IOIS16 delay falling from address
-IOIS16 delay rising from address
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
20
5
0
I/O Access Write Timing
A0 to A10
thA(IOWR)
t
suREG(IOWR)
thREG(IOWR)
-REG
thCE(IOWR)
tsuCE(IOWR)
-CE2/-CE1
tsuA(IOWR)
tw(IOWR)
-IOWR
tdfIOIS16(ADR)
tdrIOIS16(ADR)
-IOIS16
tsu(IOWR)
th(IOWR)
D0 to D15
Data In
-WE, -OE, -IORD : High Fix
Rev.1.00, Mar.16.2004, page 57 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Common Memory Access Read AC Characteristics
Parameter
Symbol
ta(OE)
tdis(OE)
tsu(A)
Min
30
20
0
Typ
Max
125
100
Unit
ns
-CE access time
Output disable time (-OE)
Address setup time
Address hold time
-CE setup time
ns
ns
th(A)
ns
tsu(CE)
th(CE)
ns
-CE hold time
20
ns
Common Access Read Timing
A0 to A10
t
h(A)
t
su(A)
-REG
-CE2/-CE1
t
su(CE)
t
t
h(CE)
a(OE)
-OE
t
dis(OE)
D0 to D15
Valid Output
-WE, -IORD, -IOWR : High Fix
Rev.1.00, Mar.16.2004, page 58 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Common Memory Access Write AC characteristics
Parameter
Symbol
tsu(D-WEH)
th(D)
Min
80
30
150
30
0
Typ
Max
Unit
ns
Data setup time (-WE)
Data hold time
ns
Write pulse time
Address setup time
-CE setup time
tw(WE)
tsu(A)
ns
ns
tsu(CE)
trec(WE)
th(CE)
ns
Write recover time
-CE hold following -WE
30
20
ns
ns
Common Access Write Timing
A0 to A10
-REG
t
rec(WE)
t
su(CE)
-CE2/-CE1
t
su(A)
t
h(CE)
t
w(WE)
-WE
th(D)
t
su(D-WEH)
D0 to D15
Data In
-IOWR, -IORD, -OE : High Fix
Rev.1.00, Mar.16.2004, page 59 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
True IDE Mode Access Read/Write AC Characteristics
Register transfer AC Characteristics
Parameter
Symbol Mode0 Mode1 Mode2 Mode3 Mode4 Unit
Cycle time
(min)
t0
t1
600
70
383
50
330
30
180
30
120
25
ns
ns
Address valid to
-IORD/-IOWR setup
(min)
(min)
-IORD/-IOWR register setup
(8-bit)
t2
290
290
290
80
70
ns
-IORD/-IOWR recovery time
-IOWR data setup
-IOWR data hold
(min)
(min)
(min)
(min)
(min)
t2i
t3
t4
t5
t6
60
30
50
5
45
20
35
5
30
15
20
5
70
30
10
20
5
25
20
10
20
5
ns
ns
ns
ns
ns
ns
ns
-IORD data setup
-IORD data hold
-IORD data tristate
(max) t6z
(max) t7
30
90
30
50
30
40
30
n/a
30
n/a
Address valid to -IOCS16
assertion
Address valid to -IOCS16
released
(max) t8
t9
60
20
45
15
30
10
n/a
10
n/a
10
ns
ns
-IORD/-IOWR to address valid
hold
Data transfer AC Characteristics
Parameter
Symbol Mode0 Mode1 Mode2 Mode3 Mode4 Unit
Cycle time
(min)
t0
t1
600
70
383
50
240
30
180
30
120
25
ns
ns
Address valid to
-IORD/-IOWR setup
(min)
(min)
-IORD/-IOWR register setup
(8-bit)
t2
165
125
100
80
70
ns
-IORD/-IOWR recovery time
-IOWR data setup
-IOWR data hold
(min)
(min)
(min)
(min)
(min)
t2i
t3
t4
t5
t6
60
30
50
5
45
20
35
5
30
15
20
5
70
30
10
20
5
25
20
10
20
5
ns
ns
ns
ns
ns
ns
ns
-IORD data setup
-IORD data hold
-IORD data tristate
(max) t6z
(max) t7
30
90
30
50
30
40
30
n/a
30
n/a
Address valid to -IOCS16
assertion
Address valid to -IOCS16
released
(max) t8
t9
60
20
45
15
30
10
n/a
10
n/a
10
ns
ns
-IORD/-IOWR to address valid
hold
Rev.1.00, Mar.16.2004, page 60 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
True IDE Mode Access Read/Write Timing
t0
ADDR valid
t8
t9
t2
t1
t2i
-IORD/-IOWR
D15 to D0 (Write)
t3
t4
D15 to D0 (Read)
t6
t5
t7
t6Z
-IOCS16
IORDY
Rev.1.00, Mar.16.2004, page 61 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Reset Characteristics (only Memory Card Mode or I/O Card Mode)
Hard Reset Characteristics
Parameter
Symbol
tsu(RESET)
trec(VCC)
tpr
Min
20
1
Typ
Max
Unit
ms
µs
Test conditions Note
Reset setup time
-CE recover time
VCC rising up time
VCC falling down time
Reset pulse width
0.1
3
100
300
ms
ms
µs
tpf
tw(RESET)
10
th(Hi-ZRESET) 1
ts(Hi-ZRESET) 0
ms
ms
1
Note: 1. As for this specification, it is fitted activity state when change. When reset signal is non-activity
state and a card is ready state, can shift to power supply cutoff sequence instantly.
Hard Reset Timing
t
pr
tpf
90%
90%
rec( cc)
V
cc
t
V
10%
10%
-CE1, -CE2
RESET
t
su(RESET)
t
h(Hi-ZRESET)
t
w(RESET)
t
s(Hi-ZRESET)
High-Z
High-Z
Low
Rev.1.00, Mar.16.2004, page 62 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Power on Reset Characteristics
All card status is reset automatically without Hard reset when VCC voltage goes over about 2.3 V.
Parameter
Symbol
tsu(VCC)
tpr
Min
20
Typ
Max
Unit
ms
Test conditions
-CE setup time
VCC rising up time
0.1
100
ms
Power on Reset Timing
tpr
Vcc
tsu(vcc)
-CE1, -CE2
Attention for Card Use
•
•
•
In the reset or power off, all register informations are cleared.
All card status is cleared automatically when VCC voltage turns below about 2.5V.
Notice that the card insertion/removal should not be executed while host is active, if the card is used in
True IDE mode.
•
•
•
•
After the card hard reset, soft reset, or power on reset, ATA reset, command applied the card cannot
access during +RDY/-BSY pin is “low” level. Flash card can’t be operated in this case.
Card removal or power off should not be done during internal operations. When the removal or power
off occurs during internal operation, there is a possibility that data are lost.
Before the card insertion VCC cannot be supplied to the card. After confirmation that -CD1, -CD2 pins
are inserted, supply VCC to the card.
-OE must be kept at the VCC level during power on reset in memory card mode and I/O card mode. -
OE must be kept constantly at the GND level in True IDE mode.
•
•
•
We recommend that a circuit to detect the level of power supply voltage be added to the host.
When a read error occurs, rewriting of the sector is recommended. This may avoid the error.
Because of the delay of internal power circuit, it may occur that any pin level isn't fixed immediately in
power on.
Rev.1.00, Mar.16.2004, page 63 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Physical Outline
As of January, 2003
26 pin
50 pin
Unit: mm
1.60 0.05
3.30 0.10
1.00 0.05
1.27
1 pin
25 pin
(Top)
1.27
1.00 0.08
1.00 0.08
3.30 0.10
42.80 0.10
(Top)
41.66 0.13
0.60 0.08
Rev.1.00, Mar.16.2004, page 64 of 65
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC
Caution for Handling Cards
•
•
•
•
•
•
•
Confirm the direction of insertion before inserting the card.
Be careful not to damage the connector.
To avoid damaging the card, never insert it in the wrong direction.
Do not bend the card; do not drop the card or expose the card to mechanical shock of any other kind.
Never modify or disassemble the card.
Do not expose the card to static electricity or electrical noise.
Make regular backups of the data in the card.
Rev.1.00, Mar.16.2004, page 65 of 65
Revision History
HB28J1000CFC/HB28J512CFC/HB28J256CFC/HB28J128CFC Data Sheet
Rev. Date
Contents of Modification
Page Description
1.00 Mar. 16. 2004
Initial issue
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Colophon .1.0
相关型号：
HB29010
Board Connector, 1 Contact(s), 1 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Receptacle
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