HB28J256RM3_技术文档

HB28K032MM3/HB28K032RM3

HB28L064MM3/HB28L064RM3

HB28J128MM3/HB28J128RM3

HB28J256MM3/HB28J256RM3

HB28J512MM3

MultiMediaCard

32 MByte/64 MByte/128 MByte/256 MByte/512 MByte

REJ03C0178-0002

Preliminary

Rev.0.02

Sep.15.2004

Description

These Renesas MultiMediaCards, HB28K032MM3, HB28K032RM3, HB28L064MM3,

HB28L064RM3, HB28J128MM3, HB28J128RM3, HB28J256MM3, HB28J256RM3 and HB28J512MM3

are highly integrated flash memories with serial and random access capability. It is accessible via a

dedicated serial interface optimized for fast and reliable data transmission. This interface allows several

cards to be stacked by through connecting their peripheral contacts. These Renesas MultiMediaCards are

fully compatible to a new consumer standard, called the MultiMediaCard system standard defined in the

MultiMediaCard system specification [1]. The MultiMediaCard system is a new mass-storage system

based on innovations in semiconductor technology. It has been developed to provide an inexpensive,

mechanically robust storage medium in card form for multimedia consumer applications. MultiMediaCard

allows the design of inexpensive players and drives without moving parts. A low power consumption and

a wide supply voltage range favor mobile, battery-powered applications such as audio players, organizers,

palmtops, electronic books, encyclopedia and dictionaries. Using very effective data compression schemes

such as MPEG, the MultiMediaCard will deliver enough capacity for all kinds of multimedia data:

software/programs, text, music, speech, images, video etc.

Notes: 1. MultiMediaCard is a trademark of Infineon Technologies AG.

2. These products are designed and manufactured for retail sale only. Therefore, please contact

Renesas Technology's Sales Dept. before using these products in other circumstances.

3. In case that these products are proved to have any defects in manufacturing attributable to

Renesas Technology Corp., the defective products can be returned and exchanged for

replacements, but Renesas Technology Corp. assumes no responsibility other than exchange.

Please contact Renesas Technology's Sales Dept. for further details.

Preliminary: The specifications of this device are subject to change without notice. Please contact your

nearest Renesas Technology’s Sales Dept. regarding specifications.

Rev.0.02, Sep.15.2004, page 1 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Features

•

MultiMediaCard line up:

Model

Memory capacity

Outline*¹

HB28K032MM3

HB28K032RM3

HB28L064MM3

HB28L064RM3

HB28J128MM3

HB28J128RM3

HB28J256MM3

HB28J256RM3

HB28J512MM3

32 MByte

Full size

Reduced size

Full size

64 MByte

128 MByte

256 MByte

512 MByte

Reduced size

Full size

Reduced size

Full size

Reduced size

Full size

Note: 1. Refer to Chapter “Physical Outline”.

•

On card error correction

MultiMediaCard system standard compatibility

System specification version 3.3 compliant

SPI mode supports the single and multiple block read and write operations.

Block and partial block read supported (Command classes 2)

Stream read supported (Command class 1)

Block write and erase supported (Command classes 4 and 5)

Group write protection (Command classes 6)

Stream write supported (Command classes 3)

Password data access protection

Small erase block size of 8 KBytes

Read block size programmable between 1 and 2048 bytes

V

_CC= 2.7 V to 3.6 V operation voltage range (V_CC= 2.0 V to 3.6 V for the interface)

No external programming voltage required

Damage free powered card insertion and removal (no operation)

4kV ESD protection (Contact Pads)

•

High speed serial interface with random access

Up to 10 stacked card (at 20 MHz, V_CC= 2.7 to 3.6 V)

Access time: 300 µs (typ) (at 20 MHz, V_CC= 2.7 to 3.6 V)

Low power dissipation

•

High speed: 288 mW (max) (at 20 MHz, V_CC= 3.6 V)

Small size

Full size (24 × 32 × 1.4 mm³): 32-512 MByte

Reduced size (24 × 18 × 1.4 mm³): 32-256 MByte

Rev.0.02, Sep.15.2004, page 2 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Block Diagram

1

2

3

4

5

6

7

V

CC

V

CS CMD/DI

Internal clock

CLK/SCLK DAT/DO

Interface driver

PP

Generator

OCR[31:0]

CID[127:0]

CSD[127:0]

RCA[15:0]

Interface

Core control

Flash control

Memory core

All units in these Renesas MultiMediaCards are clocked by an internal clock generator. The Interface

driver unit synchronizes the DAT and CMD signals from external CLK to the internal used clock signal.

The card is controlled by the three line MultiMediaCard interface containing the signals: CMD, CLK,

DAT (refer to Chapter “Interfaces”). For the identification of the MultiMediaCard in a stack of

MultiMediaCards, a card identification register (CID) and a relative card address register (RCA) are

foreseen. An additional register contains different types of operation parameters. This register is called

card specific data register (CSD). The communication using the MultiMediaCard lines to access either the

memory field or the registers is defined by the MultiMediaCard standard (refer to Chapter

“Communication”). The card has its own power on detection unit. No additional master reset signal is

required to setup the card after power on. It is protected against short circuit during insertion and removal

while the MultiMediaCard system is powered up (refer to Chapter “Power Supply”). No external

programming voltage supply is required. The programming voltage is generated on card.

These Renesas MultiMediaCards support a second interface operation mode the SPI interface mode. The

SPI mode is activated if the CS signal is asserted (negative) during the reception of the reset command

(CMD0) (refer to Chapter “SPI Communication”).

Rev.0.02, Sep.15.2004, page 3 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Interface

These Renesas MultiMediaCards' interface can operate in two different modes:

•

MultiMediaCard mode

SPI mode

Both modes are using the same pins. The default mode is the MultiMediaCard mode. The SPI mode is

selected by activating (= 0) the CS signal (Pin1) and sending the CMD0.

MultiMediaCard Mode

In the MultiMediaCard mode, all data is transferred over a minimal number of lines:

•

CLK: with each cycle of this signal a one-bit transfer on the command and data lines is done. The

frequency may vary between zero and the maximum clock frequency. The MultiMediaCard bus

master is free to generate these cycles without restrictions in the range of 0 to 20 MHz.

•

CMD: is a bidirectional command channel used for card initialization and data transfer commands.

The CMD signal has two operation modes: open drain for initialization mode and push pull for fast

command transfer. Commands are sent from the MultiMediaCard bus master to the MultiMediaCard

and responses vice versa.

•

DAT: is a bidirectional data channel with a width of one line. The DAT signal of the MultiMediaCard

operates in push pull mode.

RSV: is pulled up with resistor (2 MΩ typ) in the MultiMediaCard. The external pull-up resistor

should be recommended if the system requires.

R

CMD

OD

DAT

CMD

DAT

CLK

1 2 3 4 5 6 7

MultiMediaCard Host

MultiMediaCard

MultiMediaCard Mode Interface

All MultiMediaCards are connected directly to the lines of the MultiMediaCard bus. The following table

defines the card contacts.

Rev.0.02, Sep.15.2004, page 4 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

MultiMediaCard Mode Pad Definition

Pin No.

Name

RSV

CMD

V_SS1

Type*¹

Description

No connection

Command/Response

Ground

1

2

3

4

5

6

7

NC

I/O/PP/OD

S

V_CC

S

Power supply

Clock

CLK

V_SS2

I

S

Ground

DAT

I/O/PP

Data

Note: 1. S: power supply; I: input; O: output; PP: push-pull; OD: open-drain; NC: No connection or V_IH

DAT

enable

V_SS2

CLK

V_CC

V_SS1

CMD

RSV

enable

Interface driver

MultiMediaCard Mode I/O-drivers

Rev.0.02, Sep.15.2004, page 5 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

SPI Mode

The Serial Peripheral Interface (SPI) is a general-purpose synchronous serial interface originally found on

certain Motorola microcontrollers. The MultiMediaCard SPI interface is compatible with SPI hosts

available on the market. As any other SPI device the MultiMediaCard SPI interface consists of the

following four signals:

CS: Host to card Chip Select signal.

CLK: Host to card clock signal.

Data in: Host to card data signal.

Data out: Card to host data signal.

The MultiMediaCard card identification and addressing methods are replaced by a hardware Chip Select

(CS) signal. There are no broadcast commands. For every command, a card (slave) is selected by

asserting (active low) the CS signal (refer to Figure “SPI Bus System”). The CS signal must be

continuously active for the duration of the SPI transaction (command, response and data). The only

exception occurs during card programming, when the host can de-assert the CS signal without affecting the

programming process. The bidirectional CMD and DAT lines are replaced by unidirectional data in and

data out signals. This eliminates the ability of executing commands while data is being read or written and,

therefore, makes the sequential and multi block read/write operations obsolete. The single and multiple

block read/write commands are supported by the SPI channel. The SPI interface uses the same seven

signals of the standard MultiMediaCard bus (refer to Table “SPI Interface Pin Configuration”).

CS

Power

supply

SPI bus master

CS

SPI bus (CLK, Datain, Dataout)

SPI card

SPI Bus System

Rev.0.02, Sep.15.2004, page 6 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

SPI Interface Pin Configuration

MultiMediaCard

SPI

Pin No. Name

Type*¹

Description

Name

Type

Description

Chip select (neg true)

Data in

1

2

3

4

5

6

7

RSV

CMD

V_SS1

NC

Reserved for future use CS

I

I/O/PP/OD

Command/Response

Ground

DI

I

S

V_SS

S

Ground

V_CC

S

Power supply

Clock

V_CC

S

Power supply

Clock

CLK

V_SS2

I

SCLK

V_SS2

DO

I

S

Ground

S

Ground

DAT

I/O/PP

Data

O/PP

Data out

Note: 1. S: power supply; I: input; O: output; PP: push-pull; OD: open-drain; NC: No connection or V_IH

Rev.0.02, Sep.15.2004, page 7 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Registers

These Renesas MultiMediaCards contain the following information registers:

Name

Width

Type

Description

OCR

32

Programmed by the

manufacturer.

Supported voltage range, card power up status bit.

Read only for user.

CID

128

Programmed by the

manufacturer.

Card identification number, card individual number for

identification.

Read only for user.

RCA

CSD

16

Programmed during

initialization, not readable.

Relative card address, local system address of a card,

dynamically assigned by the host during initialization.

128

Programmed by the

manufacturer. Partially

programmable by the user.

Card specific data, information about the card operation

conditions.

The CID and RCA are used for identifying and addressing the MultiMediaCard. The CSD contains the

card specific data record. This record is a set of information fields to define the operation conditions of the

MultiMediaCard.

For the user, the CID is read only register. The CSD contains read only area and some of one time or

multiple programmable area by the customer or provider. They are read out by special commands (refer to

Chapter “Commands”). The RCA registers are write only registers. Unlike CID and CSD, RCA looses its

contents after powering down the card. Its value is reassigned in each initialization cycle. The

MultiMediaCard registers usage in SPI mode is summarized in Table “MultiMediaCard Registers in SPI

Mode”:

MultiMediaCard Registers in SPI Mode

Name

OCR

CID

Available in SPI mode Width (Bytes) Description

Yes

4

Operation condition register.

16

Card identification data (serial number, manufacturer ID

etc.)

RCA

CSD

No

Yes

16

Card specific data, information about the card operation

conditions.

Rev.0.02, Sep.15.2004, page 8 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Operation Condition Register (OCR)

This register indicates supported voltage range of these Renesas MultiMediaCards. It is a 32 bit wide

register and for read only.

OCR Fields

OCR slice

D31

D[30-24]

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

Field

Value

Note

Card power up status bit (Busy). 0 or 1

Busy: 0

Reserved

0

1

0

3.5 V ≤ V_CC≤ 3.6 V

3.4 V ≤ V_CC< 3.5 V

3.3 V ≤ V_CC< 3.4 V

3.2 V ≤ V_CC< 3.3 V

3.1 V ≤ V_CC< 3.2 V

3.0 V ≤ V_CC< 3.1 V

2.9 V ≤ V_CC< 3.0 V

2.8 V ≤ V_CC< 2.9 V

2.7 V ≤ V_CC< 2.8 V

2.6 V ≤ V_CC< 2.7 V

2.5 V ≤ V_CC< 2.6 V

2.4 V ≤ V_CC< 2.5 V

2.3 V ≤ V_CC< 2.4 V

2.2 V ≤ V_CC< 2.3 V

2.1 V ≤ V_CC< 2.2 V

2.0 V ≤ V_CC< 2.1 V

1.65 V ≤ V_CC≤ 1.95 V

Reserved

D8

D7

D6

D5

Reserved

D4

Reserved

D3

Reserved

D2

Reserved

D1

Reserved

D0

Reserved

Rev.0.02, Sep.15.2004, page 9 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Card Identification (CID)

This register contains the card identification information used during the card identification procedure. It

is a 128 bit wide register, one-time programmable by the provider. It was programmed at the

manufacturer. The CID is divided into eight slices:

CID Fields

Name

Field

MID

Width

CID-slice

[127:120]

[119:104]

[103:56]

[55:48]

[47:16]

[15:8]

Note

Manufacturer ID

OEM/Application ID

Product name

8

1

OID

16

48

8

PNM

PRV

PSN

MDT

CRC7

Product revision

Product serial number

Manufacturing date

7-bit CRC checksum

Not used, always 1

32

8

7

[7:1]

1

[0:0]

Note: 1. The value of MID is 0x06.

The CID has to be error free. To ensure the correctness of the CID, a 7-bit CRC checksum is added to the

end of the CID. The CRC7 is computed according to chapter “Cyclic Redundancy Check (CRC)”.

Relative Card Address (RCA)

The 16-bit relative card address register carries the card address assigned by the host during the card

identification. This address is used for the addressed host to card communication after the card

identification procedure. The default value of the RCA register is 0x0001. The value 0x0000 is reserved

to set all cards in Standby State with the command SELECT_DESELECT_CARD (CMD7). The RCA is

programmed with the command SET_RELATIVE_ADDRESS (CMD3) during the initialization procedure.

The content of this register is lost after power down. The default value is assigned when an internal reset is

applied by the power up detection unit of these Renesas MultiMediaCards, or when the command

GO_IDLE_STATE (CMD0) is detected by these Renesas MultiMediaCards.

Rev.0.02, Sep.15.2004, page 10 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Card Specific Data (CSD)

The card specific data register describes how to access the card content. The CSD defines card operating

parameters like maximum data access time, data transfer speed.

The CSD Fields

Name

Field

Width CSD-slice Value

Type

CSD structure

Spec version

Reserved

CSD_STRUCTURE

SPEC_VERS

2

4

2

8

[127:126] “10”

read only

[125:122] “0011”

[121:120]

0

Data read access-time-1

TAAC

[119:112] 0x0E (1 ms)

Data read access-time-2 in NSAC

[111:104] 0x01 (100 cycles) read only

CLK cycles (NSAC*100)

Max. data transfer rate

Card command classes

TRAN_SPEED

CCC

8

[103:96]

[95:84]

0x2A (20 Mbit/s)

read only

12

0x0FF (class 0, 1, read only

2, 3, 4, 5, 6, 7)

Max. read data block length READ_BLK_LEN

4

1

[83:80]

[79:79]

0x9 (512 bytes)

read only

Partial blocks for read

allowed

READ_BLK_PARTIAL

‘1’ (Enabled)

Write block misalignment

WRITE_BLK_MISALIG

N

1

[78:78]

‘0’ (Disabled)

read only

Read block misalignment

DSR implemented

Reserved

READ_BLK_MISALIGN 1

[77:77]

[76:76]

[75:74]

[73:62]

[61:59]

[58:56]

[55:53]

[52:50]

[49:47]

[46:42]

[41:37]

‘0’ (Disabled)

0

read only

DSR_IMP

1

2

1

Device size

C_SIZE

12

3

*

2

Max. read current at V_DDmin VDD_R_CURR_MIN

Max. read current at V_DDmax VDD_R_CURR_MAX

Max. write current at V_DDmin VDD_W_CURR_MIN

Max. write current at V_DDmax VDD_W_CURR_MAX

*

2

3

*

2

3

*

2

3

*

3

Device size multiplier

Erase group size

C_SIZE_MULT

3

*

ERASE_GRP_SIZE

ERASE_GRP_MULT

5

0

Erase group size multiplier

5

0x0F

Rev.0.02, Sep.15.2004, page 11 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Name

Field

Width CSD-slice Value

Type

Write protect group size

Write protect group enable

Manufacturer default ECC

Write speed factor

WP_GRP_SIZE

WP_GRP_ENABLE

DEFAULT_ECC

R2W_FACTOR

5

1

2

3

4

[36:32]

[31:31]

[30:29]

[28:26]

[25:22]

[21:21]

0x01 (16 KByte)

read only

‘1’

0

4 (16)

Max. write data block length WRITE_BLK_LEN

9 (512 Bytes)

‘0’

Partial blocks for write

allowed

WRITE_BLK_PARTIAL 1

Reserved

4

[20:17]

[16:16]

0

read only

Content protection application CONTENT_PROT_AP

P

1

File format group

FILE_FORMAT_GRP

COPY

1

[15:15]

[14:14]

[13:13]

×*⁴

×

read/write

Copy flag (OTP)

Permanent write protection

PERM_WRITE_PROTE 1

CT

×

Temporary write protection

TMP_WRITE_PROTEC 1

T

[12:12]

×

read/write/

erase

File format

ECC code

FILE_FORMAT

ECC

2

[11:10]

[9:8]

×

read/write

read/write/

erase

7-bit CRC

CRC7

7

[7:1]

×

read/write/

erase

Not used, always 1

1

[0:0]

1

read only

Notes: 1. This field is depended on the model. Refer to also C_SIZE.

2. This field is depended on the model.

3. This field is depended on the model. Refer to also C_SIZE_MULT.

4. × means user programmable.

Some of the CSD fields are one-time or multiple programmable by the customer or provider. All other

field values are fixed. The following section describes the CSD fields and their values for these Renesas

MultiMediaCards:

•

CSD_STRUCTURE

CSD Register Structure

CSD_STRUCTURE

CSD register structure

“10”

CSD version No. 1.2

The CSD version of these Renesas MultiMediaCards is related to the “MultiMediaCard system

specification, Version 3.3”. The parameter CSD_STRUCTURE has permanently the value “10”.

Rev.0.02, Sep.15.2004, page 12 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

SPEC_VERS

•

Defines the Spec version supported by the card. It includes the commands set definition and the definition

of the card responses. The card identification procedure is compatible for all spec versions!

SPEC Version

SPEC_VERS

System specification version number

“0011”

System specification version 3.3

The Spec version of these Renesas MultiMediaCards is related to the “MultiMediaCard system

specification, Version 3.3”. The parameter SPEC_VERS has permanently the value “0011”.

•

TAAC

Defines the asynchronous data access time:

TAAC Access Time Definition

TAAC bit

Description

Values

2:0

Time exponent

0 = 1 ns, 1 = 10 ns, 2 = 100 ns, 3 = 1 µs, 4 = 10 µs,

5 = 100 µs, 6 = 1 ms, 7 = 10 ms

6:3

7

Time mantissa

Reserved

0 = reserved, 1 = 1.0, 2 = 1.2, 3 = 1.3, 4 = 1.5,

5 = 2.0, 6 = 2.5, 7 = 3.0, 8 = 3.5, 9 = 4.0, A = 4.5,

B = 5.0, C = 5.5, D = 6.0, E = 7.0, F = 8.0

Always ‘0’

The value for the asynchronous delay for these Renesas MultiMediaCards is 1 ms. The coded TAAC value

is 0x0E (= 1 ms). For more details refer to Chapter “Operating Characteristics”.

•

NSAC

Defines the worst case for the synchronous data access time. The unit for NSAC is 100-clock cycles.

Therefore, maximum value for the data access time is 25.6k clock cycles. The total access time N_ACas

expressed in the Table “Timing Values” is the sum of both TAAC and NSAC. It has to be computed by

the host for the actual clock rate. The read access time should be interpreted as a typical delay for the first

data bit of a data block or stream. The value of NSAC for these Renesas MultiMediaCards is 0x01 (100-

clock cycles). For more details refer to Chapter “Operating Characteristics”.

Rev.0.02, Sep.15.2004, page 13 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

TRAN_SPEED

•

The following table defines the maximum data transfer rate TRAN_SPEED:

Maximum Data Transfer Rate Definition

TRAN_SPEED bit

Description

Values

2:0

Transfer rate exponent

0 = 100 Kbit/s, 1 = 1 Mbit/s, 2 = 10

Mbit/s, 3 = 100 Mbit/s, 4...7 =

reserved

6:3

7

Time mantissa

Reserved

0x0 = reserved, 0x1 = 1.0, 0x2 = 1.2,

0x3 = 1.3, 0x4 = 1.5, 0x5 = 2.0, 0x6

= 2.5, 0x7 = 3.0, 0x8 = 3.5, 0x9 =

4.0, 0xA = 4.5, 0xB = 5.0, 0xC = 5.5,

0xD = 6.0, 0xE = 7.0, 0xF = 8.0

Always ‘0’

These Renesas MultiMediaCards support a transfer rate between 0 and 20 Mbit/s. The parameter

TRAN_SPEED is 0x2A.

•

CCC

The MultiMediaCard command set is divided into subsets (command classes). The card command class

register CCC defines which command classes are supported by this card. A set CCC bit means that the

corresponding command class is supported. For command class definition refer to Table “Command

Classes”.

Supported Card Command Classes

CCC bit

Supported card command classes

0

class0

class1

......

1

......

11

class11

These Renesas MultiMediaCards support the command classes 0, 1, 2, 3, 4, 5, 6 and 7. The parameter

CCC is permanently assigned to the value 0x0FF.

Rev.0.02, Sep.15.2004, page 14 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

•

READ_BLK_LEN

The data block length is computed as 2^READ_BLK_LEN

.

Data Block Length

READ_BLK_LEN

Block length

2⁰= 1 byte

2¹= 2 bytes

......

Remark

0

1

......

11

2¹¹= 2048 bytes

12−15

Reserved

The block length might therefore be in the range 1, 2, 4...2048 bytes. This parameter defines the block

length if READ_BLK_PARTIAL is not set. If READ_BLK_PARTIAL is set this parameter contains the

maximum allowed value of the block length in bytes. All block lengths between one and this value are

permitted. The actual block size is programmed by the command SET_BLOCKLEN (CMD16). These

Renesas MultiMediaCards support block lengths from 1 byte up to 2048 bytes. The default value of the

parameter READ_BLK_LEN is 0x9 (512 bytes).

•

READ_BLK_PARTIAL

READ_BLK_PARTIAL defines whether partial block sizes can be used in block read command.

READ_BLK_PARTIAL = 0 means that only the block size defined by READ_BLK_LEN can be used for

block-oriented data transfers. READ_BLK_PARTIAL = 1 means that smaller blocks can be used as well.

The minimum block size will be equal to minimum addressable unit (one byte). These Renesas

MultiMediaCards support partial block read. The parameter READ_BLK_PARTIAL is permanently

assigned to the value ‘1’.

•

WRITE_BLK_MISALIGN

Defines if the data block to be written by one command can be spread over more than one physical blocks

of the memory device. The size of the memory block is defined in WRITE_BLK_LEN.

WRITE_BLK_MISALIGN is permanently assigned to the value ‘0’, signaling that crossing physical block

boundaries is not allowed.

•

READ_BLK_MISALIGN

Defines if the data block to be read by one command can be spread over more than one physical block of

the memory device. The size of the data block is defined in READ_BLK_LEN.

READ_BLK_MISALIGN = 0 signals that crossing physical block boundaries is not allowed.

READ_BLK_MISALIGN = 1 signals that crossing physical block boundaries is allowed. These Renesas

MultiMediaCards do not support read block operations with boundary crossing. The parameter

READ_BLK_MISALIGN is permanently assigned to the value ‘0’.

Rev.0.02, Sep.15.2004, page 15 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

DSR_IMP

•

Defines if the configurable driver stage option is integrated on the card or not. If implemented a driver

stage register (DSR) must be implemented also.

DSR Implementation

DSR_IMP

DSR type

0

1

No DSR implemented

DSR implemented

These Renesas MultiMediaCards' output drivers are not configurable. The parameter DSR_IMP is

permanently assigned to the value ‘0’.

•

C_SIZE

This parameter is used to compute the card capacity. The card capacity is computed from the entries

C_SIZE, C_SIZE_MULT and READ_BLK_LEN as follows:

memory capacity = BLOCKNR * BLOCK_LEN

Where

BLOCKNR = (C_SIZE+1) * MULT

MULT = 2^{C_SIZE_MULT+2}

(C_SIZE_MULT < 8)

BLOCK_LEN = 2^READ_BLK_LEN

(READ_BLK_LEN < 12)

Therefore, the maximal capacity which can be coded is 4096 * 512 * 2048 = 4 GBytes.

The following table shows the parameters for each card capacity.

Card Capacity

32 MByte

C_SIZE

0x7A7

C_SIZE_MULT

READ_BLK_LEN

3

4

5

6

7

9

64 MByte

128 MByte

256 MByte

512 MByte

Rev.0.02, Sep.15.2004, page 16 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

VDD_R_CURR_MIN, VDD_W_CURR_MIN

•

The maximum supply current at the minimum supply voltage V_CC(2.7 V) is coded as follows:

Maximum Supply Current Consumption at V_CC= 2.7 V

VDD_R_CURR_MIN

VDD_W_CURR_MIN

Code for current consumption at 2.7 V

2:0

0 = 0.5 mA; 1 = 1 mA; 2 = 5 mA; 3 = 10 mA; 4 = 25 mA; 5 = 35 mA; 6 =

60 mA; 7 = 100 mA

The parameter VDD_R_CURR_MIN and VDD_W_CURR_MIN are permanently assigned. The value of

VDD_R_CURR_MIN and VDD_W_CURR_MIN for each model is following:

Card Capacity

32 MByte

Value

6 (60 mA)

64 MByte

128 MByte

256 MByte

512 MByte

•

VDD_R_CURR_MAX, VDD_W_CURR_MAX

The maximum supply current at the maximum supply voltage V_CC(3.6 V) is coded as follows:

Maximum Supply Current Consumption at V_CC= 3.6 V

VDD_R_CURR_MAX

VDD_W_CURR_MAX

Code for current consumption at 3.6 V

2:0

0 = 1 mA; 1 = 5 mA; 2 = 10 mA; 3 = 25 mA; 4 = 35 mA; 5 = 45 mA; 6 =

80 mA; 7 = 200 mA

The parameter VDD_R_CURR_MAX and VDD_W_CURR_MAX are permanently assigned. The value

of VDD_R_CURR_MAX and VDD_W_CURR_MAX for each model is following:

Rev.0.02, Sep.15.2004, page 17 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Card Capacity

32 MByte

Value

6 (80 mA)

64 MByte

128 MByte

256 MByte

512 MByte

For more details refer to Chapter “Characteristics”.

•

C_SIZE_MULT

This parameter is used for coding a factor MULT for computing the total device size (refer to “C_SIZE”).

The factor MULT is defined as 2^{C_SIZE_MULT+2}

.

Multiply Factor for the Device Size

C_SIZE_MULT

MULT

Remark

0

1

2

3

4

5

6

7

2²= 4

2³= 8

2⁴= 16

2⁵= 32

2⁶= 64

2⁷= 128

2⁸= 256

2⁹= 512

The card capacity is shown at “C_SIZE”.

•

ERASE_GRP_SIZE

The content of this register is a 5 bit binary coded value, used to calculate the size of the erasable unit of

these Renesas MultiMediaCards. The size of the erase unit (also referred to as erase group in chapter

“Memory Array Partitioning”) is determined by the ERASE_GRP_SIZE and the ERASE_GRP_MULT

entries of the CSD, using the following equation:

size of erasable unit = (ERASE_GRP_SIZE + 1) * (ERASE_GRP_MULT + 1)

The parameter ERASE_GRP_SIZE is permanently assigned to the value ‘0’. The size of erasable unit for

these Renesas MultiMediaCards is (0+1) * (15+1) = 16, which means that the 8 KByte area can be erased

in a single erase group command (CMD35, CMD36 and CMD38).

Rev.0.02, Sep.15.2004, page 18 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

ERASE_GRP_MULT

•

A 5 bit binary coded value is used for calculating the size of the erasable unit of these Renesas

MultiMediaCards. The parameter ERASE_GRP_MULT is permanently assigned to the value 0x0F. See

ERASE_GRP_SIZE section for detailed description.

•

WP_GRP_SIZE

The size of a write protection group. The content of this register is a binary coded value defining the

number of erase group. This parameter's value is 1, which means that a write protect group size is 16

KByte.

•

WP_GRP_ENABLE

The value is set to ‘1’, meaning group write protection is enabled.

•

DEFAULT_ECC

Set by the card manufacturer and defines the ECC code which is recommended to use (e.g. the device is

tested for). The value is set to ‘0’, indicating that no designated ECC is recommended.

•

R2W_FACTOR

Defines the typical block program time as a multiple of the read access time. The following table defines

the field format.

R2W_FACTOR

Multiples of read access time

0

1

2 (write half as fast as read)

2

4

3

8

4

16

5

32

6, 7

Reserved

This parameter value is 2 for these Renesas MultiMediaCards.

Rev.0.02, Sep.15.2004, page 19 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

•

WRITE_BLK_LEN

The data block length is computed as 2^{WRITE_BLK_LEN}

.

Data Block Length

WRITE_BLK_LEN

Block length

2⁰= 1 byte

2¹= 2 bytes

......

Remark

0

1

......

11

2¹¹= 2048 bytes

12−15

Reserved

The block length might therefore be in the range 1, 2, 4...2048 bytes. This parameter defines the block

length if WRITE_BLK_PARTIAL is not set. If WRITE_BLK_PARTIAL is set this parameter contains the

maximum allowed value of the block length in bytes. All block lengths between one and this value are

permitted. The actual block size is programmed by the command SET_BLOCKLEN (CMD16). These

Renesas MultiMediaCards support blocks with the length 512 bytes. The parameter WRITE_BLK_LEN is

permanently assigned to the value 0x9 (512 bytes).

•

WRITE_BLK_PARTIAL

WRITE_BLK_PARTIAL defines whether partial block sizes can be used in block read and block write

commands. WRITE_BLK_PARTIAL = 0 means that only the block size defined by WRITE_BLK_LEN

can be used for block-oriented data transfers. WRITE_BLK_PARTIAL = 1 means that smaller blocks can

be used as well. The minimum block size will be equal to minimum addressable unit (one byte). These

Renesas MultiMediaCards support no partial block write. The parameter WRITE_BLK_PARTIAL is

permanently assigned to the value ‘0’.

•

CONTENT_PROT_APP

Indicates whether the card supports the content protection application, which is the function to protect the

stored data from illegal copies or accesses. This card doesn't support the content protection application.

The parameter CONTENT_PROT_APP is permanently assigned to the value ‘0’.

•

FILE_FORMAT_GRP

Indicates the selected group of file formats. The default value is ‘0’. This field is read-only for ROM. The

usage of this field is shown in table “File_Formats”.

Rev.0.02, Sep.15.2004, page 20 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

COPY

•

Defines if the contents are an original (COPY = ‘0’) or a copy (= ‘1’). The COPY bit is a one time

programmable bit, being set by the customer. The default value is ‘0’.

•

PERM_WRITE_PROTECT

Permanently protects the whole card content against overwriting or erasing (all write and erase commands

for this card is a permanently disabled). This parameter is one-time programmable by the customer. The

default value is ‘0’ (not protected).

•

TMP_WRITE_PROTECT

Temporarily protects the whole card content from being overwritten or erased (all write and erase

commands for this card are temporarily disabled). This parameter is programmable by the customer. The

default value is ‘0’ (not protected).

•

FILE_FORMAT

Indicates the file format on the card. The default value is ‘0’. This field is read-only for ROM. The

following formats are defined:

File_Formats

FILE_FORMAT_GRP

FILE_FORMAT Type

0

1

0

Hard disk-like file system with partition table

1

DOS FAT (floppy-like) with boot sector only (no partition table)

2

Universal File Format

Others/Unknown

Reserved

3

0, 1, 2, 3

Rev.0.02, Sep.15.2004, page 21 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

ECC

•

Defines the ECC code that was used for storing data on the card. This field is used by the host (or

application) to decode the user data. The following table defines the field format.

ECC

0

ECC type

Maximum number of correctable bits

None (default)

BCH (542,512)

Reserved

None

3

1

2−3

The content provider or customer defines which kind of error correction may be used to protect the

contents of the MultiMediaCard. This value is programmable.

•

CRC7

The CRC7 contains the check sum for the CSD content. The check sum is computed according to chapter

“Cyclic Redundancy Check (CRC)”.

The user has to recalculate a new CRC7 after defining a new CSD.

Rev.0.02, Sep.15.2004, page 22 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

MultiMediaCard Communication

All communication between host and cards is controlled by the host (master). The host sends commands

and, depending on the command, receives a corresponding response from the selected card. In this chapter

the commands to control these Renesas MultiMediaCards, the card responses and the contents of the status

and error field included in the responses, are defined.

Memory Array Partitioning

The basic unit of data transfer to/from the MultiMediaCard is one byte. All data transfer operations which

require a block size always define block lengths as integer multiples of bytes. Some special functions need

other partition granularity. For block-oriented commands, the following definition is used:

•

Block: is the unit which is related to the block-oriented read and write commands. Its size is the

number of bytes which will be transferred when one block command is sent by the host. The size of a

block is either programmable or fixed. The information about allowed block sizes and the

programmability is stored in the CSD.

For devices which have erasable memory cells, special erase commands are defined. The granularity of the

erasable units is:

•

Sector: In these Renesas MultiMediaCards, this size is same as the WRITE_BLK_LEN in CSD.

Erase Group: is the smallest number of consecutive write blocks, which can be addressed for erased.

The size of the Erase Group is card specific and stored in the CSD.

For devices which include a write protection:

•

WP-Group: is the minimal unit which may have individual write protection. Its size is the number of

erase groups which will be write protected by one bit. The size of a WP-group is fixed for each

device. The information about the size is stored in the CSD.

Each erasable unit (erase group) has a special “tag” bit. This bit may be set or cleared by special

commands to tag the unit. All tagged units will be erased in parallel by one erase command following a

number of tag commands. All tag bits are cleared by each command except a tag command. Therefore,

immediately after a sequence of tag commands an erase command has to be sent by the host. Commands

others than tagging or erasing abort a tag-erase cycle irregularly.

Rev.0.02, Sep.15.2004, page 23 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

MultiMediaCard

ERASE

GROUP 0

Write

Block 0 Block 1 Block 2 Block 3 Block n

ERASE

GROUP 1

ERASE

GROUP n

Erase Tagging Hierarchy

Each WP-group may have an additional write protection bit. The write protection bits are programmable

via special commands (refer to Chapter “Commands”). The information about the availability is stored in

the CSD.

WP-GROUP 0

WP-GROUP 1

WP-GROUP n

Write Protection

Rev.0.02, Sep.15.2004, page 24 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Commands

The command set of the MultiMediaCard system is divided into classes corresponding to the type of card

(see also [1]). These Renesas MultiMediaCards support the following command classes:

Command Classes (class 0 to class 2)

Supported commands

Card command

class (CCC)

0

1

2

3

4

7

9

10 11 12 13 15 16 17 18

Class description

basic

class 0

class 1

class 2

+

stream read

block read

+

Command Classes (class 2 to class 7)

Supported commands

Card command

20 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 42

class (CCC)

Class description

block read

class 2

+

class 3

stream write

block write

erase

+

class 4

+

class 5

+

class 6

write protection

lock card

+

class 7

+

Class 0 is mandatory and supported by all cards. It represents the card identification and initialization

commands, which are intended to handle different cards and card types on the same bus lines. The Card

Command Class (CCC) is coded in the card specific data register of each card, so that the host knows how

to access the card. There are four kinds of commands defined on the MultiMediaCard bus:

•

broadcast commands (bc) sent on CMD line, no response

broadcast commands with response (bcr) sent on CMD line, response (all cards simultaneously) on

CMD line

•

addressed (point-to-point) commands (ac) sent on CMD line, response on CMD line

addressed (point-to-point) data transfer commands (adtc) sent on CMD line, response on CMD line,

data transfer on DAT line

Rev.0.02, Sep.15.2004, page 25 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

The command transmission always starts with the MSB. Each command starts with a start bit and ends

with a 7-bit CRC command protection field followed by an end bit. The length of each command frame is

fixed to 48 bits (2.4 µs at 20 MHz):

0

1

bit5...bit0

command argument

Note: 1. (Cyclic Redundancy Check)

bit31...bit0 bit6...bit0

1

start bit host

CRC*¹

end bit

The start bit is always ‘0’ in command frames (sent from host to MultiMediaCard). The host bit is always

‘1’ for commands. The command field contains the binary coded command number. The argument

depends on the command (refer to Table “Basic Commands (class 0) and Table “Block-Oriented Read

Commands (class 2)”). The CRC field is defined in Chapter “Cyclic Redundancy Check (CRC)”.

Rev.0.02, Sep.15.2004, page 26 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Read, Write and Erase Time-out Conditions

The times after which a time-out condition for read/write/erase operations occurs are (card independent) 10

times longer than the access/program times for these operations given below. A card shall complete the

command within this time period, or give up and return an error message. If the host does not get a

response within the defined time-out it should assume the card is not going to respond anymore and try to

recover (e.g. reset the card, power cycle, reject, etc.). The typical access and program times are defined as

follows:

Read

The read access time is defined as the sum of the two times given by the CSD parameters TAAC and

NSAC (refer to Table “Card Specific Data (CSD)”). These card parameters define the typical delay

between the end bit of the read command and the start bit of the data block. This number is card dependent

and should be used by the host to calculate throughput and the maximal frequency for stream read.

Write

The R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by

multiplying the read access time by this factor. It applies to all write/erase commands (e.g.

SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands). It should be

used by the host to calculate throughput and the maximal frequency for stream write.

Erase

The duration of an erase command will be (order of magnitude) the number of write blocks to be erased

multiplied by the block write delay.

Rev.0.02, Sep.15.2004, page 27 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Basic Commands (class 0) and Read Stream Command (class 1)

CMD

index

Type Argument

Resp

Abbreviation

Command description

CMD0 bc

CMD1 bcr

[31:0] stuff bits

GO_IDLE_STATE Resets all cards to Idle State

[31:0] OCR

without busy

R3

SEND_OP_COND Checks for cards not supporting the

full range of 2.0 V to 3.6 V. After

receiving CMD1 the card sends an R3

response (refer to Chapter

“Responses”).

CMD2 bcr

CMD3 ac

CMD4 bc

CMD7 ac

[31:0] stuff bits

R2

R1

ALL_SEND_CID

Asks all cards in ready state to send

their CID*¹numbers on CMD-line

[31:16] RCA

[15:0] stuff bits

SET_RELATIVE_A Assigns relative address to the card in

DDR

identification state.

[31:16] DSR

[15:0] stuff bits

SET_DSR

Programs the DSR of all cards in

stand-by state.

[31:16] RCA

R1b (only SELECT/

Command toggles a card between the

[15:0] stuff bits

the

selected

card)

DESELECT_CARD standby and transfer states or between

the programming and disconnect state.

In both cases the card is selected by

its own relative address while

deselecting the prior selected card.

Address 0 deselects all.

CMD9 ac

CMD10 ac

[31:16] RCA

[15:0] stuff bits

R2

SEND_CSD

SEND_CID

Asks the addressed card to send its

card-specific data (CSD)*²on CMD-

line.

[31:16] RCA

[15:0] stuff bits

R2

R1

Asks the addressed card to send its

card identification (CID) on CMD-line.

CMD11 adtc [31:0] data

address

READ_DAT_UNTIL Reads data stream from the card,

_STOP

starting at the given address, until a

STOP_TRANSMISSION follows.

CMD12 ac

CMD13 ac

CMD15 ac

[31:0] stuff bits

R1b*³

STOP_TRANSMISS Forces the card to stop transmission

ION

[31:16] RCA

[15:0] stuff bits

R1

SEND_STATUS

Asks the addressed card to send its

status register.

[31:16] RCA

GO_INACTIVE_ST Sets the card to inactive state in order

[15:0] stuff bits

ATE

to protect the card stack against

communications breakdowns.

Notes: 1. CID register consists of 128 bits (starting with MSB, it is preceded by an additional start bit, ends

with an end bit)

2. CSD register consists of 128 bits (starting with MSB, it is preceded by an additional start bit,

ends with an end bit)

3. This command is indicating the busy status of the MultiMediaCard via the data channel.

Rev.0.02, Sep.15.2004, page 28 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Block-Oriented Read Commands (class 2)

CMD

index

Type Argument

Resp

Abbreviation

Command description

CMD16 ac

[31:0] block

length

R1

SET_BLOCKLEN

Selects a block length (in bytes) for all

following block-oriented read

commands and lock card command.*¹

CMD17 adtc [31:0] data

address

R1

READ_SINGLE_BL Reads a block of the size selected by

OCK

the SET_BLOCKLEN command.*²

CMD18 adtc [31:0] data

address

READ_MULTIPLE_ Continuously send blocks of data until

BLOCK interrupted by a stop.

Notes: 1. The default block length is as specified in the CSD. These Renesas MultiMediaCards do not

support partial block write, so the write block size defined by WRITE_BLK_LEN is permanently

assigned to the value 512 bytes.

2. The data transferred must not cross a physical block boundary unless READ_BLK_MISALIGN is

set in the CSD. These Renesas MultiMediaCards do not support read block operations with

boundary crossing (READ_BLK_MISALIGN = ‘0’), so the data transferred must not cross a

physical block boundary.

Stream Write Command (class 3)

CMD

index

Type Argument

Resp

Abbreviation

Command description

CMD20 adtc [31:0] data

address

R1

WRITE_DAT_

UNTIL_STOP

Writes data stream from the host,

starting at the given address, until a

STOP_TRANSMISSION follows.

Block-Oriented Read/Write Command (class 2/4)

CMD

index

Type Argument

Resp

Abbreviation

Command description

CMD23 ac

[31:16] set to 0

[15:0] number of

blocks

R1

SET_BLOCK_COU Defines the number of blocks which

NT

are going to be transferred in the

immediately succeeding multiple block

read or write command.

Rev.0.02, Sep.15.2004, page 29 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Block-Oriented Write Commands (class 4)

CMD

index

Type Argument

Resp

Abbreviation

Command description

CMD24 adtc [31:0] data

address

R1

WRITE_BLOCK

Write a block. The write-block-length

of the Renesas MultiMediaCard is

permanently assigned to the value 512

bytes.*¹

CMD25 adtc [31:0] data

address

R1

WRITE_MULTIPLE Continuously writes blocks of data until

_BLOCK

a STOP_TRANSMISSION follows.

CMD26 adtc [31:0] stuff bits

PROGRAM_CID

Programming of the card identification

register. This command is only done

once per MultiMediaCard card. The

card has some hardware to prevent

this operation after the first

programming. Normally this command

is reserved for the manufacturer. The

CID register is programmed at the

manufacturer.

CMD27 adtc [31:0] stuff bits

R1

PROGRAM_CSD

Programming of the programmable bits

of the CSD.

Note: 1. The data transferred must not cross a physical block boundary unless WRITE_BLK_MISALIGN

is set in the CSD. These Renesas MultiMediaCards do not support write block operations with

boundary crossing (WRITE_BLK_MISALIGN = ‘0’), so the data transferred must not cross a

physical block boundary.

Erase Commands (class 5)

CMD

index

Type Argument

Resp

Abbreviation

Command description

CMD32 Not supported

CMD33 Not supported

CMD34 Not supported

CMD35 ac

[31:0] data

address

R1

TAG_ERASE_GRO Sets the address of the first erase

UP_START

group within a range to be selected for

erase

CMD36 ac

[31:0] data

address

TAG_ERASE_GRO Sets the address of the last erase

UP_END

group within a continuous range to be

selected for erase

CMD37 Not supported

CMD38 ac [31:0] stuff bits

R1b

ERASE

Erases all previously selected groups

Rev.0.02, Sep.15.2004, page 30 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Write Protection Commands (class 6)

CMD

index

Type Argument

Resp

Abbreviation

Command description

CMD28 ac

[31:0] data

address

R1b

SET_WRITE_PROT If the card has write protection

features, this command sets the write

protection bit of the addressed group.

The properties of write protection are

coded in the card specific data

(WP_GRP_SIZE).

CMD29 ac

[31:0] data

address

R1b

R1

CLR_WRITE_PROT If the card provides write protection

features, this command clears the

write protection bit of the addressed

group.

CMD30 adtc [31:0] write

protect data

SEND_WRITE_PR If the card provides write protection

OT

features, this command asks the card

to send the status of the write

protection bits.*¹

address

Note: 1. 32 write protection bits (representing 32 write protect groups starting at the specified address)

followed by 16 CRC bits are transferred in a payload format via the data line. The last (least

significant) bit of the protection bits corresponds to the first addressed group. If the addresses

of the last groups are outside the valid range, then the corresponding write protection bits shall

be set to zero.

Lock Card Command (class 7)

CMD

index

Type Argument

Resp

Abbreviation

Command description

CMD42 adtc [31:0] stuff bits

R1b

LOCK_UNLOCK

Used to set/reset the password or

lock/unlock the card. The size of the

data block is set by the

SET_BLOCK_LEN command.

Rev.0.02, Sep.15.2004, page 31 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Other Command

CMD index Type

Argument

Resp

Abbreviation Command description

CMD5

CMD6

CMD8

CMD14

CMD19

Reserved

CMD21 … Reserved

CMD22

CMD31

CMD39

Reserved

Not

supported

CMD40

Not

supported

CMD41

Reserved

CMD43 … Reserved

CMD54

CMD55

ac

[31:16] RCA

[15:0] stuff bits

R1

APP_CMD

GEN_CMD

Indicates to the card that the next

command is an application specific

command rather than a standard

command

These Renesas MultiMediaCards

do not support this command.

CMD56

adtc

[31:1] RCA

R1b

Used either to transfer a data block to

the card or to get a data block from

the card for general purpose /

[0] RD/WR*¹

application specific commands. The

size of the data block shall be set by

the SET_BLOCK_LEN command.

These Renesas MultiMediaCards

do not support this command.

CMD57 … Reserved

CMD63

Note: 1. ‘1’ the host gets a block of data from the card.

‘0’ the host sends block of data to the card.

Rev.0.02, Sep.15.2004, page 32 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Card identification mode

All the data communication in the card identification mode uses only the command line (CMD).

Power on

Idle state

CMD0

from all states except (ina)

(idle)

card is busy or

host omitted

voltage range

Inactive state

(ina)

CMD1

CMD15

cards with non-compatible voltage range

card loses bus

Ready state

(ready)

card wins bus

CMD2

Identification state

(ident)

card-identification mode

CMD3

data-transfer mode

from all states in data-transfer mode

Stand-by state

(stby)

MultiMediaCard State Diagram (Card Identification Mode)

The host starts the card identification process in open drain mode with the identification clock rate f_OD

(generated by a push pull driver stage). The open drain driver stages on the CMD line allow the parallel

card operation during card identification. After the bus is activated the host will request the cards to send

their valid operation conditions with the command SEND_OP_COND (CMD1). Since the bus is in open

drain mode, as long as there is more than one card with operating conditions restrictions, the host gets in

the response to the CMD1 a “wired or” operation condition restrictions of those cards. The host then must

pick a common denominator for operation and notify the application that cards with out of range

parameters (from the host perspective) are connected to the bus. Incompatible cards go into Inactive State

(refer to also Chapter “Operating Voltage Range Validation”). The busy bit in the CMD1 response can be

used by a card to tell the host that it is still working on its power-up/reset procedure (e.g. downloading the

register information from memory field) and is not ready yet for communication. In this case the host must

repeat CMD1 until the busy bit is cleared. After an operating mode is established, the host asks all cards

for their unique card identification (CID) number with the broadcast command ALL_SEND_CID (CMD2).

All not already identified cards (i.e. those which are in Ready State) simultaneously start sending their CID

numbers serially, while bit-wise monitoring their outgoing bitstream. Those cards, whose outgoing CID

bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending

Rev.0.02, Sep.15.2004, page 33 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

their CID immediately and must wait for the next identification cycle (cards stay in the Ready State).

There should be only one card which successfully sends its full CID-number to the host. This card then

goes into the Identification State. The host assigns to this card (using CMD3, SET_RELATIVE_ADDR) a

relative card address (RCA, shorter than CID), which will be used to address the card in future

communication (faster than with the CID). Once the RCA is received the card transfers to the Standby

State and does not react to further identification cycles. The card also switches the output drivers from the

open-drain to the push-pull mode in this state. The host repeats the identification process as long as it

receives a response (CID) to its identification command (CMD2). When no card responds to this

command, all cards have been identified. The time-out condition to recognize this, is waiting for the start

bit for more than 5 clock periods after sending CMD2.

Operating Voltage Range Validation

The MultiMediaCard standards operating range validation is intended to support reduced voltage range

MultiMediaCards. These Renesas MultiMediaCards support the range of 2.7 V to 3.6 V supply voltage.

So these Renesas MultiMediaCards send a R3 response to CMD1 which contains an OCR value of

0x80FF8000 if the busy flag is set to “ready” or 0x00FF8000 if the busy flag is active (refer to Chapter

“Responses”). By omitting the voltage range in the command, the host can query the card stack and

determine the common voltage range before sending out-of-range cards into the Inactive State. This bus

query should be used if the host is able to select a common voltage range or if a notification to the

application of non usable cards in the stack is desired. Afterwards, the host must choose a voltage for

operation and reissue CMD1 with this condition, sending incompatible cards into the Inactive State.

Rev.0.02, Sep.15.2004, page 34 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Data Transfer Mode

When in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all

CSD registers is not known, the f_PPclock rate is equal to the slow f_ODclock rate. SEND_CSD (CMD9)

allows the host to get the Card Specific Data (CSD register), e.g. ECC type, block length, card storage

capacity, maximum clock rate etc.

card-identification mode

CMD3

CMD15

CMD0

Sending-data state

(data)

from all states in

data-transfer mode

CMD13

CMD12,

CMD11, 17, 18, 30

''operation

complete''

no state transition

in data-transfer mode

CMD7

Stand-by state

(stby)

Transfer state

(tran)

CMD16, 23, 35, 36

CMD9, 10

CMD20, 24, 25, 26, 27, 42

''operation

complete''

''operation

complete''

Receive-data state

(rcv)

CMD24, 25

CMD28, 29, 38

CMD7

CMD12 or

Disconnect state

(dis)

Programming state

(prg)

''transfer end''

CMD7

MultiMediaCard State Diagram (Data Transfer Mode)

The command SELECT_DESELECT_CARD (CMD7) is used to select one card and place it in the

Transfer State. If a previously selected card is in the Transfer State its connection with the host is released

and it will move back to the Stand-by State. Only one card can be, at any time, in the Transfer State. A

selected card is responding the CMD7, the deselected one does not respond to this command. When

CMD7 is sent including the reserved relative card address 0x0000, all cards transfer back to Stand-by State.

This command is used to identify new cards without resetting other already acquired cards. Cards to which

an RCA has already been assigned, do not respond to the identification command flow in this state. All the

data communication in the Data Transfer Mode is consequently a point-to point communication between

the host and the selected card (using addressed commands). All addressed commands are acknowledged

by a response on the CMD line. All read commands (data is sent from the card via data lines) can be

interrupted at any time, by a stop command. The data transfer will terminate and the card will stop or start

working on the next command. The DAT bus line signal level is high when no data is transmitted. A

transmitted data block consists of a start bit (LOW), followed by a continuous data stream. The data

stream contains the net payload data (and error correction bits if an off-card ECC is used). The data stream

Rev.0.02, Sep.15.2004, page 35 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

ends with an end bit (HIGH). The data transmission is synchronous to the clock signal. The payload for

block-oriented data transfer is preserved by a 16-bit CRC check sum (refer to Chapter “Cyclic Redundancy

Check (CRC)”).

•

Stream read

There is a stream oriented data transfer controlled by READ_DAT_UNTIL_STOP (CMD11). This

command instructs the card to send its payload, starting at a specified address, until the host sends a

STOP_TRANSMISSION command (CMD12). The stop command has an execution delay due to the serial

command transmission. The data transfer stops after the end bit of the stop command. If the end of the

memory range is reached while sending data and no stop command has been sent yet by the host, the

contents of the further transferred payload is undefined. The maximum clock frequency for stream read

operation is given by the following formula:

max. speed = min (TRAN_SPEED, (8 * 2^READ_BL_LEN− NSAC) / TAAC),

= min (20, (8 * 2⁹) − 100 [cycles]) / 1000 [µs]) [MHz]

= min (20, 3.996) 3.996 [MHz]

these parameters being defined in Chapter “Registers”. If the host attempts to use a higher frequency, the

card may not be able to sustain data transfer. If this happens, the card will set the UNDERRUN error bit in

the status register, abort the transmission and wait in the data state for a stop command.

•

Block read

The basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BLK_LEN).

READ_BLK_PARTIAL is set, thus smaller blocks whose starting and ending address are wholly contained

within one physical block (as defined by READ_BLK_LEN) may also be transmitted. A 16-bit CRC is

appended to the end of each block ensuring data transfer integrity. READ_SINGLE_BLOCK (CMD17)

starts a block read and after a complete transfer the card goes back to Transfer State.

READ_MULTIPLE_BLOCK (CMD18) starts a transfer of several consecutive blocks. Two types of

multiple block read transactions are defined (the host can use either one at any time):

•

Open-ended Multiple block read

The number of blocks for the read multiple block operation is not defined. The card will

continuously transfer data blocks until a stop transmission command is received.

•

Multiple block read with pre-defined block count

The card will transfer the requested number of data blocks, terminate the transaction and return to

transfer state. Stop command is not required at the end of this type of multiple block read, unless

terminated with an error. In order to start a multiple block read with pre-defined block count, the

host must use the SET_BLOCK_COUNT command (CMD23) immediately preceding the

READ_MULTIPLE_BLOCK (CMD18) command. Otherwise the card will start an open-ended

multiple block read which can be stopped using the STOP_TRANSMISSION command.

The host can abort reading at any time, within a multiple block operation, regardless of the its type.

Transaction abort is done by sending the stop transmission command.

Rev.0.02, Sep.15.2004, page 36 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

If the card detects an error (e.g. out of range, address misalignment, internal error, etc.) during a multiple

block read operation (both types) it will stop data transmission and remain in the Data State. The host must

than abort the operation by sending the stop transmission command. The read error is reported in the

response to the stop transmission command.

If the host sends a stop transmission command after the card transmits the last block of a multiple block

operation with a pre-defined number of blocks, it will be responded to as an illegal command, since the

card is no longer in data state.

If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not

allowed, the card shall detect a block misalignment error condition at the beginning of the first misaligned

block (ADDRESS_ERROR error bit will be set in the status register).

•

Stream write

Stream write (CMD20) starts the data transfer from the host to the card beginning from the starting address

until the host issues a stop command. If partial blocks are allowed (if CSD parameter

WRITE_BL_PARTIAL is set) the data stream can start and stop at any address within the card address

space, otherwise it shall start and stop only at block boundaries. Since the amount of data to be transferred

is not determined in advance, CRC can not be used. If the end of the memory range is reached while

sending data and no stop command has been sent by the host, all further transferred data is discarded. The

maximum clock frequency for stream write operation is given by the following formula:

max. speed = min (TRAN_SPEED, (8 * 2^WRITE_BL_LEN− NSAC) / (TAAC * R2W_FACTOR))

= min (20, (8 * 2⁹− 100 [cycles]) / 1000 [µs] * 4)[MHz] = min (20, 0.999) = 0.999 [MHz]

these parameters being defined in Chapter “Registers”. If the host attempts to use a higher frequency, the

card may not be able to process the data and will stop programming, set the OVERRUN error bit in the

status register, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop

command. The write operation shall also be aborted if the host tries to write over a write-protected area.

In this case, however, the card shall set the WP_VIOLATION bit.

•

Block write

Block write (CMD24 − 27) means that one or more blocks of data are transferred from the host to the card

with a 16-bit CRC appended to the end of each block by the host. A card supporting block write must

always be able to accept a block of data defined by WRITE_BLK_LEN. If the CRC fails, the card will

indicate the failure on the DAT line; the transferred data will be discarded and not written and all further

transmitted blocks (in multiple block write mode) will be ignored.

WRITE_MULTIPLE_BLOCK (CMD25) starts a transfer of several consecutive blocks. Two types of

multiple block write transactions, identical to the multiple block read, are defined (the host can use either

one at any time):

•

Open-ended Multiple block write

The number of blocks for the write multiple block operation is not defined. The card will

continuously accept and program data blocks until a stop transmission command is received.

Rev.0.02, Sep.15.2004, page 37 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Multiple block write with pre-defined block count

•

The card will transfer the requested number of data blocks, terminate the transaction and return to

transfer state. Stop command is not required at the end of this type of multiple block write, unless

terminated with an error. In order to start a multiple block write with pre-defined block count, the

host must use the SET_BLOCK_COUNT command (CMD23) immediately preceding the

WRITE_MULTIPLE_BLOCK (CMD25) command. Otherwise the card will start an open-ended

multiple block write which can be stopped using the STOP_TRANSMISSION command.

The host can abort writing at any time, within a multiple block operation, regardless of the its type.

Transaction abort is done by sending the stop transmission command. If a multiple block write with

predefined block count is aborted, the data in the remaining blocks is not defined.

If the card detects an error (e.g. write protect violation, out of range, address misalignment, internal error,

etc.) during a multiple block write operation (both types) it will ignore any further incoming data blocks

and remain in the Receive State. The host must than abort the operation by sending the stop transmission

command. The write error is reported in the response to the stop transmission command.

If the host sends a stop transmission command after the card received the last block of a multiple block

write with a pre-defined number of blocks, it will be responded to as an illegal command, since the card is

no longer in rcv state.

If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not

allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card will detect the block misalignment

error and abort programming before the beginning of the first misaligned block. The card will set the

ADDRESS_ERROR error bit in the status register, and wait (in the Receive-data-State) for a stop

command while ignoring all further data transfer. The write operation will also be aborted if the host tries

to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit.

Programming of the CID and CSD register does not require a previous block length setting. The

transferred data is also CRC protected.

•

Erase

Identification of these erase groups is accomplished with the TAG_ERASE_GROUP commands. A first

command with the starting address is followed by a second command with the final address, and all erase

groups within this range will be selected for erase. The host must adhere to the following command

sequence; TAG_ERASE_GROUP_START, TAG_ERASE_GROUP_END and ERASE. The following

exception conditions are detected by the card: An erase or tag command is received out of sequence. The

card will set the ERASE_SEQUENCE error bit in the status register and reset the whole sequence. An out

of sequence command (except SEND_STATUS) is received. The card will set the ERASE_RESET status

bit in the status register, reset the erase sequence and execute the last command. If the erase range includes

write protected erase groups, they will be left intact and only the non-protected erase groups will be erased.

The WP_ERASE_SKIP status bit in the status register will be set. The address field in the tag commands

is an erase group. The card will ignore all LSB’s below the group size. As described above for block

write, the card will indicate that an erase is in progress by holding DAT low. The actual erase time may be

quite long, and the host may choose to deselect the card using CMD7.

Rev.0.02, Sep.15.2004, page 38 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Write protect management

•

Card data may be protected against either erase or write. The entire card may be permanently write

protected by the manufacturer or content provider by setting the permanent or temporary write protect bits

in the CSD. Portions of the data may be protected (in units of WP_GRP_SIZE sectors as specified in the

CSD), and the write protection may be changed by the application. The SET_WRITE_PROT command

sets the write protection of the addressed write-protect group, and the CLR_WRITE_PROT command

clears the write protection of the addressed write-protect group. The SEND_WRITE_PROT command is

similar to a single block read command. The card shall send a data block containing 32 write protection

bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits. The

address field in the write protect commands is a group address in byte units. The card will ignore all LSB’s

below the group size.

•

Card lock/unlock operation

The password protection feature enables the host to lock a card while providing a password, which later

will be used for unlocking the card. The password and its size are kept in a 128-bit PWD and 8-bit

PWD_LEN registers, respectively. These registers are non-volatile so that a power cycle will not erase

them. Locked cards respond to (and execute) all commands in the "basic" command class (class 0) and

“lock card” command class. Thus the host is allowed to reset, initialize, select, query for status, etc., but

not to access data on the card. If the password was previously set (the value of PWD_LEN is not‘0’) will

be locked automatically after power on. Similar to the existing CSD and CID register write commands the

lock/unlock command is available in "transfer state" only. This means that it does not include an address

argument and the card has to be selected before using it. The card lock/unlock command has the structure

and bus transaction type of a regular single block write command. The transferred data block includes all

the required information of the command (password setting mode, PWD itself, card lock/unlock etc.). The

following table describes the structure of the command data block.

Lock Card Data Structure

Byte#

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0

Reserved

ERASE LOCK_

CLR_

SET_

PWD

UNLOCK PWD

1

PWD_LEN

2

Password data

...

PWD_LEN + 1

Rev.0.02, Sep.15.2004, page 39 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

•

ERASE: 1 Defines Forced Erase Operation (all other bits shall be ‘0’) and only the cmd byte is

sent.

LOCK/UNLOCK: 1 = Locks the card. 0 = Unlock the card (note that it is valid to set this bit

together with SET_PWD but it is not allowed to set it together with CLR_PWD).

•

CLR_PWD: 1 = Clears PWD.

SET_PWD: 1 = Set new password to PWD.

PWD_LEN: Defines the following password length (in bytes).

PWD: The password (new or currently used depending on the command).

The data block size shall be defined by the host before it sends the card lock/unlock command. This will

allow different password sizes. The following paragraphs define the various lock/unlock command

sequences:

•

Setting the Password

Select a card (CMD7), if not previously selected already.

Define the block length (CMD16), given by the 8bit card lock/unlock mode, the 8-bit

password size (in bytes), and the number of bytes of the new password. In case that a password

replacement is done, then the block size shall consider that both passwords, the old and the new

one, are sent with the command.

Send Card Lock/Unlock command with the appropriate data block size on the data line

including 16-bit CRC. The data block shall indicate the mode (SET_PWD), the length

(PWD_LEN) and the password itself. In case that a password replacement is done, then the

length value (PWD_LEN) shall include both passwords, the old and the new one, and the PWD

field shall include the old password (currently used) followed by the new password.

In case that the sent old password is not correct (not equal in size and content) then

LOCK_UNLOCK_FAILED error bit will be set in the status register and the old password does

not change. In case that PWD matches the sent old password then the given new password and

its size will be saved in the PWD and PWD_LEN fields, respectively.

Note that the password length register (PWD_LEN) indicates if a password is currently set. When it equals

‘0’ there is no password set. If the value of PWD_LEN is not equal to zero the card will lock itself after

power up. It is possible to lock the card immediately in the current power session by set-ting the

LOCK/UNLOCK bit (while setting the password) or sending additional command for card lock.

•

Reset the Password:

Select a card (CMD7), if not previously selected already.

Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit

password size (in bytes), and the number of bytes of the currently used password.

Send the card lock/unlock command with the appropriate data block size on the data line

including 16-bit CRC. The data block shall indicate the mode CLR_PWD, the length

(PWD_LEN) and the password (PWD) itself (LOCK/UNLOCK bit is don’t care). If the PWD

and PWD_LEN content match the sent password and its size, then the content of the PWD

register is cleared and PWD_LEN is set to 0. If the password is not correct then the

LOCK_UNLOCK_FAILED error bit will be set in the status register.

Rev.0.02, Sep.15.2004, page 40 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

•

Locking a card:

Select a card (CMD7), if not previously selected already.

Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit

password size (in bytes), and the number of bytes of the currently used password.

Send the card lock/unlock command with the appropriate data block size on the data line

including 16-bit CRC. The data block shall indicate the mode LOCK, the length (PWD_LEN)

and the password (PWD) itself.

If the PWD content equals to the sent password then the card will be locked and the card-locked status bit

will be set in the status register. If the password is not correct then LOCK_UNLOCK_FAILED error bit

will be set in the status register. Note that it is possible to set the password and to lock the card in the same

sequence. In such case the host shall perform all the required steps for setting the password (as described

above) including the bit LOCK set while the new password command is sent. If the password was

previously set (PWD_LEN is not ‘0’), then the card will be locked automatically after power on reset. An

attempt to lock a locked card or to lock a card that does not have a password will fail and the

LOCK_UNLOCK_FAILED error bit will be set in the status register.

•

Unlocking the card:

Select a card (CMD7), if not previously selected already.

Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit

password size (in bytes), and the number of bytes of the currently used password.

Send the card lock/unlock command with the appropriate data block size on the data line

including 16-bit CRC. The data block shall indicate the mode UNLOCK, the length

(PWD_LEN) and the password (PWD) itself.

If the PWD content equals to the sent password then the card will be unlocked and the card-locked status

bit will be cleared in the status register. If the password is not correct then the LOCK_UNLOCK_FAILED

error bit will be set in the status register. Note that the unlocking is done only for the current power

session. As long as the PWD is not cleared the card will be locked automatically on the next power up.

The only way to unlock the card is by clearing the password. An attempt to unlock an unlocked card will

fail and LOCK_UNLOCK_FAILED error bit will be set in the status register.

•

Forcing Erase:

In case that the user forgot the password (the PWD content) it is possible to erase all the card data content

along with the PWD content. This operation is called Forced Erase.

Select a card (CMD7), if not previously selected already.

Define the block length (CMD16) to 1 byte (8bit card lock/unlock command). Send the card

lock/unlock command with the appropriate data block of one byte on the data line including 16-

bit CRC. The data block shall indicate the mode ERASE (the ERASE bit shall be the only bit

set).

If the ERASE bit is not the only bit in the data field then the LOCK_UNLOCK_FAILED error bit will be

set in the status register and the erase request is rejected. If the command was accepted then ALL THE

CARD CONTENT WILL BE ERASED including the PWD and PWD_LEN register content and the

locked card will get unlocked. An attempt to force erase on an unlocked card will fail and

LOCK_UNLOCK_FAILED error bit will be set in the status register.

Rev.0.02, Sep.15.2004, page 41 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

State transition summary

•

Table “Card State Transition Table” defines the card state transitions as a function of received command.

Card State Transition Table

Current state

Command

idle

ready ident stby tran

data rcv

prg

dis

ina

1

CRC fail

*

Commands out of the

supported class(es)

class0 CMD0

idle

CMD1, card V_CC

range compatible

ready

CMD1, card is

busy

idle

ina

CMD1, card V_CC

range not

compatible

CMD2, card wins

bus

ident

CMD2, card loses

bus

ready

CMD3

CMD4

stby

tran

CMD7, card is

addressed

prg

CMD7, card is not

addressed

stby

dis

CMD9

CMD10

stby

CMD12

tran

data

ina

prg

rcv

ina

CMD13

stby

ina

tran

ina

prg

ina

dis

ina

CMD15

class1 CMD11

class2 CMD16

CMD17

data

tran

data

tran

rcv

CMD18

CMD23

class3 CMD20

Rev.0.02, Sep.15.2004, page 42 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Current state

Command

class4 CMD16

CMD23

idle

ready ident stby tran

data rcv

prg

dis

ina

see class 2

rcv

CMD24

rcv

CMD25

rcv

CMD26

rcv

CMD27

rcv

class5 CMD35

CMD36

tran

prg

CMD38

class6 CMD28

CMD29

prg

CMD30

data

rcv

class7 CMD42

Notes: 1. “ ” means command is ignored, no state change and no response.

Rev.0.02, Sep.15.2004, page 43 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Responses

All responses are sent via command line (CMD), all data starts with the MSB.

Format R1 (response command): response length 48 bits.

0

bit5...bit0 bit31...bit0 bit6...bit0

command status CRC

1

start bit card

end bit

The contents of the status field are described in Chapter “Status”

Format R1b (response command with busy signal):

R1b is identical to R1 with an optional busy signal transmitted on the data line. The card may become

busy after receiving these commands based on its state prior to the command reception.

Format R2 (CID, CSD register): response length 136 bits.

Note: Bit 127 down to bit 1 of CID and CSD are transferred, the reserved bit [0] is replaced by the end bit.

0

bit5...bit0 bit127...bit1

1

start bit card

reserved CID or CSD register

including internal CRC

end bit

CID register is sent as a response to commands CMD2 and CMD10.

CSD register is sent as a response to the CMD9.

Format R3 (OCR): response length 48 bits.

0

bit5...bit0 bit31...bit0 bit6...bit0

reserved OCR field reserved

1

start bit card

end bit

The OCR is sent as a response to the CMD1 to signalize the supported voltage range. These Renesas

MultiMediaCards support the range from 2.7 V to 3.6 V. Respectively the value of all bits of the OCR

field of these Renesas MultiMediaCards is set to 0x80FF8000. So the R3 frame contains the value

0x3F80FF8000FF if the card is ready and 0x3F00FF8000FF if the card is busy.

Rev.0.02, Sep.15.2004, page 44 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Status

The response format R1 contains a 32-bit field with the name card status. This field is intended to transmit

status information which is stored in a local status register of each card to the host. The following table

defines the status register structure. The Type and Clear-Condition fields in the table are coded as follows:

•

Type:

•

E: Error bit.

S: Status bit.

R: Detected and set for the actual command response.

X: Detected and set during command execution. The host must poll the card by sending status

command in order to read these bits.

•

Clear Condition:

•

A: According to the card state.

B: Always related to the previous command. Reception of a valid command will clear it (with a

delay of one command).

•

C: Clear by read.

Rev.0.02, Sep.15.2004, page 45 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Status

Bits Identifier

Type Value

E R ‘0’= no error

‘1’= error

Description

Clear condition

31

OUT_OF_RANGE

The commands argument was out C

of allowed range for this card.

30

ADDRESS_ERROR E R X ‘0’= no error

‘1’= error

A misaligned address, which did

not match the block length was

used in the command.

C

29

BLOCK_LEN_ERRO E R

R

‘0’= no error

‘1’= error

The transferred block length is not C

allowed for this card or the

number of transferred bytes does

not match the block length.

28

27

26

25

ERASE_SEQ_ERR E R

OR

‘0’= no error

‘1’= error

An error in the sequence of erase C

commands occurred.

ERASE_PARAM

E X

‘0’= no error

‘1’= error

An invalid selection, groups, for

erase.

C

WP_VIOLATION

E R X ‘0’= not protected The command tried to write a

C

‘1’= protected

write protected block.

CARD_IS_LOCKED S X

‘0’= card

unlocked

When set, signals that the card is A

locked by the host.

‘1’= card locked

24

LOCK_UNLOCK_

FAILED

E R X ‘0’= no error

‘1’= error

Set when a sequence or

password error has been

C

detected in lock/unlock card

command or it there was an

attempt to access a locked card.

23

22

21

20

19

18

17

COM_CRC_ERROR E R

‘0’= no error

‘1’= error

The CRC check of the previous

command failed.

B

C

ILLEGAL_COMMAN E R

D

‘0’= no error

‘1’= error

Command not legal for the

current state

CARD_ECC_FAILE E X

D

‘0’= success

‘1’= failure

Card internal ECC was applied

but the correction of data is failed.

CC_ERROR

E R X ‘0’= no error

‘1’= error

Internal card controller error

ERROR

E R X ‘0’= no error

‘1’= error

A general or an unknown error

occurred during the operation.

UNDERRUN

OVERRUN

E X

‘0’= no error

‘1’= error

The card could not sustain data

transfer in stream read mode.

E X

‘0’= no error

‘1’= error

The card could not sustain data

programming in stream write

mode.

Rev.0.02, Sep.15.2004, page 46 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Bits Identifier

Type Value

Description

Clear condition

16

CID_OVERWRITE/ E R X ‘0’= no error

Can be either one of the following C

errors:

CSD_OVERWRITE

‘1’= error

•

The CID register is already

written and can not be

overwritten.

The read only section of the

CSD does not match the card

content.

An attempt to reverse the

copy (set as original) or

permanent WP (unprotected)

bits was done.

15

14

13

WP_ERASE_SKIP S X

‘0’= not protected Only partial address space was

C

‘1’= protected

erased due to existing WP blocks.

CARD_ECC_

DISABLED

S X

S R

‘0’= enabled

‘1’= disabled

The command has been executed A

without using the internal ECC.

ERASE_RESET

‘0’= cleared

‘1’= set

An erase sequence was cleared

before executing because an out

of erase sequence command was

received.

C

12:9 CURRENT_STATE S X

0 = idle

Current state of the card.

B

1 = ready

2 = ident

3 = stby

4 = tran

5 = data

6 = rcv

7 = prg

8 = dis

9-15 = reserved

8

BUFFER_EMPTY

S X

S R

‘0’= not empty

‘1’= empty

Corresponds to buffer empty

signaling on the bus.

A

7:6

5

Reserved

Permanently 0

APP_CMD

‘0’= disabled

‘1’= enabled

The card will expect APP_CMD or C

indication that the command has

been interpreted as APP_CMD.

4

Reserved

Permanently 0

3:2

1:0

Reserved for application specific commands

Reserved for manufacturer test mode

Rev.0.02, Sep.15.2004, page 47 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Command Response Timings

All timing diagrams use the following schematics and abbreviations:

S: Start bit (= 0)

T: Transmitter bit (Host = 1, Card = 0)

P: One-cycle pull-up (= 1)

E: End bit (= 1)

Z: High impedance state (-> = 1)

D: Data bits

*: Repeater

CRC: Cyclic redundancy check bits (7 bits for command or response, 16 bits for block data)

The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card

respectively host output driver, while the Z-bit is driven to (respectively kept) HIGH by the pull-up

resistors R_CMDrespectively R_DAT. Actively driven P-bits are less sensitive to noise superposition. For the

timing of these Renesas MultiMediaCards, the following values are defined:

Timing Values

Value [clock cycles]

Symbol

Min

Max

Description

N_CR

2

64

Number of cycles between command and

response

N_ID

5

Number of cycles between card identification

or card operation conditions command and the

corresponding response

N_AC

N_RC

N_CC

2*¹

8

TAAC + NSAC*²Number of cycles between a command and the

start of a related data block

Number of cycles between the last response

and a new command

8

Number of cycles between two commands, if

no response will be sent after the first

command (e.g. broadcast)

N_WR

N_ST

2

Number of cycles between a write command

and the start of a related data block

2

Number of cycles between stop command and

valid read / write data end

Notes: 1. Refer to Chapter “Electrical Characteristics” for more details about the access time.

2. Refer to Chapter “Read, Write and Erase Time-out Conditions”.

Rev.0.02, Sep.15.2004, page 48 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

The host command and the card response are clocked out with the rising edge of the host clock. The delay

between host command and card response is N_CRclock cycles. The following timing diagram is relevant

for host command CMD3:

Host command

N_CRcycles

Response

content CRC E Z Z Z

CMD

S T

content

CRC E Z * * * * * * Z S T

Host active

Card active

Command Response Timing (Identification Mode)

There is just one Z bit period followed by P bits pushed up by the responding card. The following timing

diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:

Host command

N_CRcycles

Response

content CRC E Z Z Z

CMD

S T

content

CRC E Z Z P * * * P S T

Host active

Card active

Command Response Timing (Data Transfer Mode)

•

Card identification and card operation conditions timing

The card identification (CMD2) and card operation condition (CMD1) timing are processed in the open-

drain mode. The card response to the host command starts after exactly N_IDclock cycles.

Host command

N_IDcycles

* * *

CID or OCR

content

CMD

S T

content

CRC E Z

Z S T

Z Z Z

Host active

Card active

Identification Timing (Card Identification Mode)

•

Last card response - next host command timing

After receiving the last card response, the host can start the next command transmission after at least N_RC

clock cycles. This timing is relevant for any host command.

Response

content

N_RCcycles

Host command

CMD

S T

CRC E Z * * * * * * Z S T

content

CRC E

Card active

Host active

Timing Response End to Next CMD Start (Data Transfer Mode)

Rev.0.02, Sep.15.2004, page 49 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Last host command - next host command timing diagram

•

After the last command, which does not force a response, has been sent, the host can continue sending the

next command after at least N_CCclock periods.

Host command

N_CCcycles

Host command

CMD

S T

content

CRC E Z * * * * * * Z S T

content

CRC E

Host active

Timing CMD_nEnd to CMD_n+1Start (All Modes)

In the case the CMD_ncommand was a last identification command (no more response sent by a card), then

the next CMD_n+1command is allowed to follow after at least N_CC+ 136 (the length of the R2 response)

clock periods.

•

Data access timing

Data transmission starts with the access time delay t_AC(which corresponds to N_AC), beginning from the end

bit of the data address command. The data transfer stops automatically in case of a data block transfer or

by a transfer stop command.

Host command

N_CRcycles

Response

content CRC E

CMD

DAT

S T

content

CRC E Z Z P * * * P S T

Host active

Card active

N_ACcycles

Read data

Z Z Z * * * * Z Z Z Z Z Z P * * * * * * * * * * * P S D D D * * *

Card active

Data Read Timing (Data Transfer Mode)

•

Data transfer stop command timing

The card data transmission can be stopped using the stop command. The data transmission stops

immediately with the end bit of the stop command.

Host command

N_CRcycles

Response

content CRC E

CMD

DAT

S T

content

CRC E Z Z P * * * P S T

Host active

Card active

Z * * * * * * * * * * * * * * * * * * * * * *

N_ST

D D D * * * * * * * * D D D E

Card active

Z

Timing of Stop Command (CMD12, Data Transfer Mode)

Rev.0.02, Sep.15.2004, page 50 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Stream read

•

The data transfer starts N_ACclock cycles after the end bit of the host command. The bus transaction is

identical to that of a read block command (refer to Figure “Data Read Timing”). As the data transfer is not

block-oriented, the data stream does not include the CRC checksum. Consequently the host can not check

for data validity. The data stream is terminated by a stop command. The corresponding bus transaction is

identical to the stop command for the multiple read block (refer to Figure “Timing of Stop Command”).

•

Single or multiple block write

The host selects one card for data write operation by CMD7. The host sets the valid block length for

block-oriented data transfer by CMD16 (The write-block-length of the Renesas MultiMediaCard is

permanently assigned to the value 512 bytes). The host transfers the data with CMD24. The address of the

data block is determined by the argument of this command. This command is responded by the card on the

CMD line as usual. The data transfer from the host starts N_WRclock cycles after the card response was

received. The write data have CRC check bits to allow the card to check the transferred data for

transmission errors. The card sends the CRC check information as a CRC status to the host (on the data

line). The CRC status contains the information if the write data transfer was non-erroneous (the CRC

check did not fail) or not. In the case of transmission error the card sends a negative CRC status (“101”

bin) which forces the host to retransmit command and the data. In the case of non-erroneous transmission

the card sends a positive CRC status (“010” bin) and starts the data programming procedure.

N_CR

Host command

Card response

CMD

S T

content

CRC E

S T

content

CRC E

N_WR

Host active

Card active

Write data

content

Z Z Z * * * * Z Z Z Z Z Z

Z Z * * * * Z Z Z Z Z P S

Z

DAT

Host active

CMD

Write data

content

Host active

CRC status

Card busy

DAT

CRC E Z Z S status E S busy = 'L' E Z

Card active

L ... pull down to LOW bit

Timing of The Block Write Command

If the card does not have any more free data receive buffer, the card indicates it by pulling down the data

line to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the

defined data transfer block length becomes free. This signaling does not give any information about the

data write status. This information has to be polled by CMD13 polling command (SEND_STATUS).

Rev.0.02, Sep.15.2004, page 51 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Stream write

•

The data transfer starts N_WRclock cycles after the card response to the sequential write command was

received. The bus transaction is identical to that of a write block command (see Figure “Timing of The

Block Write Command”). As the data transfer is not block-oriented, the data stream does not include the

CRC checksum. Consequently the host can not receive any CRC status information from the card. The

data stream is terminated by a stop command. The bus transaction is identical to the write block option

when a data block is interrupted by the stop command (see Figure “Stop Transmission During Data

Transfer From The Host”).

Host command

content

N_CRcycles

Card response

content CRC E

Host command

S T content

CMD

DAT

S T

CRC E Z Z P * * * P S T

N_ST

Card is programming

D D D D D D D D D D

Valid write data

E Z Z S L * * * * * * * * * * * * * * * * * * E Z Z Z Z Z Z Z Z

Stop Transmission During Data Transfer From The Host

•

Erase block timing

The host must first tag the group to erase. The tagged group(s) are erased in parallel by using the CMD35,

CMD36 and CMD38. The card busy signaling is also used for the indication of the card erase procedure

duration. In this case the end of the card busy signaling also does mean that the erase of all tagged groups

has been finished. The host can (also) request the card to send the actual card state using the CMD13.

Card response

content CRC E

N_CR

CMD

DAT

T

content

CRC E

S T

card is erasing

card busy

Host active

Z Z * * * * * * * * * * * Z Z Z S L L * * * * * * * * * * * * * * * * * * * * L E

Card active

Host command

S T

content

CRC E

CMD

DAT

Host active

L

* * * * * L E Z * * * * * * * *

Card active

L ... pull down to LOW bit

Timing of Erase Operation

Rev.0.02, Sep.15.2004, page 52 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Reset

GO_IDLE_STATE (CMD0) is the software reset command, which sets the MultiMediaCard into the Idle

State independently of the current state. In the Inactive State the MultiMediaCard is not affected by this

command. After power-on the MultiMediaCard is always in the Idle State. After power-on or command

GO_IDLE_STATE (CMD0) all output bus drivers of the MultiMediaCard is in a high-impedance state and

the card will be initialized with a default relative card address (0x0001). The host runs the bus at the

identification clock rate f_ODgenerated by a push-pull driver stage (refer to also Chapter “Power on” for

more details).

CMD0 is valid in all states with the exception of the Inactive State. While in Inactive state the card will not

accept CMD0 unless it is used to switch the card into SPI mode.

Rev.0.02, Sep.15.2004, page 53 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

SPI Communication

The SPI mode consists of a secondary communication protocol. This mode is a subset of the

MultiMediaCard protocol, designed to communicate with a SPI channel, commonly found in Motorola’s

(and lately a few other vendors’) microcontrollers. The interface is selected during the first reset command

after power up (CMD0) and cannot be changed once the part is powered on. The SPI standard defines the

physical link only, and not the complete data transfer protocol. The MultiMediaCard SPI implementation

uses a subset of the MultiMediaCard protocol and command set. It is intended to be used by systems

which require a small number of card (typically one) and have lower data transfer rates (compared to

MultiMediaCard protocol based systems). From the application point of view, the advantage of the SPI

mode is the capability of using an off-the-shelf host, hence reducing the design-in effort to minimum. The

disadvantage is the loss of performance of the SPI system versus MultiMediaCard (lower data transfer rate,

fewer cards, hardware CS per card etc.). While the MultiMediaCard channel is based on command and

data bitstreams which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte

oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal (i.e. the

length is a multiple of 8 clock cycles). Similar to the MultiMediaCard protocol, the SPI messages consist

of command, response and data-block tokens (refer to Chapter “Commands” and Chapter “Responses” for

a detailed description). All communication between host and cards is controlled by the host (master). The

host starts every bus transaction by asserting the CS signal low. The response behavior in the SPI mode

differs from the MultiMediaCard mode in the following three aspects:

•

The selected card always responds to the command.

An additional (8 bit) response structure is used.

When the card encounters a data retrieval problem, it will respond with an error response (which

replaces the expected data block) rather than by a time-out as in the MultiMediaCard mode.

Single block and multiple read and write operations are supported in SPI mode. In addition to the

command response, every data block sent to the card during write operations will be responded with a

special data response token. A data block may be as big as one card sector and as small as a single byte.

Partial block read/write operations are enabled by card options specified in the CSD register.

Mode Selection

The MultiMediaCard wakes up in the MultiMediaCard mode. It will enter SPI mode if the reset command

(CMD0) is received during the CS signal is asserted (negative). Selecting SPI mode is not restricted to Idle

state (the state the card enters after power up) only. Every time the card receives CMD0, including while

in Inactive state, CS signal is sampled.

If the card recognizes that the MultiMediaCard mode is required it will not respond to the command and

remain in the MultiMediaCard mode. If SPI mode is required the card will switch to SPI and respond with

the SPI mode R1 response.

The only way to return to the MultiMediaCard mode is by entering the power cycle. In SPI mode the

MultiMediaCard protocol state machine is not observed. All the MultiMediaCard commands supported in

SPI mode are always available.

Rev.0.02, Sep.15.2004, page 54 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Bus Transfer Protection

Every MultiMediaCard token transferred on the bus is protected by CRC bits. In SPI mode, the

MultiMediaCard offers a non-protected mode which enables systems built with reliable data links to

exclude the hardware or firmware required for implementing the CRC generation and verification

functions. In the non-protected mode the CRC bits of the command, response and data tokens are still

required in the tokens. However, they are defined as “don’t care” for the transmitter and ignored by the

receiver. The SPI interface is initialized in the non protected mode. However, the RESET command

(CMD0), which is used to switch the card to SPI mode, is received by the card while in MultiMediaCard

mode and, therefore, must have a valid CRC field.

The host can turn this option on and off using the CRC_ON_OFF command (CMD59).

Data Read Overview

The SPI mode supports single and multiple block read operations (CMD17 and CMD18 in the

MultiMediaCard protocol). The main difference between SPI and MultiMediaCard modes is that the data

and the response are both transmitted to the host on the DataOut signal (refer to Figure 43 and Figure 45).

Therefore the card response to the STOP_COMMAND may cut-short and replace the last data block (refer

to Figure “Read Operation”).

from

host

from

card

data from card

to host

to card

to host

command

Data in

command

Data out

response

data block CRC

Single Block Read Operation

from

host

from

card

data from card

to host

Stop

command

to card

to host

command

Data in

command

Data out

data block CRC data B. response

data block CRC

response

Multiple Block Read Operation

The basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BL_LEN). If

READ_BL_PARTIAL is set, smaller blocks whose starting and ending addresses are entirely contained

within one physical block (as defined by READ_BL_LEN) may also be transmitted. A 16-bit CRC is

appended to the end of each block ensuring data transfer integrity (also refer to chapter “Cyclic

Redundancy Check (CRC)”). CMD17 (READ_SINGLE_BLOCK) initiates a single block read. CMD18

Rev.0.02, Sep.15.2004, page 55 of 89

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

(READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. Two types of multiple

block read transactions are defined (the host can use either one at any time):