HA2-5002-2ZR5254 [RENESAS]
BUFFER AMPLIFIER, MBCY8, GREEN, METAL CAN, 8 PIN;
| 型号： | HA2-5002-2ZR5254 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | BUFFER AMPLIFIER, MBCY8, GREEN, METAL CAN, 8 PIN 放大器 |
| 文件： | 总14页 (文件大小：849K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5002
®
Data Sheet
March 8, 2006
FN2921.11
110MHz, High Slew Rate, High Output
Current Buffer
Features
• Voltage Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.995
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . .3000kΩ
• Low Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . 3Ω
• Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . 1300V/µs
• Very Wide Bandwidth. . . . . . . . . . . . . . . . . . . . . . 110MHz
• High Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . ±200mA
• Pulsed Output Current . . . . . . . . . . . . . . . . . . . . . . 400mA
• Monolithic Construction
The HA-5002 is a monolithic, wideband, high slew rate, high
output current, buffer amplifier.
Utilizing the advantages of the Intersil D.I. technologies, the
HA-5002 current buffer offers 1300V/µs slew rate with
110MHz of bandwidth. The ±200mA output current capability
is enhanced by a 3Ω output impedance.
The monolithic HA-5002 will replace the hybrid LH0002 with
corresponding performance increases. These characteristics
range from the 3000kΩ input impedance to the increased
output voltage swing. Monolithic design technologies have
allowed a more precise buffer to be developed with more than
an order of magnitude smaller gain error.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Line Driver
• Data Acquistion
The HA-5002 will provide many present hybrid users with a
higher degree of reliability and at the same time increase
overall circuit performance.
• 110MHz Buffer
• Radara Cable Driver
• High Power Current Booster
• High Power Current Source
• Sample and Holds
• Video Products
For the military grade product, refer to the HA-5002/883
datasheet.
Ordering Information
TEMP.
PKG.
PART NUMBER
HA2-5002-2
PART MARKING
HA2-5002-2
RANGE (°C)
PACKAGE
8 Pin Metal Can
DWG. #
-55 to 125
0 to 75
T8.C
HA2-5002-5
HA2-5002-5
HA3-5002-5
HA3-5002-5Z
HA4P5002-5
HA4P5002-5Z
50025
8 Pin Metal Can
8 Ld PDIP
T8.C
HA3-5002-5
0 to 75
E8.3
HA3-5002-5Z (Note)
HA4P5002-5
0 to 75
8 Ld PDIP* (Pb-free)
20 Ld PLCC
E8.3
0 to 75
N20.35
N20.35
M8.15
M8.15
M8.15
M8.15
HA4P5002-5Z (Note)
HA9P5002-5
0 to 75
20 Ld PLCC (Pb-free)
8 Ld SOIC
0 to 75
HA9P5002-5Z (Note)
HA9P5002-9
50025Z
0 to 75
8 Ld SOIC (Pb-free)
8 Ld SOIC
50029
-40 to 85
-40 to 85
HA9P5002-9Z (Note)
50029Z
8 Ld SOIC (Pb-free)
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HA-5002
Pinouts
HA-5002 (PDIP, SOIC)
HA-5002 (PLCC)
HA-5002 (METAL CAN)
TOP VIEW
TOP VIEW
TOP VIEW
IN
8
1
8
7
6
5
V +
OUT
1
3
2
1
20 19
V +
1
3
V -
1
7
5
1
2
3
4
V -
2
V +
2
4
5
6
7
8
18 NC
NC
NC
IN
NC
2
6
V +
V -
2
2
V -
2
17 V +
2
V -
1
NC
NC
NC
16
15
NC
NC
NC
NC
4
OUT
14 NC
NOTE: Case Voltage = Floating
9
10 11 12 13
FN2921.11
March 8, 2006
2
HA-5002
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V + to V -
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . ±200mA
Thermal Resistance (Typical, Note 2)
θ
(°C/W)
θ
(°C/W)
JC
JA
1
1
PDIP Package*. . . . . . . . . . . . . . . . . . .
Metal Can Package . . . . . . . . . . . . . . .
PLCC Package. . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
92
155
74
N/A
67
N/A
N/A
Output Current (50ms On, 1s Off) . . . . . . . . . . . . . . . . . . . . ±400mA
157
Max Junction Temperature (Hermetic Packages, Note 1) . . . . . . 175°C
Max Junction Temperature (Plastic Packages, Note 1) . . . . . . . . 150°C
Max Storage Temperature Range . . . . . . . . . . . . . . -65°C to 150°C
Max Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . 300°C
(PLCC and SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range
HA-5002-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C
HA-5002-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
HA-5002-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175°C for the
can packages, and below 150°C for the plastic packages.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±12V to ±15V, R = 50Ω, R = 1kΩ, C = 10pF, Unless Otherwise Specified
SUPPLY
S
L
L
HA-5002-2
TYP
HA-5002-5, -9
TYP
TEST
CONDITIONS
TEMP
(°C)
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
MIN
MAX
MIN
MAX
UNITS
25
Full
Full
25
-
5
10
30
2
20
30
-
-
5
10
30
2
20
30
-
mV
mV
-
-
Average Offset Voltage Drift
Bias Current
-
-
µV/°C
µA
-
-
7
-
-
7
Full
Full
25
3.4
3
10
-
2.4
3
10
-
µA
Input Resistance
1.5
-
1.5
-
MΩ
Input Noise Voltage
TRANSFER CHARACTERISTICS
Voltage Gain
10Hz-1MHz
18
-
18
-
µV
P-P
R
= 50Ω
25
25
-
0.900
0.971
0.995
-
-
-
-
-
-
-
-
0.900
0.971
0.995
-
-
-
-
-
-
-
V/V
L
(V
= ±10V)
OUT
R
R
R
= 100Ω
= 1kΩ
= 1kΩ
-
-
V/V
V/V
L
25
-
-
L
Full
25
0.980
0.980
V/V
L
-3dB Bandwidth
V
= 1V
-
-
110
40
-
-
110
40
MHz
A/mA
IN
P-P
AC Current Gain
25
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
R
R
= 100Ω
25
Full
Full
25
±10
±10.7
±13.5
±10.5
220
-
-
±10
±11.2
±13.9
±10.5
220
-
-
V
V
L
= 1kΩ, V = ±15V
±10
±10
L
S
= 1kΩ, V = ±12V
±10
-
±10
-
V
L
S
Output Current
V
= ±10V, R = 40Ω
-
-
-
-
-
-
-
-
mA
Ω
IN
L
Output Resistance
Harmonic Distortion
TRANSIENT RESPONSE
Full Power Bandwidth (Note 3)
Rise Time
Full
25
3
10
-
3
10
-
V
= 1V
, f = 10kHz
RMS
<0.005
<0.005
%
IN
25
25
25
25
25
25
-
20.7
3.6
2
-
-
-
-
-
-
-
20.7
3.6
2
-
-
-
-
-
-
MHz
ns
-
-
Propagation Delay
Overshoot
-
-
-
-
ns
30
30
%
Slew Rate
1.0
-
1.3
50
1.0
-
1.3
50
V/ns
ns
Settling Time
To 0.1%
FN2921.11
3
March 8, 2006
HA-5002
Electrical Specifications
V
= ±12V to ±15V, R = 50Ω, R = 1kΩ, C = 10pF, Unless Otherwise Specified (Continued)
SUPPLY
S
L
L
HA-5002-2
TYP
HA-5002-5, -9
TYP
TEST
CONDITIONS
TEMP
(°C)
PARAMETER
Differential Gain
MIN
MAX
MIN
MAX
UNITS
%
R
= 500Ω
25
25
-
-
0.06
-
-
-
-
0.06
-
-
L
Differential Phase
R
= 500Ω
0.22
0.22
Degrees
L
POWER REQUIREMENTS
Supply Current
25
-
-
8.3
-
-
10
-
-
-
8.3
-
-
10
-
mA
mA
dB
Full
Full
Power Supply Rejection Ratio
NOTE:
A
= 10V
54
64
54
64
V
Slew Rate
3.
.
--------------------------
FPBW =
; V = 10V
P
2πV
PEAK
Test Circuit and Waveforms
+15V
V +
V +
2
1
R
S
IN
OUT
V -
V -
2
1
R
L
-15V
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE
V
V
IN
IN
V
OUT
V
OUT
R
= 50Ω, R = 100Ω
R = 50Ω, R = 1kΩ
S L
S
L
SMALL SIGNAL WAVEFORMS
SMALL SIGNAL WAVEFORMS
FN2921.11
4
March 8, 2006
HA-5002
Test Circuit and Waveforms (Continued)
V
IN
V
IN
V
V
OUT
OUT
R
= 50Ω, R = 1kΩ
L
R
= 50Ω, R = 100Ω
L
S
S
LARGE SIGNAL WAVEFORMS
LARGE SIGNAL WAVEFORMS
Schematic Diagram
V +
1
R
8
R
R
9
N1
Q
19
V +
2
R
R
6
4
1
Q
20
Q
18
Q
Q
Q
25
26
Q
12
R
10
Q
3
Q
1
Q
9
27
Q
Q
10
R
11
Q
Q
4
7
R
IN
OUT
5
R
N2
Q
21
Q
5
Q
11
Q
2
Q
22
Q
8
Q
15
Q
23
Q
24
V -
2
R
6
Q
17
Q
13
Q
Q
16
14
R
7
R
R
N3
2
R
R
3
12
V -
1
Other considerations are proper power supply bypassing
and keeping the input and output connections as short as
possible which minimizes distributed capacitance and
reduces board space.
Application Information
Layout Considerations
The wide bandwidth of the HA-5002 necessitates that high
frequency circuit layout procedures be followed. Failure to
follow these guidelines can result in marginal performance.
Power Supply Decoupling
For optimal device performance, it is recommended that the
positive and negative power supplies be bypassed with
capacitors to ground. Ceramic capacitors ranging in value
from 0.01 to 0.1µF will minimize high frequency variations in
supply voltage, while low frequency bypassing requires
Probably the most crucial of the RF/video layout rules is the
use of a ground plane. A ground plane provides isolation and
minimizes distributed circuit capacitance and inductance
which will degrade high frequency performance.
FN2921.11
5
March 8, 2006
HA-5002
larger valued capacitors since the impedance of the
capacitor is dependent on frequency.
Capacitive Loading
The HA-5002 will drive large capacitive loads without oscillation
but peak current limits should not be exceeded. Following the
formula I = Cdv/dt implies that the slew rate or the capacitive
load must be controlled to keep peak current below the
maximum or use the current limiting approach as shown. The
HA-5002 can become unstable with small capacitive loads
(50pF) if certain precautions are not taken. Stability is
It is also recommended that the bypass capacitors be
connected close to the HA-5002 (preferably directly to the
supply pins).
Operation at Reduced Supply Levels
The HA-5002 can operate at supply voltage levels as low as
±5V and lower. Output swing is directly affected as well as
slight reductions in slew rate and bandwidth.
enhanced by any one of the following: a source resistance in
series with the input of 50Ω to 1kΩ; increasing capacitive load
Short Circuit Protection
to 150pF or greater; decreasing C
to 20pF or less; adding
LOAD
The output current can be limited by using the following circuit:
an output resistor of 10Ω to 50Ω; or adding feedback
capacitance of 50pF or greater. Adding source resistance
generally yields the best results.
I
= 200mA
V+
V-
V+
OUTMAX
R
= ------------------------- = -------------------------
LIM
(CONTINUOUS)
I
I
OUTMAX
OUTMAX
R
V +
LIM
1
V +
2
OUT
IN
V -
2
V -
1
R
LIM
V-
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
T
– T
A
+ θ
CS SA
JMAX
+ θ
PLCC
P
= --------------------------------------------
θ
DMAX
PDIP
JC
Where: T
Device
= Maximum Junction Temperature of the
JMAX
CAN
T = Ambient
A
θ
θ
θ
= Junction to Case Thermal Resistance
= Case to Heat Sink Thermal Resistance
= Heat Sink to Ambient Thermal Resistance
JC
CS
SA
SOIC
T
– T
A
QUIESCENT POWER DISSIPATION
AT ±15V SUPPLIES
JMAX
θ
Graph is based on:
P
= -------------------------------
DMAX
JA
25
65
85
45
125
105
TEMPERATURE (°C)
FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE
FN2921.11
6
March 8, 2006
HA-5002
Typical Application
+12V
V +
V +
2
1
V
IN
R
S
R
RG -58
M
V
OUT
50Ω
50Ω
V
R
L
50Ω
IN
V -
V -
2
1
-12V
V
OUT
FIGURE 3. COAXIAL CABLE DRIVER - 50Ω SYSTEM
Typical Performance Curves
9
9
V
= ±15V, R = 50Ω
V
= ±15V, R = 50Ω
S
S
S
S
6
3
6
3
GAIN
GAIN
0
0
-3
-3
PHASE
PHASE
-6
0°
-6
0°
-9
-9
45°
90°
45°
90°
-12
-15
-18
-12
-15
-18
135°
180°
135°
180°
1
10
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
FIGURE 4. GAIN/PHASE vs FREQUENCY (R = 1kΩ)
FIGURE 5. GAIN/PHASE vs FREQUENCY (R = 50Ω)
L
L
0.998
0.994
V
= ±15V
V
= ±15V
S
S
0.992
0.990
0.988
0.986
0.984
0.982
0.980
0.978
0.976
0.974
0.997
0.996
0.995
0.994
0.993
0.992
0.991
V
= 0 TO +10V
OUT
V
= -10V TO +10V
OUT
V
= 0 TO -10V
OUT
-60 -40
-20
0
20
40
60
80 100 120
-60 -40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 6. VOLTAGE GAIN vs TEMPERATURE (R = 100Ω)
FIGURE 7. VOLTAGE GAIN vs TEMPERATURE (R = 1kΩ)
L
L
FN2921.11
March 8, 2006
7
HA-5002
Typical Performance Curves (Continued)
7
6
5
4
3
2
1
0
3
V
= ±15V
V
= ±15V
2
1
S
S
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-60
-40
-20
0
20
40
60
80
100 120
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. BIAS CURRENT vs TEMPERATURE
FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE
15
14
13
12
11
10
9
V
= ±15V, R
= 100Ω
LOAD
S
V
= ±15V, I
= 0mA
OUT
S
+V
8
OUT
7
-V
OUT
6
5
4
3
-60
-40
-20
0
20
40
60
80
100 120
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 10. MAXIMUM OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 11. SUPPLY CURRENT vs TEMPERATURE
10
V
= ±15V
S
I
= 0mA
OUT
125°C, 25°C
-55°C
100K
10K
1000
100
10
8
6
4
2
0
Z
IN
Z
OUT
1
0
2
4
6
8
10
12
14
16
18
100K
1M
10M
100M
SUPPLY VOLTAGE (±V)
FREQUENCY (Hz)
FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 13. INPUT/OUTPUT IMPEDANCE vs FREQUENCY
FN2921.11
March 8, 2006
8
HA-5002
Typical Performance Curves (Continued)
80
70
60
50
23
R
= 100Ω
22
21
20
19
18
17
16
15
14
13
12
11
10
9
LOAD
T
= 25°C
A
40
30
T
= 125°C,
A
T
= -55°C
A
20
10
8
0
10K
7
100K
1M
10M
100M
15
12
8
5
SUPPLY VOLTAGE (±V)
FREQUENCY (Hz)
FIGURE 15. PSRR vs FREQUENCY
FIGURE 14. V
OUT
MAXIMUM vs V
SUPPLY
1500
1400
1300
1200
1100
1000
900
150
V
= ±15V
S
T
= 25°C
A
100
50
R
= 100
L
R
= 1K
L
0
-50
-100
-150
R
= 600
L
6
8
10
12
14
16
18
-10
-8
-6
-4
-2
0
2
4
6
8
10
SUPPLY VOLTAGE (±V)
INPUT VOLTAGE (VOLTS)
FIGURE 16. SLEW RATE vs SUPPLY VOLTAGE
FIGURE 17. GAIN ERROR vs INPUT VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V -
1
TRANSISTOR COUNT:
27
PROCESS:
Bipolar Dielectric Isolation
FN2921.11
9
March 8, 2006
HA-5002
Metallization Mask Layout
HA-5002
IN
V -
1
V - (ALT)
1
V + (ALT)
1
V +
2
V -
2
V +
1
OUT
FN2921.11
10
March 8, 2006
HA-5002
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
FN2921.11
11
March 8, 2006
HA-5002
Metal Can Packages (Can)
REFERENCE PLANE
T8.C MIL-STD-1835 MACY1-X8 (A1)
8 LEAD METAL CAN PACKAGE
A
e1
L
INCHES
MILLIMETERS
L2
L1
SYMBOL
MIN
MAX
0.185
0.019
0.021
0.024
0.375
0.335
0.160
MIN
4.19
0.41
0.41
0.41
8.51
7.75
2.79
MAX
4.70
0.48
0.53
0.61
9.40
8.51
4.06
NOTES
ØD2
A
Øb
Øb1
Øb2
ØD
ØD1
ØD2
e
0.165
0.016
0.016
0.016
0.335
0.305
0.110
-
A
A
1
k1
1
Øe
ØD ØD1
2
-
N
1
-
-
Øb1
β
α
C
L
-
Øb
k
F
0.200 BSC
0.100 BSC
5.08 BSC
2.54 BSC
-
BASE AND
Q
e1
F
-
SEATING PLANE
-
0.040
0.034
0.045
0.750
0.050
-
-
1.02
0.86
1.14
19.05
1.27
-
-
BASE METAL
LEAD FINISH
Øb2
k
0.027
0.027
0.500
-
0.69
0.69
12.70
-
-
k1
L
2
Øb1
1
L1
L2
Q
1
SECTION A-A
0.250
0.010
6.35
0.25
1
0.045
1.14
-
NOTES:
o
o
45 BSC
45 BSC
3
α
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
o
o
β
45 BSC
45 BSC
3
4
N
8
8
2. Measured from maximum diameter of the product.
Rev. 0 5/18/94
3. α is the basic spacing from the centerline of the tab to terminal 1
and β is the basic spacing of each lead or lead position (N -1
places) from α, looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
FN2921.11
12
March 8, 2006
HA-5002
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
N20.35 (JEDEC MS-018AA ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
PIN (1) IDENTIFIER
0.025 (0.64)
0.045 (1.14)
0.050 (1.27) TP
INCHES
MILLIMETERS
R
C
L
SYMBOL
MIN
MAX
MIN
4.20
2.29
9.78
8.89
3.59
9.78
8.89
3.59
MAX
4.57
NOTES
A
A1
D
0.165
0.090
0.385
0.350
0.141
0.385
0.350
0.141
0.180
0.120
0.395
0.356
0.169
0.395
0.356
0.169
-
3.04
-
-
D2/E2
D2/E2
10.03
9.04
C
L
D1
D2
E
3
E1 E
4.29
4, 5
-
10.03
9.04
VIEW “A”
E1
E2
N
3
4.29
4, 5
6
0.020 (0.51)
MIN
20
20
A1
D1
D
Rev. 2 11/97
A
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controllingdimension:INCH. Convertedmillimeterdimensionsare
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
FN2921.11
13
March 8, 2006
HA-5002
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2921.11
14
March 8, 2006
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