HA2-5002/883 [INTERSIL]
Monolithic, Wideband, High Slew Rate, High Output Current Buffer; 单片，宽带，高转换率，高输出电流缓冲器
| 型号： | HA2-5002/883 |
| 厂家： | 
Intersil |
| 描述： | Monolithic, Wideband, High Slew Rate, High Output Current Buffer |
| 文件： | 总7页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5002/883
®
Data Sheet
January 5, 2006
FN3705.4
Monolithic, Wideband, High Slew Rate,
High Output Current Buffer
The HA-5002/883 is a monolithic, wideband, high slew rate,
high output current, buffer amplifier.
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Voltage Gain (R = 1kΩ) . . . . . . . . . . . . . . . . . .0.98 (Min)
L
Utilizing the advantages of the Intersil Dielectric Isolation
technologies, the HA-5002/883 current buffer offers
1300V/µs slew rate typically and 1000V/µs minimum with
110MHz of bandwidth. The ±100mA minimum output current
capability is enhanced by a 3Ω output impedance.
0.995 (Typ)
(R = 100Ω) . . . . . . . . . . . . . . . . .0.96 (Min)
L
0.971 (Typ)
• High Input Impedance . . . . . . . . . . . . . . . . . . 1.5MΩ (Min)
3MΩ (Typ)
The monolithic HA-5002/883 will replace the hybrid LH0002
with corresponding performance increases. These
• Low Output Impedance . . . . . . . . . . . . . . . . . . . 5Ω (Max)
3Ω (Typ)
characteristics range from the 3MΩ (typ) input impedance to
the increased output voltage swing. Monolithic design
technologies have allowed a more precise buffer to be
developed with more than an order of magnitude smaller
gain error. The voltage gain is 0.98 guaranteed minimum
with a 1kΩ load and 0.96 minimum with a 100Ω load.
• Very High Slew Rate . . . . . . . . . . . . . . . . .1000V/µs (Min)
1300V/µs (Typ)
• Wide Small Signal Bandwidth . . . . . . . . . . .110MHz (Typ)
• High Output Current. . . . . . . . . . . . . . . . . . . .100mA (Min)
• High Pulsed Output Current. . . . . . . . . . . . . 400mA (Max)
• Monolithic Dielectric Isolation Construction
The HA-5002/883 will provide many present hybrid users
with a higher degree of reliability and at the same time
increase overall circuit performance.
• Replaces Hybrid LH0002
Ordering Information
Applications
• Line Driver
TEMP
PART
PART
RANGE
(°C)
NUMBER
MARKING
PACKAGE
• Data Acquisition
HA2-5002/883 HA2-5002/883 -55 to +125 8 Pin Can
• 110MHz Buffer
HA4-5002/883 HA4-5002/883 -55 to +125 20 Ld Ceramic LCC
• High Power Current Booster
• High Power Current Source
• Sample and Holds
• Radar Cable Driver
• Video Products
Pinouts
HA-5002/883 (CLCC)
HA-5002/883
(METAL CAN)
TOP VIEW
TOP VIEW
IN
8
3
2
1 20 19
18
17
16
15
14
NC
NC
4
5
6
7
8
V +
V -
1
1
3
7
5
1
V +
2
V -
2
NC
NC
NC
NC
NC
NC
V +
V -
2
2
6
2
NC
NC
9
10 11 12 13
4
OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2004-2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HA-5002/883
Absolute Maximum Ratings
Thermal Information
Thermal Resistance
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .44V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equal to Supplies
Peak Output Current (50ms On, 1s Off). . . . . . . . . . . . . . . . . .±400mA
θ
(°C/W)
160
80
θ
(°C/W)
JC
JA
Metal Can Package . . . . . . . . . . . . . . .
70
30
Ceramic LCC Package. . . . . . . . . . . . .
Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
J
Package Power Dissipation Limit at +75°C for T ≤ +175°C
J
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<4000V
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300°C
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .625mW
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25W
Package Power Dissipation Derating Factor Above +75°C
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.3mW/°C
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . .12.5mW/°C
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . ±12V to ±15V
R
≥ 100Ω
L
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379
for details.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
= ±12V and ±15V, R
SOURCE
= 50Ω, C ≤ 10pF, V = 0V, Unless Otherwise Specified.
LOAD IN
SUPPLY
GROUP A
PARAMETERS
SYMBOL
CONDITIONS
SUBGROUPS
TEMPERATURE (°C)
+25
MIN
-20
-30
-20
-30
-7
MAX
20
30
20
30
7
UNITS
mV
mV
mV
mV
µA
Input Offset
Voltage
V
V
I
V
V
V
V
= ±15V
1
2, 3
1
IO1
IO2
B1
SUP
SUP
SUP
SUP
SUP
+125, -55
+25
= ±12V
2, 3
1
+125, -55
+25
Input Bias Current
Voltage Gain 1
= ±15V, R = 1kΩ
S
2, 3
1
+125, -55
+25
-10
-7
10
7
µA
I
= ±12V, R = 1kΩ
µA
B2
S
2, 3
1
+125, -55
+25
-10
0.98
0.98
0.98
0.98
0.96
10
-
µA
+AV
V
V
= ±12V, R = 1kΩ,
V/V
V/V
V/V
V/V
V/V
1
L
= 10V
IN
2, 3
1
+125, -55
+25
-
-AV
V
V
= ±12V, R = 1kΩ,
-
1
SUP
IN
L
= -10V
2, 3
1
+125, -55
+25
-
Voltage Gain 2
Voltage Gain 3
Voltage Gain 4
+AV
V
V
= ±12V, R = 100Ω,
-
2
SUP
IN
L
= 10V
-AV
V
V
= ±12V, R = 100Ω,
1
1
1
+25
+25
+25
0.96
0.96
0.96
-
-
-
V/V
V/V
V/V
2
SUP
IN
L
= -10V
+AV
V
V
= ±15V, R = 100Ω,
SUP L
3
= 10V
IN
-AV
V
V
= ±15V, R = 100Ω,
3
SUP
IN
L
= -10V
+AV
V
= ±15V,
1
+25
0.99
0.99
-
-
V/V
V/V
4
SUP
L
IN
R
= 1kΩ,
2, 3
+125, -55
V
= +10V
-AV
V
= ±15V,
1
+25
0.99
0.99
-
-
V/V
V/V
4
SUP
L
IN
R
= 1kΩ,
2, 3
+125, -55
V
= -10V
FN3705.4
January 5, 2006
2
HA-5002/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: V
= ±12V and ±15V, R
= 50Ω, C ≤ 10pF, V = 0V, Unless Otherwise Specified.
LOAD IN
SUPPLY
SOURCE
GROUP A
PARAMETERS
SYMBOL
CONDITIONS
SUBGROUPS
TEMPERATURE (°C)
+25
MIN
10
MAX
UNITS
Output Voltage
Swing
+V
V
= ±15V,
SUP
1
-
-
V
V
OUT1
R
IN
= 100Ω,
L
2, 3
+125, -55
10
V
= +15V
-V
V
= ±15V,
1
+25
-
-
-10
-10
V
V
OUT1
SUP
L
IN
R
= 100Ω,
2, 3
+125, -55
V
= -15V
+V
V
= ±15V,
SUP
1
+25
10
10
-
-
V
V
OUT2
OUT2
R
= 1kΩ,
L
IN
2, 3
+125, -55
V
= +15V
-V
V
= ±15V,
1
+25
-
-
-10
-10
V
V
SUP
L
IN
R
= 1kΩ,
2, 3
+125, -55
V
= -15V
+V
V
= ±12V,
SUP
1
+25
10
10
-
-
V
V
OUT3
R
= 1kΩ,
L
2, 3
+125, -55
V
= +12V
IN
-V
V
= ±12V,
1
+25
-
-
-10
-10
V
V
OUT3
SUP
L
IN
R
= 1kΩ,
2, 3
+125, -55
V
= -12V
Output Current
+I
V
V
= ±15V,
1
2, 3
1
+25
+125, -55
+25
100
100
-
-
mA
mA
mA
mA
mA
mA
mA
mA
dB
OUT1
SUP
OUT
= +10V
-
-I
V
V
= ±15V,
= -10V
-100
OUT1
SUP
OUT
2, 3
1
+125, -55
+25
-
-100
+I
V
V
= ±12V,
= +10V
100
100
-
-
OUT2
SUP
OUT
2, 3
1
+125, -55
+25
-
-100
-100
-
-I
V
V
= ±12V,
= -10V
OUT2
SUP
OUT
2, 3
1
+125, -55
+25
-
Power Supply
Rejection Ratio
+PSRR
∆V
= ±5V,
SUP
54
54
1
2
V+ = +20V, V- = -15V,
V+ = +10V, V- = -15V
2, 3
+125, -55
-
dB
-PSRR
∆V
= ±5V,
SUP
1
+25
54
54
-
-
dB
dB
1
V+ = +15V, V- = -20V,
V+ = +15V, V- = -10V
2, 3
+125, -55
+PSRR
∆V
= ±5V,
1
+25
54
54
-
-
dB
dB
SUP
V+ = +17V, V- = -12V,
V+ = +7V, V- = -12V
2, 3
+125, -55
-PSRR
∆V
= ±5V,
SUP
1
+25
54
54
-
-
dB
dB
2
V+ = +12V, V- = -17V,
V+ = +12V, V- = -7V
2, 3
+125, -55
Power Supply
Current
+ICC
V
V
= ±15V,
1
2, 3
1
+25
+125, -55
+25
-
-
10
10
-
mA
mA
mA
mA
mA
mA
mA
mA
1
SUP
OUT
= 0V
-ICC
V
V
= ±15V,
= 0V
-10
-10
-
1
SUP
OUT
2, 3
1
+125, -55
+25
-
+ICC
V
V
= ±12V,
= 0V
10
10
-
2
SUP
OUT
2, 3
1
+125, -55
+25
-
-ICC
V
V
= ±12V,
= 0V
-10
-10
2
SUP
OUT
2, 3
+125, -55
-
FN3705.4
January 5, 2006
3
HA-5002/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank. See AC Specifications in Table 3
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: V
= ±15V or ±12V, R
LOAD
= 1kΩ, C
LOAD
≤ 10pF, Unless Otherwise Specified.
SUPPLY
TEMPERATURE
PARAMETERS
SYMBOL
CONDITIONS
NOTES
(°C)
MIN
MAX
UNITS
MΩ
MΩ
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
ns
Input Resistance
R
R
V
V
= ±15V
= ±12V
1
1
1
+25
1.5
-
-
IN1
SUP
SUP
+25
1.5
IN2
Slew Rate
+SR
V
V
= ±15V,
= -5V to +5V
+25
1000
-
1
2
SUP
OUT
+125, -55
+25
1000
-
-SR
V
V
= ±15V,
= +5V to -5V
1
1
1
1000
-
1
SUP
OUT
+125, -55
+25
1000
-
+SR
V
V
= ±12V,
= -5V to +5V
1000
-
SUP
OUT
+125, -55
+25
1000
-
-SR
V
V
= ±12V,
= +5V to -5V
1000
-
2
SUP
OUT
+125, -55
+25
1000
-
Rise and Fall Time
Overshoot
T
V
V
= ±15V or ±12V,
= 0 to +500mV
1, 2
1, 2
1, 2
1, 2
1
-
-
-
-
-
-
-
-
-
-
10
10
10
10
30
30
30
30
300
300
R
SUP
OUT
+125, -55
+25
ns
T
V
V
= ±15V or ±12V,
= 0 to -500mV
ns
F
SUP
OUT
+125, -55
+25
ns
+OS
-OS
V
V
= ±12V or ±15V,
= 0 to +500mV
%
SUP
OUT
+125, -55
+25
%
V
V
= ±12V or ±15V,
= 0 to -500mV
1
%
SUP
OUT
+125, -55
+25
%
Quiescent Power
Consumption
PC
PC
V
V
= ±15V,
1, 3
mW
mW
1
2
SUP
= 0V,
IN
+125, -55
I
= 0mA
OUT
V
V
= ±12V,
1, 3
+25
-
-
240
240
mW
mW
SUP
= 0V,
IN
+125, -55
I
= 0mA
= ±12V
= ±12V
OUT
Output Resistance
NOTES:
R
V
V
1
1
+25
+25
-
-
5
5
Ω
Ω
OUT1
OUT2
SUP
SUP
R
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
2. Measured between 10% and 90% points.
3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.)
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
Group A Test Requirements
SUBGROUPS (SEE TABLE 1)
1
1 (Note 1), 2, 3
1, 2, 3
Groups C and D Endpoints
1
NOTE:
1. PDA applies to Subgroup 1 only.
FN3705.4
4
January 5, 2006
HA-5002/883
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): V1-
TRANSISTOR COUNT: 27
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5002/883
IN
V -
1
V - (ALT)
1
V + (ALT)
1
V +
2
V -
2
V +
1
OUT
FN3705.4
5
January 5, 2006
HA-5002/883
Ceramic Leadles s Chip Carrier Packages (CLCC)
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES MILLIMETERS
MIN
D3
SYMBOL
A
MAX
0.100
0.088
-
MIN
1.52
1.27
-
MAX
2.54
2.23
-
NOTES
o
j x 45
0.060
0.050
-
6, 7
A1
B
-
-
B1
B2
B3
D
0.022
0.028
0.56
0.71
2, 4
-
0.072 REF
1.83 REF
E3
E
B
0.006
0.342
0.022
0.358
0.15
8.69
0.56
9.09
-
-
D1
D2
D3
E
0.200 BSC
0.100 BSC
5.08 BSC
2.54 BSC
-
-
o
h x 45
-
0.358
0.358
-
9.09
9.09
2
-
0.010 S E F S
A1
0.342
8.69
E1
E2
E3
e
0.200 BSC
0.100 BSC
0.358
0.050 BSC
0.015
5.08 BSC
2.54 BSC
9.09
1.27 BSC
0.38
1.02 REF
0.51 REF
-
A
-
PLANE 2
PLANE 1
-
-
2
-
-E-
e1
h
-
-
2
5
5
-
0.040 REF
0.020 REF
j
0.007 M E F S H S
L
0.045
0.055
0.055
0.095
0.015
1.14
1.14
1.91
0.08
1.40
1.40
2.41
0.38
L1
L2
L3
ND
NE
N
0.045
0.075
0.003
-
B1
e
-
L3
L
-H-
-
5
5
5
5
3
3
3
20
20
Rev. 0 5/18/94
-F-
NOTES:
B3
E1
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
L2
E2
B2
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
L1
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
D2
e1
D1
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
FN3705.4
6
January 5, 2006
HA-5002/883
Metal Can Packages (Can)
REFERENCE PLANE
T8.C MIL-STD-1835 MACY1-X8 (A1)
8 LEAD METAL CAN PACKAGE
A
e1
L
INCHES
MILLIMETERS
L2
L1
SYMBOL
MIN
MAX
0.185
0.019
0.021
0.024
0.375
0.335
0.160
MIN
4.19
0.41
0.41
0.41
8.51
7.75
2.79
MAX
4.70
0.48
0.53
0.61
9.40
8.51
4.06
NOTES
ØD2
A
Øb
Øb1
Øb2
ØD
ØD1
ØD2
e
0.165
0.016
0.016
0.016
0.335
0.305
0.110
-
A
A
1
k1
1
Øe
ØD ØD1
2
-
N
1
-
-
Øb1
β
α
C
L
-
Øb
k
F
0.200 BSC
0.100 BSC
5.08 BSC
2.54 BSC
-
BASE AND
Q
e1
F
-
SEATING PLANE
-
0.040
0.034
0.045
0.750
0.050
-
-
1.02
0.86
1.14
19.05
1.27
-
-
BASE METAL
LEAD FINISH
Øb2
k
0.027
0.027
0.500
-
0.69
0.69
12.70
-
-
k1
L
2
Øb1
1
L1
L2
Q
1
SECTION A-A
0.250
0.010
6.35
0.25
1
0.045
1.14
-
NOTES:
o
o
45 BSC
45 BSC
3
α
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
o
o
β
45 BSC
45 BSC
3
4
N
8
8
2. Measured from maximum diameter of the product.
Rev. 0 5/18/94
3. α is the basic spacing from the centerline of the tab to terminal 1
and β is the basic spacing of each lead or lead position (N -1
places) from α, looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3705.4
7
January 5, 2006
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