CD4047BHMSR [RENESAS]
4000/14000/40000 SERIES, MONOSTABLE MULTIVIBRATOR, UUC14, DIE-14;
| 型号： | CD4047BHMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, MONOSTABLE MULTIVIBRATOR, UUC14, DIE-14 时钟 逻辑集成电路 |
| 文件： | 总15页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4047BMS
CMOS Low-Power
Monostable/Astable Multivibrator
December 1992
Features
Description
CD4047BMS consists of a gatable astable multivibrator with logic tech-
niques incorporated to permit positive or negative edge triggered
monostable multivibrator action with retriggering and external counting
options.
• High Voltage Type (20V Rating)
• Low Power Consumption: Special CMOS Oscillator
Configuration
• Monostable (One-Shot) or Astable (Free-Running)
Operation
Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE,
RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q, Q, and
OSCILLATOR. In all modes of operation, an external capacitor must be
connected between C-Timing and RC-Common terminals, and an
external resistor must be connected between the R-Timing and RC-
Common terminals.
• True and Complemented Buffered Outputs
• Only One External R and C Required
• Buffered Inputs
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
Astable operation is enabled by a high level on the ASTABLE input or a
low level on the ASTABLE input, or both. The period of the square wave
at the Q and Q Outputs in this mode of operation is a function of the
external components employed. “True” input pulses on the ASTABLE
input or “Complement” pulses on the ASTABLE input allow the circuit to
be used as a gatable multivibrator. The OSCILLATOR output period will
be half of the Q terminal output in the astable mode. However, a 50%
duty cycle is not guaranteed at this output.
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Monostable Multivibrator Features
• Positive or Negative Edge Trigger
The CD4047BMS triggers in the monostable mode when a positive
going edge occurs on the +TRIGGER input while the -TRIGGER is held
low. Input pulses may be of any duration relative to the output pulse.
• Output Pulse Width Independent of Trigger Pulse
Duration
If retrigger capability is desired, the RETRIGGER input is pulsed. The
retriggerable mode of operation is limited to positive going edge. The
CD4047BMS will retrigger as long as the RETRIGGER input is high,
with or without transitions (See Figure 31)
• Retriggerable Option for Pulse Width Expansion
• Internal Power-On Reset Circuit
• Long Pulse Widths Possible Using Small RC Compo-
nents by Means of External Counter Provision
An external countdown option can be implemented by coupling “Q” to
an external “N” counter and resetting the counter with trigger pulse. The
counter output pulse is fed back to the ASTABLE input and has a dura-
tion equal to N times the period of the multivibrator.
• Fast Recovery Time Essentially Independent of Pulse
Width
A high level on the EXTERNAL RESET input assures no output pulse
during an “ON” power condition. This input can also be activated to ter-
minate the output pulse at any time. For monostable operation, when-
ever VDD is applied, an internal power on reset circuit will clock the Q
output low within one output period (tM).
• Pulse-Width Accuracy Maintained at Duty Cycles
Approaching 100%
Astable Multivibrator Features
• Free-Running or Gatable Operating Modes
• 50% Duty Cycle
The CD4047BMS is supplied in these 14-lead outline packages:
Braze Seal DIP
Frit Seal DIP
H4Q
H1B
• Oscillator Output Available
• Good Astable Frequency Stability: Frequency Deviation:
Ceramic Flatpack H3W
- = ±2% + 0.03%/oC at 100kHz
- = ±0.5% + 0.015%/oC at 10kHz (Circuits “Trimmed”
to Frequency VDD = 10V ± 10%
Pinout
CD4047BMS
TOP VIEW
Applications
Digital equipment where low power dissipation and/or high noise
immunity are primary design requirements
C
R
1
14 VDD
2
3
4
5
6
7
13 OSC OUT
12 RETRIGGER
11 Q
R-C COMMON
ASTABLE
ASTABLE
-TRIGGER
VSS
• Envelope Detection
• Frequency Multiplication • Timing Circuits
• Frequency Division • Time Delay Applications
• Frequency Discriminators
10 Q
9
8
EXT. RESET
+TRIGGER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3313
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-897
Specifications CD4047BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
2
µA
µA
µA
nA
nA
nA
nA
nA
nA
nA
µA
nA
µA
mV
V
o
2
+125 C
-
200
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
2
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
o
IIH
1
+25 C
-
100
1000
100
-
o
2
+125 C
-
o
VDD = 18V
3
-55 C
-
o
Input Leakage Curent
(Pin 3)
IIL
VDD = 24V, VIN = 11V or GND
1
+25 C
-300
o
2
+125 C
-10
-
o
Input Leakage Current
(Pin 3)
IIH
VDD = 26V, VIN = 13V or GND
1
2
+25 C
-
-
-
300
10
50
-
o
+125 C
o
o
o
Output Voltage
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
1, 2, 3
1
+25 C, +125 C, -55 C
o
o
o
VOH15 VDD = 15V, No Load (Note 3)
+25 C, +125 C, -55 C 14.95
o
Output Current (Sink)
Q, Q, OSC Out
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
+25 C
0.53
-
mA
o
Output Current (Sink)
Q, Q, OSC Out
1
1
1
1
1
1
+25 C
1.4
-
mA
mA
mA
mA
mA
mA
o
Output Current (Sink)
Q, Q, OSC Out
+25 C
3.5
-
o
OutputCurrent(Source)
Q, Q, OSC Out
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
IOH10 VDD = 10V, VOUT = 9.5V
IOH15 VDD = 15V, VOUT = 13.5V
+25 C
-
-
-
-
-0.53
-1.8
-1.4
-3.5
o
OutputCurrent(Source)
Q, Q, OSC Out
+25 C
o
OutputCurrent(Source)
Q, Q, OSC Out
+25 C
o
OutputCurrent(Source)
Q, Q, OSC Out
+25 C
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5RC VDD = 5V, VOUT = 0.4V
IOL10RC VDD = 10V, VOUT = 0.5V
IOL15RC VDD = 15V, VOUT = 1.5V
1
1
1
1
1
1
1
+25 C
0.78
2.0
5.2
-
-
-
mA
mA
mA
mA
mA
mA
V
o
+25 C
o
+25 C
-
o
Output Current (Source) IOH5RC VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH10RC VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15RC VDD = 15V, VOUT = 13.5V
+25 C
-0.78
-2
o
+25 C
-
o
+25 C
-
-5.2
-0.7
o
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
+25 C
-2.8
7-898
Specifications CD4047BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN MAX UNITS
0.7
GROUP A
SUBGROUPS
PARAMETER
P Threshold Voltage
Functional
SYMBOL
VPTH
F
CONDITIONS (NOTE 1)
VSS = 0V, IDD = 10µA
TEMPERATURE
o
1
7
+25 C
2.8
V
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
+25 C
VOH > VOL <
VDD/2 VDD/2
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES:
1. All voltages referenced to device GND, 100% testing being implemented
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max..
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
(NOTES 1, 2)
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
ns
o
Propagation Delay
Astable, Astable to OSC
TPLH1 VDD = 5V, VIN = VDD or GND
9
+25 C
-
-
-
-
-
-
400
540
o
o
10, 11
9
+125 C, -55 C
ns
o
Propagation Delay
Trigger to Q, Q
TPHL3 VDD = 5V, VIN = VDD or GND
TPLH3
+25 C
1000
1350
700
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Propagation Delay
(Note 2)
Astable or Astable to Q, Q
TPLH2 VDD = 5V, VIN = VDD or GND
TPLH2
+25 C
ns
o
o
10, 11
+125 C, -55 C
945
ns
o
Propagation Delay
(Note 2)
Retrigger to Q, Q
TPHL4 VDD = 5V, VIN = VDD or GND
TPLH4
9
+25 C
-
-
600
810
ns
ns
o
o
10, 11
+125 C, -55 C
o
Propagation Delay
(Note 2)
Reset to Q, Q
TPLH5 VDD = 5V, VIN = VDD or GND
TPLH5
9
+25 C
-
-
500
675
ns
ns
o
o
10, 11
+125 C, -55 C
o
Transition Time
NOTES:
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
9
+25 C
-
-
200
270
ns
ns
o
o
10, 11
+125 C, -55 C
1. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
7-899
Specifications CD4047BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
1
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
30
2
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
60
2
µA
o
o
-55 C, +25 C
µA
o
+125 C
120
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
VIH
+25 C, +125 C,
+7
-
V
o
-55 C
o
Propagation Delay
Astable, Astable to OSC
TPLH1 VDD = 10V
VDD = 15V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
200
160
350
250
450
300
300
200
200
140
100
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
o
+25 C
o
Propagation Delay
Astable or Astable to Q, Q TPHL2
TPLH2 VDD = 10V
+25 C
o
VDD = 15V
+25 C
o
Propagation Delay
Trigger to Q, Q
TPHL3 VDD = 10V
+25 C
TPLH3
o
VDD = 15V
+25 C
o
Propagation Delay
Retrigger to Q, Q
TPHL4 VDD = 10V
+25 C
TPLH4
o
VDD = 15V
+25 C
o
Propagation Delay
Reset to Q, Q
TPLH5 VDD = 10V
+25 C
TPLH5
o
VDD = 15V
+25 C
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
+25 C
o
+25 C
7-900
Specifications CD4047BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
VDD = 5V
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
MIN
MAX
±1
UNITS
%
o
Q or Q Deviation from
50% Duty Factor
QD
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
-
o
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
+25 C
±1
%
o
+25 C
±0.5
400
160
100
200
100
60
%
o
Minimum Pulse Width
+ Trigger
- Trigger
TW
TW
TW
CIN
+25 C
ns
o
+25 C
ns
o
+25 C
ns
o
Minimum Pulse Width
Reset
+25 C
ns
o
+25 C
ns
o
+25 C
ns
o
Minimum Retrigger Pulse
Width
+25 C
600
230
150
7.7
ns
o
+25 C
ns
o
+25 C
ns
o
Input Capacitance
NOTES:
+25 C
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
7.5
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 0.2µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
7-901
Specifications CD4047BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
1, 7, 9
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
Note 1
1, 2, 10, 11, 13
3-9, 12
14
Static Burn-In 2
Note 1
1, 2, 10, 11, 13
7
7, 9, 12
7
3-6, 8, 9, 12, 14
4, 5, 14
Dynamic Burn-
In Note 1
-
1, 2, 10, 11, 13
6, 8
3
Irradiation
Note 2
1, 2, 10, 11, 13
3-6, 8, 9, 12, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
7-902
CD4047BMS
TABLE 9. FUNCTIONAL TERMINAL CONNECTIONS
In all cases External resistor between terminals 2 and 3 (Note 1)
External capacitor between terminals 1 and 3 (Note 1)
TERMINAL CONNECTIONS
OUTPUT PULSE OUTPUT PERIOD OR PULSE
FUNCTION
ASTABLE MULTIVIBRATOR
Free Running
TO VDD
TO VSS
INPUT TO
FROM
WIDTH
4, 5, 6, 14
4, 6, 14
6, 14
7, 8, 9, 12
7, 8, 9, 12
-
10, 11, 13
10, 11, 13
10, 11, 13
T (10, 11) = 4.40 RC
A
True Gating
5
4
T (13) = 2.20 RC (Note 2)
A
Complement Gating
MONOSTABLE MULTIVIBRATOR
Positive Edge Trigger
Negative Edge Trigger
Retriggerable
5, 7, 8, 9, 12
4, 14
4, 8, 14
4, 14
14
5, 6, 7, 9, 12
5, 7, 9, 12
8
10, 11
10, 11
10, 11
10, 11
tM (10, 11) = 2.48 RC
6
8, 12
-
5, 6, 7, 9
External Countdown (Note 3)
NOTES:
5, 6, 7, 8, 9, 12
1. See text.
1
2. First positive / cycle pulse width = 2.48 RC. See note follow Monostable Mode Design Information.
2
3. Input Pulse to Reset of External Counting Chip External Counting Chip Output to Terminal 4.
Logic Diagrams
C
R
C-TIMING
RC
R-TIMING
3
1
2
OSCILLATOR OUT
13
10
COMMON
Q
Q
ASTABLE
ASTABLE
5
4
ASTABLE
LOW POWER
ASTABLE
MULTIVIBRATOR
FREQUENCY
DIVIDER (÷2)
GATE
CONTROL
11
-TRIGGER
6
8
MONOSTABLE
CONTROL
+TRIGGER
RETRIGGER
RETRIGGER
CONTROL
12
EXTERNAL
RESET
9
FIGURE 1. CD4047BMS LOGIC BLOCK DIAGRAM
7-903
CD4047BMS
Logic Diagrams (Continued)
*
**
RC
*
VDD
12
3
1
2
RETRIGGER
CTC
RTC
COMMON
5
ASTABLE
ASTABLE
*
4
*
8
+TRIGGER
-TRIGGER
*
6
OSC
OUT
VDD
FF1
D
Q
13
CL
CL
R1 R2
14
7
VDD
VSS
S
S
10
11
Q
D
FF3
CL
Q
Q
FF4
CL
CL
Q
Q
D
D
FF2
CL
VSS
CL Q
R
CL
R1 R2
R
*
9
EXTERNAL
RESET
VDD
VDD
SPECIAL
**
RC COMMON
PROTECTION
NETWORK
CAUTION: Terminal 3 is more sensitive
to static electrical discharge. Extra
handling precautions are recommended.
INPUTS PROTECTED
BY CMOS
*
PROTECTION
NETWORK
VSS
VSS
FIGURE 2. CD4047BMS LOGIC DIAGRAM
R2 R1
CL
CL
p
n
p
n
Q
D
D
Q
R1 R2
CL
CL
CL
CL
CL
CL
p
n
p
n
R1 R2
FF1, FF3
CL
CL
(a)
Q
CL
S
CL
S
p
n
Q
p
n
S
D
D
Q
Q
CL
CL
CL
CL
CL
CL
R
p
n
p
n
FF2, FF4
R
R
CL
CL
(b)
FIGURE 3. DETAIL LOGIC DIAGRAM FOR FLIP-FLOPS FF1 AND FF3 (a) AND FOR FLIP-FLOPS FF2 AND FF4 (b)
7-904
CD4047BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
7.5
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-2.5
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-2.5
-7.5
-10
-12.5
-15
-10V
-10V
-5
-15V
-15V
-7.5
FIGURE 6. TYP. OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
400
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 5V
600
300
200
100
SUPPLY VOLTAGE (VDD) = 5V
400
10V
15V
10V
200
15V
AMBIENT TEMPERATURE (TA) = +25oC
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYP.PROPAGATIONDELAYTIMEASAFUNCTIONOF
LOAD CAPACITANCE (ASTABLE, ASTABLE TO Q, Q)
FIGURE 9. TYP. PROPAGATION DELAY TIME AS A FUNCTION
OF LOAD CAPACITANCE (+ OR - TRIGGER TO Q, Q)
7-905
CD4047BMS
Typical Performance Characteristics (Continued)
4
3
2
1
0
AMBIENT TEMPERATURE (TA) = +25oC
CX = 1µF
AMBIENT TEMPERATURE (TA) = +25oC
1MΩ AND 100kΩ
10kΩ
200
10MΩ
SUPPLY VOLTAGE (VDD) = 5V
150
10MΩ
-1
-2
-3
-4
100
50
0
10V
15V
RX = 1MΩ AND
100kΩ
10kΩ
0
20
40
60
80
100
0
2
4
6
8
10
12
14
16
18
20
LOAD CAPACITANCE (CL) (pF)
SUPPLY VOLTAGE (VDD) (V)
FIGURE 10. TYP. TRANSITION TIME AS A FUNCTION OF LOAD
CAPACITANCE
FIGURE 11. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs SUPPLY VOLTAGE
4
AMBIENT TEMPERATURE (TA) = +25oC
CX = 1000pF
4
AMBIENT TEMPERATURE (TA) = +25oC
CX = 0.01µF
3
3
2
10MΩ
10kΩ
2
1
1
10kΩ
1MΩ
100kΩ
1MΩ AND
10MΩ
RX = 1MΩ AND
10kΩ
0
-1
-2
-3
-4
0
100kΩ
10kΩ
RX = 1MΩ
100kΩ
-1
-2
-3
-4
10MΩ
10kΩ
10kΩ
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE (VDD) (V)
SUPPLY VOLTAGE (VDD) (V)
FIGURE 12. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs SUPPLY VOLTAGE
FIGURE 13. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs SUPPLY VOLTAGE
1
2
CX = 0.1µF
RX = 1MΩ
CX = 1µF
RX = 1MΩ
10V, 15V
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V
1
5V
0
10V
0
15V
-1
5V
15V
-1
10V, 15V
-2
10V
-2
-3
-55
-55
-15
25
65
105
145
-15
25
65
105
145
AMBIENT TEMPERATURE (TA) (oC)
AMBIENT TEMPERATURE (TA) (oC)
FIGURE 14. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE (ULTRA
LOW FREQ.)
FIGURE 15. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE (LOW
FREQ.)
7-906
CD4047BMS
Typical Performance Characteristics (Continued)
2
1
0
12
10
8
CX = 0.01µF
RX = 100kΩ
CX = 1000pF
RX = 10kΩ
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V, 10V
15V
6
4
5V AND 10V
15V
2
10V, 15V
10V AND 15V
5V
0
-1
-2
-2
-4
-55
-15
25
65
105
145
-55 -35 -15
-5
25
45
65
85 105 125 145
AMBIENT TEMPERATURE (TA) (oC)
AMBIENT TEMPERATURE (TA) (oC)
FIGURE 16. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
FIGURE 17. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE (HIGH
FREQ.)
ACCURACY vs AMBIENT TEMPERATURE (MEDIUM
FREQ.)
8
AMBIENT TEMPERATURE (TA) = +25oC
RX = 10kΩ
SUPPLY VOLTAGE (VDD) = 5V
6
CX = 1µF
4
2
20
10
1kΩ
100pF
100kΩ
10kΩ, 1MΩ AND 10MΩ
10kΩ
0
0.001µF
RX = 100kΩ, 1MΩ, 10MΩ
1kΩ
-2
0.01µF, 0.1µF, 1µF
0.01µF, 0.1µF, 1µF
0.001µF
-4
-6
0
CX = 100pF
-10
-8
-55
-15
25
65
105
145
0
5
10
15
20
25
AMBIENT TEMPERATURE (TA) (oC)
SUPPLY VOLTAGE (VDD) (V)
FIGURE 18. TYPICAL ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE
FIGURE 19. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
SUPPLY VOLTAGE
8
AMBIENT TEMPERATURE (TA) = +25oC
8
AMBIENT TEMPERATURE (TA) = +25oC
CX = 1000pF
6
CX = 0.1µF
6
4
4
2
2
RX = 1MΩ AND 10Ω
10kΩ, 100kΩ, 1MΩ AND 10MΩ
100kΩ
10kΩ
0
0
10MΩ
-2
-2
RX = 10kΩ, 100kΩ, 1MΩ
-4
-6
-4
-6
-8
-8
0
5
10
15
20
25
0
5
10
15
20
25
SUPPLY VOLTAGE (VDD) (V)
SUPPLY VOLTAGE (VDD) (V)
FIGURE 20. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
SUPPLY VOLTAGE
FIGURE 21. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
SUPPLY VOLTAGE
7-907
CD4047BMS
Typical Performance Characteristics (Continued)
RX = 100kΩ
SUPPLY VOLTAGE (VDD) = 10V OR 15V
8
RX = 100kΩ
SUPPLY VOLTAGE (VDD) = 5V
10
8
6
CX = 100pF
4
6
4
2
0
0.001µF
0.01µF
2
0.1µF
0.1µF
0
0.1µF, 0.01µF
0.01µF
-2
-4
-6
-8
-10
-12
-2
0.01µF
0.001µF
0.1µF AND 0.001µF
-4
-6
100pF
0.001µF
85 105 125 145
-8
-55 -35 -15
5
25
45 65
-50 -35 -15
5
25 45 65 85 105 125 145
AMBIENT TEMPERATURE (TA) (oC)
AMBIENT TEMPERATURE (TA) (oC)
FIGURE 22. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
AMBIENT TEMPERATURE
FIGURE 23. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
AMBIENT TEMPERATURE
4
4
CX = 1000pF
SUPPLY VOLTAGE (VDD) = 15V
CX = 1000pF
SUPPLY VOLTAGE (VDD) = 5V OR 10V
10MΩ
2
2
0
10kΩ
10kΩ
0
100kΩ
10kΩ
10MΩ
100kΩ
-2
-4
RX = 1MΩ
-2
RX = 1MΩ
10kΩ 100kΩ
-4
100kΩ
1MΩ
-6
-6
-8
-8
1MΩ
-10
-10
-12
10MΩ
10MΩ
85 105 125 145
-12
-55 -35 -15
5
25
45 65
85 105 125 145
-50 -35 -15
5
25
45
65
AMBIENT TEMPERATURE (TA) (oC)
AMBIENT TEMPERATURE (TA) (oC)
FIGURE 24. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
AMBIENT TEMPERATURE
FIGURE 25. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
AMBIENT TEMPERATURE
105
106
ASTABLE MODE
SUPPLY VOLTAGE (VDD) = 10V
ASTABLE MODE
SUPPLY VOLTAGE (VDD) = 5V
105
104
C =100pF
C =100pF
C =1000pF
104
103
C = 0.01µF
C =1000pF
C = 0.1µF
C = 0.01µF
C =10pF
C =10pF
C = 0.1µF
103
102
101
102
101
100
10-1
10-1
100
101
102
103
104
105
106
100
101
102
103
104
105
106
Q OR Q FREQUENCY (F) (Hz)
Q OR Q FREQUENCY (F) (Hz)
FIGURE 26. TYPICAL POWER DISSIPATION vs OUTPUT
FREQUENCY (VDD = 5V)
FIGURE 27. TYPICAL POWER DISSIPATION vs OUTPUT
FREQUENCY (VDD = 10V)
7-908
CD4047BMS
Typical Performance Characteristics (Continued)
ASTABLE MODE
SUPPLY VOLTAGE (VDD) = 15V
105
C =100pF
C =1000pF
C = 0.01µF
104
103
102
C =10pF
C = 0.1µF
10-1
100
101
102
103
104
105
106
Q OR Q FREQUENCY (F) (Hz)
FIGURE 28. TYPICAL POWER DISSIPATION vs OUTPUT FREQUENCY (VDD = 15V)
Astable Mode Design Information
Monostable Mode Design Information
Unit-to-Unit Transfer Voltage Variations
The following analysis presents variations from unit to unit as a
function of transfer voltage (VTR) shift (33% - 67% VDD) for
one shot (monostable) operation.
The following analysis presents variations from unit to unit as
a function of transfer voltage (VTR) shift (33%-67% VDD) for
free running (astable) operation.
TERMINAL 8
t1
t2
t1
t2
TERMINAL 13
TERMINAL 10
t1´ t2
tM
t1´ t2
tM
TERMINAL 13
TERMINAL 10
tA/2
tA/2
tA
FIGURE 30. MONOSTABLE WAVEFORMS
FIGURE 29. ASTABLE MODE WAVEFORMS
VTR
VTR
t1´ = -RC In
;
t1 = -RC In
t2 = -RC In
;
2VDD
VDD + VTR
typically, t1 = 1.1RC
typically, t1´ = 1.38RC
tM = (t1´ + t2)
VDD - VTR
;
(VTR)(VDD - VTR)
2VDD - VTR
tM = -RC In
(2VDD - VTR)(2VDD)
typically, t2 = 1.1RC
where tM = Monostable mode pulse width.
Values for tM are as follows:
t
= 2(t1 + t2)
= -2RC In
A
(VTR)(VDD - VTR)
Typ: VTR = 0.5VDD
Min: VTR = 0.33VDD
Max: VTR = 0.67VDD
tM = 2.48RC
tM = 2.71RC
tM = 2.48RC
(VDD + VTR)(2VDD - VTR)
Typ: VTR = 0.5VDD
Min: VTR = 0.33VDD
Max: VTR = 0.67VDD
t
t
t
= 4.40RC
= 4.62RC
= 4.62RC
A
A
A
thus if tM = 2.48RC is used, the variation will be +9.3%,
-0% due to variations in transfer voltage.
tA = 4.40RC
NOTES:
thus if
is used, the variation will be +5%, -0%
due to variations in transfer voltage.
1. In the astable mode, the first positive half cycle has a duration of
tM; succeeding durations are t /s.
A
Variations Due to VDD and Temperature Changes
2. In addition to variations from unit to unit, the monostable pulse
width varies with VDD and temperature. These variations are
presented in graphical form in Figures 19 to 26 with 10V as ref-
In addition to variations from unit to unit, the astable period
varies with VDD and temperature, Typical variations are pre-
sented in graphical form in Figures 11 to 18 with 10V as ref-
erence for voltage variations curves and +25oC as reference
for temperature variations curves.
o
erence for voltage variation curves and +25 C as reference for
temperature variation curves.
7-909
CD4047BMS
Retrigger Mode Operation
However, in consideration of accuracy, C must be much larger
than the inherent stray capacitance in the system (unless this
capacitance can be measured and taken into account). R must
be much larger than the CMOS “ON” resistance in series with
it, which typically is hundreds of Ω. In addition, with very large
values of R, some short term instability with respect to time may
be noted.
The CD4047BMS can be used in the retrigger mode to extend
the output pulse duration, or to compare the frequency of an
input signal with that of the internal oscillator. In the retrigger
mode the input pulse is applied to terminal 12, and the output is
taken from terminal 10 or 11. As shown in Figure 31 normal
monostable action is obtained when one retrigger pulse is
applied. Extended pulse duration is obtained when more than
one pulse is applied.
The recommended values for these components to maintain
agreement with previously calculated formulas without trimming
should be:
For two input pulses, tRE = t1´ + t1 + 2t2. For more than two
pulses, the output pulse width is an integral number of time peri-
ods, with the first time period being t1´ + t2, typically, 2.48RC, and
all subsequent time periods being t1 + t2, typically, 2.2RC.
C ≥ 100pF, up to any practical value, for astable modes;
C ≥ 1000pF, up to any practical value for monostable modes.
10kΩ ≤ R ≤ 1MΩ
External Counter Option
Time tM can be extended by any amount with the use of external
counting circuitry. Advantages include digitally controlled pulse
duration, small timing capacitors for long time periods, and
extremely fast recovery time. A typical implementation is shown
in Figure 32. The pulse duration at the output is
Power Consumption
In the standby mode (Monostable or Astable), power dissipa-
tion will be a function of leakage current in the circuit, as shown
in the static electrical characteristics. For dynamic operation,
the power needed to charge the external timing capacitor C is
given by the following formula:
text = (N - 1) (tA) + (tM + tA/2)
where text = pulse duration of the circuitry, and N is the number
of counts used.
Astable Mode:
P = 2CV2f. (Output at terminal No. 13)
P = 4CV2f. (Output at terminal Nos. 10 and 11)
Monostable Mode:
OPTIONAL
BUFFER
AST
CD4047BMS
Q
CD4017BMS
R
CL
OUT
2
12
(2.9CV ) (Duty Cycle)
P =
11
T
INPUT
PULSE
TEXT
(Output at terminal Nos. 10 to 11)
The circuit is designed so that most of the total power is con-
sumed in the external components. In practice, the lower the
values of frequency and voltage used, the closer the actual
power dissipation will be to the calculated value.
FIGURE 32. IMPLEMENTATION OF EXTERNAL COUNTER OPTION
Timing Component Limitations
The capacitor used in the circuit should be non polarized and
have low leakage (i.e. the parallel resistance of the capacitor
should be at least an order of magnitude greater than the exter-
nal resistor used). There is no upper or lower limit for either R or
C value to maintain oscillation.
Because the power dissipation does not depend on R, a
design for minimum power dissipation would be a small value
of C. The value of R would depend on the desired period
(within the limitations discussed above). See Figures 26, 27,
and 28 for typical power consumption in astable mode.
+TRIGGER &
RETRIGGER
TERMINALS
8 & 12
OSC OUTPUT
TERMINAL 13
t1´ t2
tRE
t1´ t2 t1´ t2
t1´ t2 t1´ t2 t1´ t2 t1´ t2
t1´ t2 t1´ t2 t1´ t2
Q OUTPUT
TERMINAL 10
tRE
tRE
tRE
FIGURE 31. RETRIGGER MODE WAVEFORMS
7-910
CD4047BMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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