BB305CEW-TL-E [RENESAS]
Built in Biasing Circuit MOS FET IC VHF RF Amplifier; 内置偏置电路MOS FET的IC甚高频射频放大器型号: | BB305CEW-TL-E |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | Built in Biasing Circuit MOS FET IC VHF RF Amplifier |
文件: | 总10页 (文件大小:213K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BB305C
Built in Biasing Circuit MOS FET IC
VHF RF Amplifier
REJ03G0828-0600
(Previous ADE-208-608D)
Rev.6.00
Aug.10.2005
Features
•
•
•
•
Built in Biasing Circuit; To reduce using parts cost & PC board space.
Superior cross modulation characteristics.
High gain; (PG = 28 dB typ. at f = 200 MHz)
Wide supply voltage range;
Applicable with 5 V to 9 V supply voltage.
•
•
Withstanding to ESD;
Built in ESD absorbing diode. Withstand up to 200V at C = 200 pF, Rs = 0 conditions.
Provide mini mold packages; CMPAK-4 (SOT-343mod)
Outline
RENESAS Package code: PTSP0004ZA-A
(Package name: CMPAK-4
)
2
1. Source
2. Gate1
3. Gate2
4. Drain
3
1
4
Notes:
1. Marking is “EW –”.
2. BB305C is individual type number of RENESAS BBFET.
Rev.6.00 Aug 10, 2005 page 1 of 9
BB305C
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Symbol
VDS
Ratings
Unit
12
+10
V
V
VG1S
–0
Gate2 to source voltage
Drain current
VG2S
ID
+10
V
25
mA
mW
°C
°C
Channel power dissipation
Channel temperature
Storage temperature
Pch
Tch
Tstg
100
150
–55 to +150
Electrical Characteristics
(Ta = 25°C)
Item
Symbol
Min
12
Typ
—
Max
—
Unit
Test conditions
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Gate2 to source breakdown voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Gate2 to source cutoff voltage
Input capacitance
V(BR)DSS
V(BR)G1SS
V(BR)G2SS
IG1SS
V
V
ID = 200 µA, VG1S = VG2S = 0
IG1 = +10 µA, VG2S = VDS = 0
IG2 = ±10 µA, VG1S = VDS = 0
VG1S = +9 V, VG2S = VDS = 0
VG2S = ±9 V, VG1S = VDS = 0
VDS = 5 V, VG2S = 4 V, ID = 100 µA
VDS = 5 V, VG1S = 5 V, ID = 100 µA
VDS = 5 V, VG1 = 5 V
+10
±10
—
—
—
—
—
V
—
+100
±100
1.0
1.0
3.5
1.9
nA
nA
V
IG2SS
—
—
VG1S(off)
VG2S(off)
Ciss
0.4
0.4
2.3
1.1
—
—
—
V
2.8
1.5
pF
pF
pF
mA
VG2S = 4 V, RG = 82 kΩ,
f = 1 MHz
Output capacitance
Coss
Reverse transfer capacitance
Drain current
Crss
0.017 0.04
ID(op)
1
10
15
13
28
28
28
28
1.3
1.3
20
—
—
—
—
—
1.8
—
VDS = 5 V, VG1 = 5 V, VG2S = 4 V,
RG = 82 kΩ
VDS = 9 V, VG1 = 9 V, VG2S = 6 V,
RG = 220 kΩ
VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG =82 kΩ, f = 1 kHz
VDS = 9 V, VG1 = 9 V, VG2S = 6 V,
RG = 220 kΩ, f = 1 kHz
VDS = 5 V, VG1 = 5 V, VG2S = 4 V,
RG = 82 kΩ, f = 200 MHz
VDS = 9 V, VG1 = 9 V, VG2S = 6 V,
RG = 220 kΩ, f = 200 MHz
VDS = 5 V, VG1 = 5 V, VG2S =4 V,
RG = 82 kΩ, f = 200 MHz
DS = 9 V, VG1 = 9 V, VG2S = 6 V,
I
D(op) 2
—
23
—
24
—
—
—
mA
mS
mS
dB
dB
dB
dB
Forward transfer admittance
Power gain
|yfs|1
|yfs|2
PG1
PG2
NF1
NF2
Noise figure
V
RG = 220 kΩ, f = 200 MHz
Rev.6.00 Aug 10, 2005 page 2 of 9
BB305C
Main Characteristics
Test Circuit for Operating Items (ID(op) , |yfs|, Ciss, Coss, Crss, NF, PG)
VG2
VG1
RG
Gate 1
Source
Gate 2
Drain
A
ID
200MHz Power Gain, Noise Figure Test Circuit
VT
VG2
VT
1000p
1000p
1000p
47k
BBFET
47k
1000p
1SV70
Output(50Ω)
47k
L1
1000p
L2
Input(50Ω)
10p max
1000p
RG
1000p
RFC
1SV70
82k
36p
1000p
VD = VG1
Unit Resistance (Ω)
Capacitance (F)
L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns
L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns
RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns
Rev.6.00 Aug 10, 2005 page 3 of 9
BB305C
Maximum Channel Power
Dissipation Curve
Typical Output Characteristics
VG2S = 4 V
25
20
15
10
5
200
150
100
50
V
G1 = VDS
Ω
180 k
0
0
50
100
150
200
1
2
3
4
5
Ambient Temperature Ta (°C)
Drain to Source Voltage VDS (V)
Drain Current vs.
Gate2 to Source Voltage
Drain Current vs. Gate1 Voltage
VDS = 5 V
25
20
15
10
5
20
16
12
8
VDS = VG1 = 5 V
R
G = 68 kΩ
4 V
3 V
2 V
VG2S = 1 V
4
0
0
4.0
1
2
3
4
5
0.8
1.6
2.4
3.2
Gate1 Voltage VG1 (V)
Gate2 to Source Voltage VG2S (V)
Drain Current vs. Gate1 Voltege
VDS = 5 V
Drain Current vs. Gate1 Voltege
VDS = 5 V
20
16
12
8
20
16
12
8
RG = 100 kΩ
R
G = 82 kΩ
4 V
4 V
3 V
3 V
2 V
VG2S = 1 V
2 V
VG2S = 1 V
4
4
0
0
1
2
3
4
5
1
2
3
4
5
Gate1 Voltage VG1 (V)
Gate1 Voltage VG1 (V)
Rev.6.00 Aug 10, 2005 page 4 of 9
BB305C
Forward Transfer Admittance
vs. Gate1 Voltage
Forward Transfer Admittance
vs. Gate1 Voltage
30
24
18
12
6
30
24
18
12
6
VDS = 5 V
VDS = 5 V
4 V
R
G = 68 kΩ
4 V
R
G = 82 kΩ
f = 1 kHz
f = 1 kHz
3 V
3 V
2 V
2 V
VG2S = 1 V
VG2S = 1 V
0
0
1
2
3
4
5
1
2
3
4
5
Gate1 Voltage VG1 (V)
Gate1 Voltage VG1 (V)
Forward Transfer Admittance
vs. Gate1 Voltage
Power Gain vs. Gate Resistance
40
35
30
25
20
30
24
18
12
6
VDS = 5 V
RG = 100 kΩ
4 V
f = 1 kHz
3 V
2 V
VDS = 5 V
V
V
G1 = 5 V
G2S = 4 V
15
10
f = 200 MHz
VG2S = 1 V
4 5
0
10
20 50 100 200
500 1000
1
2
3
Gate1 Voltage VG1 (V)
Gate Resistance RG (kΩ)
Noise Figure vs. Gate Resistance
VDS = 5 V
Power Gain vs. Drain Current
4
3
2
40
35
30
25
20
15
10
VG1 = 5 V
VG2S = 4 V
f = 200 MHz
VDS = 5 V
V
V
G1 = 5 V
G2S = 4 V
1
0
RG = variable
f = 200 MHz
0
10
20
50 100 200
500 1000
5
10
15
20
25
30
Gate Resistance RG (kΩ)
Drain Current ID (mA)
Rev.6.00 Aug 10, 2005 page 5 of 9
BB305C
Noise Figure vs. Drain Current
VDS = 5 V
Drain Current vs. Gate Resistance
30
25
20
15
10
4
3
2
1
V
V
G1 = 5 V
G2S = 4 V
R
G = variable
f = 200 MHz
VDS = 5 V
G1 = 5 V
VG2S = 4 V
5
0
V
0
10
20
50 100 200
500 1000
5
10
15
20
25
30
Gate Resistance RG (kΩ)
Drain Current ID (mA)
Gain Reduction vs.
Input Capacitance vs.
Gate2 to Source Voltage
Gate2 to Source Voltage
VDS = 5 V
60
50
40
30
20
10
6
5
4
3
2
1
0
V
G1 = 5 V
VG2S = 4 V
G = 82 kΩ
f = 200 MHz
R
VDS = 5 V
VG1 = 5 V
RG = 82 k
f = 1 MHz
0
1
2
3
5
4
0
1
2
3
5
4
Gate2 to Source Voltage VG2S (V)
Gate2 to Source Voltage VG2S (V)
Rev.6.00 Aug 10, 2005 page 6 of 9
BB305C
S21 Parameter vs. Frequency
S11 Parameter vs. Frequency
Scale: 1 / div.
1
90°
.8
1.5
60°
.6
120°
2
.4
3
30°
4
150°
.2
5
10
.2
.4 .6 .8 1
1.5 2 3 4 5 10
0
180°
0°
–10
–5
–4
–.2
–30°
–150°
–3
–.4
–2
–60°
–120°
Test Condition :
–.6
–1.5
–.8
–1
–90°
V
V
= 5 V , V = 5 V
G1
Test Condition :
V
V
= 5 V , V = 5 V
G1
DS
DS
= 4 V , R = 82 kΩ
= 4 V , R = 82 kΩ
G2S
G
G2S
G
50 — 1000 MHz (50 MHz step)
50 — 1000 MHz (50 MHz step)
S12 Parameter vs. Frequency
S22 Parameter vs. Frequency
Scale: 0.002 / div.
1
90°
.8
1.5
60°
.6
120°
2
.4
3
30°
150°
4
.2
5
10
.2
.4 .6 .8 1
1.5 2 3 4 5 10
0
180°
0°
–10
–5
–4
–.2
–30°
–150°
–3
–.4
–2
–60°
–120°
–.6
–1.5
–.8
–1
–90°
Test Condition :
V
V
= 5 V , V
= 5 V
= 4 V , R = 82 kΩ
DS
G1
Test Condition :
V
V
= 5 V , V = 5 V
G1
DS
G2S
G
= 4 V , R = 82 kΩ
G2S
G
50 — 1000 MHz (50 MHz step)
50 — 1000 MHz (50 MHz step)
Rev.6.00 Aug 10, 2005 page 7 of 9
BB305C
S Parameter
(VDS = VG1 = 5V, VG2S = 4V, RG = 82kΩ, Zo = 50Ω)
S11
S21
S12
S22
f(MHz)
MAG.
ANG.
–4.8
MAG.
2.69
2.68
2.66
2.62
2.60
2.54
2.47
2.42
2.38
2.32
2.25
2.18
2.12
2.06
2.00
1.94
1.89
1.83
1.78
1.73
ANG.
174.9
169.3
163.4
157.5
152.0
146.3
140.9
135.7
130.5
125.7
120.8
116.2
111.5
106.8
102.5
98.4
MAG.
ANG.
91.4
90.5
73.8
74.9
70.1
69.0
63.7
64.8
56.8
58.6
54.4
53.3
49.5
48.6
49.7
51.6
53.3
57.9
72.9
78.9
MAG.
0.991
0.992
0.991
0.989
0.985
0.981
0.977
0.973
0.967
0.962
0.957
0.952
0.944
0.939
0.933
0.927
0.921
0.915
0.909
0.904
ANG.
–2.2
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
0.991
0.991
0.982
0.975
0.972
0.956
0.942
0.928
0.920
0.906
0.894
0.880
0.868
0.854
0.842
0.835
0.820
0.802
0.801
0.789
0.00090
0.00153
0.00243
0.00293
0.00370
0.00444
0.00478
0.00535
0.00551
0.00549
0.00584
0.00542
0.00562
0.00509
0.00465
0.00427
0.00416
0.00289
0.00288
0.00241
–9.9
–4.8
–15.4
–20.7
–25.6
–30.6
–35.5
–40.1
–44.9
–49.2
–53.6
–57.8
–62.1
–66.2
–70.3
–73.9
–77.7
–81.5
–84.7
–87.9
–7.5
–9.9
–12.6
–15.0
–17.3
–19.7
–22.0
–24.5
–26.9
–29.2
–31.5
–33.8
–36.1
–38.3
–40.5
–42.7
–44.9
–47.1
94.0
89.6
85.6
82.1
Rev.6.00 Aug 10, 2005 page 8 of 9
BB305C
Package Dimensions
JEITA Package Code
SC-82A
RENESAS Code
PTSP0004ZA-A
Package Name
MASS[Typ.]
0.006g
CMPAK-4(T) / CMPAK-4(T)V
D
A
e2
B
e
Q
b1
c
B
E
HE
LP
Reference
Symbol
Dimension in Millimeters
Min
0.8
0
Nom
Max
1.1
0.1
1.0
L
A
A
A
A
1
2
3
A
A
L1
0.8
0.9
0.25
0.32
0.42
0.3
A3
b
b
0.25
0.35
0.4
0.5
x
S
A
M
e2
e
b
b
b
1
2
3
0.4
c
0.1
0.13
0.11
2.0
0.15
c
1
A2
A1
A
l1
D
E
e
1.8
2.2
1.15
1.25
0.65
1.35
e
0.6
2.1
2
b5
y
S
H
1.8
0.3
0.1
0.2
2.4
0.7
e1
E
S
L
L
0.5
1
b
b1
b3
L
0.6
P
l1
b
2
x
0.05
0.05
0.45
0.55
c1
c
1
y
b
4
5
1
c
c
b
e
b4
Pattern of terminal position areas
1.5
0.2
l
0.9
1
A-A Section
B-B Section
Q
Ordering Information
Part Name
Quantity
Shipping Container
φ 178 mm Reel, 8 mm Emboss Taping
BB305CEW-TL-E
3000
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.6.00 Aug 10, 2005 page 9 of 9
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
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publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
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http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .3.0
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