ALC882H-LF [REALTEK]
7.12 CHANNEL HIGH DEFINITION AUDIO CODEC;
| 型号： | ALC882H-LF |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | 7.12 CHANNEL HIGH DEFINITION AUDIO CODEC |
| 文件： | 总83页 (文件大小：1329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC882 Series
7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC
DATASHEET
Rev. 1.5
04 October 2005
Track ID: JATR-1076-21
ALC882 Series
Datasheet
COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC882 Series Audio Codec ICs.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide. In that event, please
contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
Release Date
2005/01/27
2005/03/25
Summary
First release.
1.1
Change to package/version ID (see page 6).
Change to .Ordering Information, page 73.
Add Port Information to pin assignments figure (see Figure 3, page 6).
Expand section 10 Application Notes, page 67.
Add ALC882DTS-LF version (see Ordering Information, page 73).
Delete ‘DVD Contents protection’ in ‘General Description’, page 1.
Update ordering information (see Table 80, on page 73).
Update Table 75, page 62.
1.2
2005/05/24
1.3
1.4
1.5
2005/08/04
2005/09/01
2005/10/04
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Table of Contents
1. General Description .................................................................................................... 1
2. Features ........................................................................................................................ 2
2.1. HARDWARE FEATURES.....................................................................................................................2
2.2. SOFTWARE FEATURES ......................................................................................................................3
3. System Applications .................................................................................................... 3
4. Block Diagram............................................................................................................. 4
4.1. ANALOG INPUT/OUTPUT UNIT .........................................................................................................5
5. Pin Assignments........................................................................................................... 6
5.1. LEAD (PB)-FREE PACKAGE AND VERSION IDENTIFICATION .............................................................6
6. Pin Descriptions........................................................................................................... 7
6.1. DIGITAL I/O PINS .............................................................................................................................7
6.2. ANALOG I/O PINS.............................................................................................................................7
6.3. FILTER/REFERENCE ..........................................................................................................................8
6.4. POWER/GROUND ..............................................................................................................................8
7. High Definition Audio Link Protocol ........................................................................ 9
7.1. LINK SIGNALS ..................................................................................................................................9
7.1.1.
7.1.2.
Signal Definitions.................................................................................................................................................10
Signaling Topology...............................................................................................................................................11
7.2. FRAME COMPOSITION.....................................................................................................................12
7.2.1.
7.2.2.
7.2.3.
7.2.4.
7.2.5.
Outbound Frame – Single SDO............................................................................................................................12
Outbound Frame – Multiple SDO ........................................................................................................................13
Inbound Frame – Single SDI................................................................................................................................14
Inbound Frame – Multiple SDI ............................................................................................................................15
Variable Sample Rates..........................................................................................................................................15
7.3. RESET AND INITIALIZATION............................................................................................................18
7.3.1.
7.3.2.
7.3.3.
Link Reset .............................................................................................................................................................18
Codec Reset..........................................................................................................................................................19
Codec Initialization Sequence ..............................................................................................................................20
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7.4. VERB AND RESPONSE FORMAT.......................................................................................................20
7.4.1.
7.4.2.
Command Verb Format ........................................................................................................................................20
Response Format..................................................................................................................................................21
7.5. POWER MANAGEMENT ...................................................................................................................21
8. Supported Verbs and Parameters............................................................................ 23
8.1. VERB – GET PARAMETERS (VERB ID=F00H) .................................................................................23
8.1.1.
8.1.2.
8.1.3.
8.1.4.
8.1.5.
8.1.6.
8.1.7.
8.1.8.
8.1.9.
Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................23
Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................23
Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................24
Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)...........................................................24
Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................25
Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................25
Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................26
Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................27
Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................28
8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)................................29
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)..............................29
8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ............................................................30
8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh).......................................................30
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) .......................................................30
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ...............................................................31
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ...................................................31
8.2. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................32
8.3. VERB – SET CONNECTION SELECT (VERB ID=701H) .....................................................................32
8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H)..............................................................33
8.5. VERB – GET PROCESSING STATE (VERB ID=F03H)........................................................................37
8.6. VERB – SET PROCESSING STATE (VERB ID=703H) ........................................................................37
8.7. VERB – GET COEFFICIENT INDEX (VERB ID=DH) ..........................................................................38
8.8. VERB – SET COEFFICIENT INDEX (VERB ID=5H)............................................................................38
8.9. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH).................................................................39
8.10. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..................................................................39
8.11. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................40
8.12. VERB – SET AMPLIFIER GAIN (VERB ID=3H).................................................................................42
8.13. VERB – GET CONVERTER FORMAT (VERB ID=AH)........................................................................43
8.14. VERB – SET CONVERTER FORMAT (VERB ID=2H) .........................................................................44
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8.15. VERB – GET POWER STATE (VERB ID=F05H)................................................................................45
8.16. VERB – SET POWER STATE (VERB ID=705H).................................................................................46
8.17. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................46
8.18. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ....................................................47
8.19. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)...................................................................47
8.20. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................48
8.21. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................49
8.22. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................49
8.23. VERB – GET PIN SENSE (VERB ID=F09H)......................................................................................50
8.24. VERB – EXECUTE PIN SENSE (VERB ID=709H)..............................................................................50
8.25. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) ...........................................................51
8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR
BYTES 0, 1, 2, 3).............................................................................................................................51
8.27. VERB – GET BEEP GENERATOR (VERB ID=F0AH) .......................................................................52
8.28. VERB – SET BEEP GENERATOR (VERB ID=70AH) ........................................................................52
8.29. VERB – GET GPIO DATA (VERB ID= F15H) ..................................................................................53
8.30. VERB – SET GPIO DATA (VERB ID= 715H)...................................................................................53
8.31. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).....................................................................54
8.32. VERB – SET GPIO ENABLE MASK (VERB ID=716H)......................................................................54
8.33. VERB – GET GPIO DIRECTION (VERB ID=F17H)...........................................................................55
8.34. VERB – SET GPIO DIRECTION (VERB ID=717H)............................................................................55
8.35. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ...........................56
8.36. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ............................56
8.37. VERB – FUNCTION RESET (VERB ID=7FFH) ..................................................................................57
8.38. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) ..............57
8.39. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ................59
8.40. GET/SET VOLUME KNOB WIDGET (NID=21H) (VERB ID= F0FH/70FH)......................................60
9. Electrical Characteristics ......................................................................................... 61
9.1. DC CHARACTERISTICS ...................................................................................................................61
9.1.1.
9.1.2.
9.1.3.
9.1.4.
Absolute Maximum Ratings..................................................................................................................................61
Threshold Voltage.................................................................................................................................................61
Digital Filter Characteristics...............................................................................................................................62
S/PDIF Input/Output Characteristics...................................................................................................................62
9.2. AC CHARACTERISTICS ...................................................................................................................63
9.2.1.
Link Reset and Initialization Timing.....................................................................................................................63
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9.2.2.
9.2.3.
9.2.4.
Link Timing Parameters at the Codec ..................................................................................................................64
S/PDIF Output and Input Timing .........................................................................................................................65
Test Mode..............................................................................................................................................................65
9.3. ANALOG PERFORMANCE ................................................................................................................66
10. Application Notes ...................................................................................................... 67
10.1. STANDARD APPLICATION CIRCUIT .................................................................................................67
10.2. VOLUME CONTROL BY EXTERNAL VARIABLE RESISTOR................................................................70
10.3. VOLUME CONTROL BY GPIO0/GPIO1...........................................................................................70
11. Mechanical Dimensions ............................................................................................ 71
11.1. MECHANICAL DIMENSIONS NOTES.................................................................................................72
12. Ordering Information............................................................................................... 73
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List of Tables
Table 1. Digital I/O Pins ...........................................................................................................................7
Table 2. Analog I/O Pins...........................................................................................................................7
Table 3. Filter/Reference...........................................................................................................................8
Table 4. Power/Ground.............................................................................................................................8
Table 5. Link Signal Definitions.............................................................................................................10
Table 6. HDA Signal Definitions............................................................................................................10
Table 7. Defined Sample Rate and Transmission Rate...........................................................................16
Table 8. 48kHz Variable Rate of Delivery Timing .................................................................................16
Table 9. 44.1kHz Variable Rate of Delivery Timing ..............................................................................17
Table 10. 40-Bit Commands in 4-Bit Verb Format...................................................................................20
Table 11. 40-Bit Commands in 12-Bit Verb Format.................................................................................20
Table 12. Solicited Response Format .......................................................................................................21
Table 13. Unsolicited Response Format ...................................................................................................21
Table 14. System Power State Definitions ...............................................................................................21
Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h ..................................................................22
Table 16. Powered Down Conditions .......................................................................................................22
Table 17. Verb – Get Parameters (Verb ID=F00h) ...................................................................................23
Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)...................................................23
Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ................................................23
Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)............................24
Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) .................................24
Table 22. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h).......................25
Table 23. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) .........................25
Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ......................26
Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) ........................27
Table 26. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..........................................28
Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) .....29
Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...29
Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ..................................30
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .............................30
Table 31. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..............................30
Table 32. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ......................................31
Table 33. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) .........................31
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Table 34. Verb – Get Connection Select Control (Verb ID=F01h)...........................................................32
Table 35. Verb – Set Connection Select (Verb ID=701h).........................................................................32
Table 36. Verb – Get Connection List Entry (Verb ID=F02h)..................................................................33
Table 37. Verb – Get Processing State (Verb ID=F03h)...........................................................................37
Table 38. Verb – Set Processing State (Verb ID=703h)............................................................................37
Table 39. Verb – Get Coefficient Index (Verb ID=Dh).............................................................................38
Table 40. Verb – Set Coefficient Index (Verb ID=5h) ..............................................................................38
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch).....................................................................39
Table 42. Verb – Set Processing Coefficient (Verb ID=4h)......................................................................39
Table 43. Verb – Get Amplifier Gain (Verb ID=Bh) ................................................................................40
Table 44. Verb – Set Amplifier Gain (Verb ID=3h)..................................................................................42
Table 45. Verb – Get Converter Format (Verb ID=Ah)............................................................................43
Table 46. Verb – Set Converter Format (Verb ID=2h)..............................................................................44
Table 47. Verb – Get Power State (Verb ID=F05h) ..................................................................................45
Table 48. Verb – Set Power State (Verb ID=705h)...................................................................................46
Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h)...........................................................47
Table 50. Verb – Get Pin Widget Control (Verb ID=F07h) ......................................................................47
Table 51. Verb – Set Pin Widget Control (Verb ID=707h).......................................................................48
Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h) .....................................................49
Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h) ......................................................49
Table 54. Verb – Get Pin Sense (Verb ID=F09h)......................................................................................50
Table 55. Verb – Execute Pin Sense (Verb ID=709h)...............................................................................50
Table 56. Verb – Get Configuration Default (Verb ID=F1Ch) .................................................................51
Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) ............................................................51
Table 58. Verb – Get BEEP Generator (Verb ID= F0Ah).........................................................................52
Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah)..........................................................................52
Table 60. Verb – Get GPIO Data (Verb ID= F15h) ..................................................................................53
Table 61. Verb – Set GPIO Data (Verb ID= 715h) ...................................................................................53
Table 62. Verb – Get GPIO Enable Mask (Verb ID= F16h).....................................................................54
Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h).......................................................................54
Table 64. Verb – Get GPIO Direction (Verb ID=F17h)............................................................................55
Table 65. Verb – Set GPIO Direction (Verb ID=717h).............................................................................55
Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) ..................................56
Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)...................................56
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Table 68. Verb – Function Reset (Verb ID=7FFh)....................................................................................57
Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)........................57
Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) ..........................59
Table 71. Get/Set Volume Knob Widget (NID=21h) (Verb ID= F0Fh/70Fh) ..........................................60
Table 72. Absolute Maximum Ratings .....................................................................................................61
Table 73. Threshold Voltage .....................................................................................................................61
Table 74. Digital Filter Characteristics.....................................................................................................62
Table 75. S/PDIF Input/Output Characteristics........................................................................................62
Table 76. Link Reset and Initialization Timing ........................................................................................63
Table 77. Link Timing Parameters at the Codec.......................................................................................64
Table 78. S/PDIF Output and Input Timing..............................................................................................65
Table 79. Analog Performance .................................................................................................................66
Table 80. Ordering Information................................................................................................................73
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List of Figures
Figure 1. Block Diagram ..........................................................................................................................4
Figure 2. Analog Input/Output Unit .........................................................................................................5
Figure 3. Pin Assignments........................................................................................................................6
Figure 4. HDA Link Protocol ...................................................................................................................9
Figure 5. Bit Timing ...............................................................................................................................10
Figure 6. Signaling Topology .................................................................................................................11
Figure 7. SDO Outbound Frame.............................................................................................................12
Figure 8. SDO Stream Tag is Indicated in SYNC ..................................................................................12
Figure 9. Stripped Stream on Multiple SDO ..........................................................................................13
Figure 10. SDI Inbound Stream................................................................................................................14
Figure 11. SDI Stream Tag and Data ........................................................................................................14
Figure 12. Codec Transmits Data Over Multiple SDI ..............................................................................15
Figure 13. Link Reset Timing...................................................................................................................19
Figure 14. Codec Initialization Sequence.................................................................................................20
Figure 15. Link Reset and Initialization Timing.......................................................................................63
Figure 16. Link Signals Timing................................................................................................................64
Figure 17. Output and Input Timing.........................................................................................................65
Figure 18. Filter Connection.....................................................................................................................67
Figure 19. IO Connection .........................................................................................................................68
Figure 20. On board Front Panel Header & Front I/O Module Connection.............................................69
Figure 21. Volume Control by External Variable Resistor .......................................................................70
Figure 22. Volume Control by GPIO0 and GPIO1...................................................................................70
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1. General Description
The ALC882 series* 7.1+2 Channel High Definition Audio codecs with UAA (Universal Audio
Architecture), featuring five 24-bit stereo DACs and three 20-bit stereo ADCs, are designed for high
performance multimedia PC systems. The ALC882 series incorporates proprietary converter technology
to achieve over 100dB Signal-to-Noise ratio playback quality; easily meeting PC2001 requirements and
also bringing PC sound quality closer to consumer electronic devices.
The ALC882 series provides 10 channels of DAC that simultaneously support 7.1 sound playback, plus 2
channels of independent stereo sound output (multiple streaming) through the Front-Out-Left and
Front-Out-Right channels. Flexible mixing, mute, and fine gain control functions provide a complete
integrated audio solution for next generation multimedia PCs.
The DACs (with a highest sampling frequency of 192kHz) are applicable for DVD-Audio, previously
only implemented in high-end consumer electronics, and now achieved by PCs with the ALC882 series
inside. The ALC882 series also integrate three stereo ADCs that can support a microphone array with
Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology
simultaneously, significantly improving recording quality for conference calls. With this feature (3 stereo
ADCs), the ALC882 series can provide high-quality audio using S/PDIF to output analog data, or for
multiple-source recording applications.
All analog IO are input and output capable, and headphone amplifiers are also integrated at each analog
output. All analog IOs can be re-tasked according to user’s definitions, or automatically switched
depending on the connected device type.
The ALC882 series supports 16/20/24/32-bit S/PDIF input and output functions for both consumer mode
and professional mode, offering easy connection of PCs to high quality consumer electronic products such
as AC-3 decoders/speakers, and mini disk devices.
The ALC882 series supports host/soft audio from the Intel ICH6/ICH7 chipset, and also from any other
HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent
software utilities such as Karaoke mode, environment emulation, software equalizer, HRTF 3D positional
audio, optional DTS Connect™, and optional Dolby® Digital Live, Home Theatre, and Master Studio
programs, the ALC882 series provides an excellent entertainment package and game experience for PC
users.
*Note: The ALC882 series covers all products listed in section 12 Ordering Information, page 73.
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2. Features
2.1. Hardware Features
High-performance DACs with 103dB SNR are ideal for Dolby® Master Studio
ADCs with 90dBA SNR
Meets performance requirements for audio on PC2001 systems
10 DAC channels support 16/20/24-bit PCM format for 7.1 sound playback, plus 2 channels of
independent stereo sound output (multiple streaming) through the Front-Out-Left and
Front-Out-Right channels
3 stereo ADCs support 16/20-bit PCM format, two for microphone array, one for legacy mixer
recording
All DACs supports 44.1K/48K/96K/192kHz sample rate
All ADCs support 44.1K/48K/96K sample rate
Applicable for DVD-Audio solutions
16/20/24-bit S/PDIF-OUT supports 44.1K/48K/96/192kHz sample rate
16/20/24-bit S/PDIF-IN supports 44.1K/48K/96/192kHz sample rate
Up to four channels of microphone input are supported for AEC/BF application
High-quality analog differential CD input
Supports external PCBEEP input and built-in digital BEEP generator
Software selectable 2.5V/3.75V VREFOUT
Six VREFOUTs are supported by default, with additional four VREFOUTs available by sharing
unused analog I/O pins
Two jack detection pins each designed to detect up to 4 jacks
Reserve analog mixer architecture for backward compatibility with AC'97
Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain
All analog jacks are stereo input and output re-tasking for analog plug & play
Built-in headphone amplifiers for each re-tasking jack
Supports both analog DC volume control and GPI digital volume control
2 GPIOs (General Purpose Input/Output) for customized applications
Optional EAPD (External Amplifier Power Down) is supported
Power support: Digital: 3.3V; Analog: 5.0V (Minimum AVDD is 3.6V)
Power management and enhanced power saving features
48-pin LQFP lead (Pb)-free package
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2.2. Software Features
Meets Microsoft WHQL/WLP 2.0 audio requirements
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
HRTF 3D Positional Audio
Emulation of 26 sound environments to enhance gaming experience
10 Software Equalizer Bands
Voice Cancellation and Key Shifting in Karaoke mode
Realtek Media Player
Enhanced Configuration Panel and device sensing wizard to improve user experience
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS) and Beam Forming (BF)
technology for voice application
ALC882D features Dolby® Digital Live output for consumer equipment
ALC882H features Dolby® Home Theater software
ALC882M features Dolby® Master Studio software
ALC882DTS features DTS® Connect™ software
3. System Applications
Multimedia PCs
3D PC games
Information appliances (IA)
Voice recognition
Audio conferencing
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4. Block Diagram
Figure 1. Block Diagram
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4.1. Analog Input/Output Unit
Pin Complex widgets NID=14h~1Bh are re-tasking IO.
Left
A
R
EN_OBUF
EN_AMP
Right
R
Output_Signal_Left
Output_Signal_Right
Input_Signal_Left
Input_Signal_Right
EN_OBUF
EN_IBUF
Figure 2. Analog Input/Output Unit
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5. Pin Assignments
36 35 34 33 32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
16
15
14
PIN37-VREFO-R
37
LINE1-R (PORT-C-R)
LINE1-L (PORT-C-L)
MIC1-R (PORT-B-R)
MIC1-L (PORT-B-L)
CD-R
CD-GND
CD-L
MIC2-R (PORT-F-R)
MIC2-L (PORT-F-L)
LINE2-R (PORT-E-R)
LINE2-L (PORT-E-L)
Sense A (JD1)
38
39
40
41
42
43
44
45
46
47
48
AVDD2
(PORT-A-L) SURR-OUT-L
JDREF
(PORT-A-R) SURR-OUT-R
AVSS2
ALC882 Series
(PORT-G-L) CEN-OUT
(PORT-G-R) LFE-OUT
(PORT-H-L) SIDESURR-OUT-L
(PORT-H-R) SIDESURR-OUT-R
SPDIFI/EAPD
LLLLLLL
TXXXVV
13
SPDIFO
1
2 3 4 5 6 7 8 9 10 11 12
0
Figure 3. Pin Assignments
5.1. Lead (Pb)-Free Package and Version Identification
Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 3. The version number
is shown in the location marked ‘VV’.
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Type Pin No. Description Characteristic Definition
TTL input, VIL=1.0V, VIH=2.0V
Name
RESET#
SYNC
I
I
11
10
6
H/W reset
Sample Sync (48kHz)
24MHz Bit clock input
Serial TDM data input
Serial TDM data output
S/PDIF Input /
Schmitt trigger input, VIL=1.0V, VIH=2.0V
Schmitt trigger input, VIL=1.0V, VIH=2.0V
TTL input, VIL=1.0V, VIH=2.0V
BITCLK
SDATA-OUT
SDATA-IN
SPDIFI /
EAPD
I
I
5
O
I/O
8
TTL output, VOH=0.9*DVDD, VOL=0.1*DVDD
Schmitt input (VIL=1.45V, VIH=1.85V) /
TTL output
47
Signal to power down ext. amp
S/PDIF output
SPDIFO
GPIO0
O
48
2
TTL output has 12mA@75Ω driving capability.
I/O
I/O
General Purpose Input/Output 0 Schmitt input/output, VIL=1.45V, VIH=1.85V
General Purpose Input/Output 1 Schmitt input/output, VIL=1.45V, VIH=1.85V
Total: 9 Pins
GPIO1
3
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Type Pin No. Description Characteristic Definition
Analog input/output, default is input (JACK-E)
2nd line input right channel Analog input/output, default is input (JACK -E)
nd stereo microphone input Analog input/output, default is input (JACK -F)
left channel
nd stereo microphone input Analog input/output, default is input (JACK -F)
Name
LINE2-L
LINE2-R
MIC2-L
IO
IO
IO
14
15
16
2nd line input left channel
2
MIC2-R
IO
17
2
right channel
CD-L
I
I
18
19
20
21
CD input left channel
Analog input, 1.6Vrms of full scale input
CD-G
CD-R
MIC1-L
CD input reference ground Analog input, 1.6Vrms of full scale input
I
CD input right channel
Analog input, 1.6Vrms of full scale input
IO
1st stereo microphone input Analog input/output, default is input (JACK -B)
left channel
MIC1-R
IO
22
1st stereo microphone input Analog input/output, default is input (JACK -B)
right channel
LINE1-L
LINE1-R
PCBEEP
FRONT-
IO
IO
I
23
24
12
35
1st line input left channel
1st line input right channel
External PCBEEP input
Front output left channel
Analog input/output, default is input (JACK -C)
Analog input/output, default is input (JACK -C)
Analog input, 1.6Vrms of full scale input
Analog output (JACK -D)
IO
OUT-L
FRONT-
IO
36
Front output right channel
Analog output (JACK -D)
OUT-R
SURR-OUT-L
SURR-OUT-R
IO
IO
39
41
Surround out left channel
Analog output (JACK -A)
Surround out right channel Analog output (JACK -A)
Track ID: JATR-1076-21 Rev. 1.5
7.1+2 Channel High Definition Audio Codec
7
ALC882 Series
Datasheet
Name
Type Pin No. Description
Characteristic Definition
Analog output (JACK -G)
Analog output (JACK -G)
Analog output (JACK -H)
CEN-OUT
LFE-OUT
SIDESURR-
OUT-L
O
O
O
43
44
45
Center output
Low Frequency output
Side Surround output left
channel
SIDESURR-
OUT-R
O
46
Side Surround output right Analog output (JACK -H)
channel
Sense A
I
I
I
13
34
33
Jack Detect pin l
Jack Detect pin 2
Jack resistor network input 1
Jack resistor network input 2
Sense B
DCVOL
DC sense for volume
control
Analog DC input for external volume control
Total: 23 Pins
6.3. Filter/Reference
Table 3. Filter/Reference
Type Pin No. Description
Name
Characteristic Definition
10uf capacitor to analog ground
2.5V/3.75Vreference voltage
2.5V/3.75Vreference voltage
2.5V/3.75Vreference voltage
2.5V/3.75Vreference voltage
VREF
-
27
28
29
30
31
32
2.5V Reference voltage
MIC1-VREFO-L
LINE1-VREFO
MIC2-VREFO
LINE2-VREFO
O
O
O
O
O
Bias voltage for MIC1 jack
Bias voltage for LINE1 jack
Bias voltage for MIC2 jack
Bias voltage for LINE2 jack
MIC1-VREFO-R
(PIN32-VREFO)
Bias voltage for MIC1 jack or 2.5V/3.75Vreference voltage
software select specific jack
LINE1-VREFO-R
(PIN37-VREFO)
O
-
37
40
Bias voltage for LINE1 jack or 2.5V/3.75Vreference voltage
software select specific jack
JDREF
Reference resistor for Jack
detection
20K, 1% external resistor to analog ground
Total: 8 Pins
6.4. Power/Ground
Table 4. Power/Ground
Type Pin No Description Characteristic Definition
Analog VDD (5V or 3.3V) Analog power for mixer and amplifier
Analog GND Analog ground for mixer and amplifier
Analog VDD (5V or 3.3V) Analog power for DACs and ADCs
Name
AVDD1
AVSS1
AVDD2
AVSS2
DVDD1
DVSS1
DVDD2
DVSS2
I
I
I
I
I
I
I
I
25
26
38
42
1
Analog GND
Analog ground for DACs and ADCs
Digital power
Digital VDD (3.3V)
Digital GND
4
Digital ground
9
Digital VDD (3.3V)
Digital GND
Digital power
7
Digital ground
Total: 8 Pins
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ALC882 Series
Datasheet
7. High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
T
= 20.833 µs (48KHz)
frame_sync
Previous Frame
BCLK
Next Frame
Frame SYNC= 8 BCLK
Stream 'A' Tag
(Here 'A' = 5)
Stream 'B' Tag
(Here 'B' = 6)
SYNC
SDO
SDI
Command Stream
(40-bit data)
Stream 'B' Data
Stream 'A' Data
Stream
'C' Tag
Stream 'C' Data
Response Stream
(36-bit data)
(n bytes + 10-bit data)
RST#
Figure 4. HDA Link Protocol
7.1+2 Channel High Definition Audio Codec
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Datasheet
7.1.1. Signal Definitions
Table 5. Link Signal Definitions
Item
Description
24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.
BCLK
SYNC
48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported.
SDI
Serial data input signal driven by the codec. It is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Table 6. HDA Signal Definitions
Signal Name Source
Controller Type
Output
Description
BCLK
SYNC
SDO
Controller
Global 24.0MHz bit clock
Controller
Output
Global 48kHz Frame Sync and outbound tag signal
Serial data output from controller
Controller
Output
SDI
Codec/Controller
Input/Output
Serial data input from codec. Weakly pulled down by the
controller
RST#
Controller
Output
Global active low reset signal
BCLK
8-Bit Frame SYNC
SYNC
Start of Frame
7
6
5
4
3
2
1
0
999 998 997 996995 994 993 992 991 990
SDO
SDI
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK
Controller samples SDI at rising edge of BCLK
Figure 5. Bit Timing
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
7.1.2. Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 6 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 12 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 6 can be implemented concurrently in an HDA system. The ALC882
series is designed to receive a single SDO stream.
SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA
Controller
SDI1
SDI0
SDO1
SDO0
SYNC
BCLK
RST#
. . .
Codec 0
Codec 1
Codec 2
Codec N
Single SDO
Single SDI
Two SDOs
Single SDI
Single SDO
Two SDIs
Two SDOs
Multiple SDIs
Figure 6. Signaling Topology
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Datasheet
7.2. Frame Composition
7.2.1. Outbound Frame – Single SDO
An outbound frame is composed of one 32-Bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be two blocks in the same stream to carry
96kHz samples (Figure 7).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-Bit preamble and 4-Bit stream ID (Figure 8).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
A 48kHz Frame is composed of Command stream and multiple Data streams
Previous Frame
Next Frame
Frame SYNC
Stream 'A' Tag
(Here 'A' = 5)
Stream 'X' Tag
(Here 'X' = 6)
SYNC
SDO
Command Stream
0s
Stream 'A' Data
Stream 'X' Data
Padded at the
end of Frame
Null Field
One or multiple blocks in a stream
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples
..
.
Block 1
Block 2
Block Y
..
.
Sample 1 Sample 2
Sample Z
Z channels of PCM Sample
...
msb first in a sample
msb
lsb
Figure 7. SDO Outbound Frame
BCLK
SYNC
Stream Tag
msb lsb
1 0 1 0
Stream=10
(4-Bit)
Preamble
(4-Bit)
Data of Stream 10
7 6 5 4 3 2 1 0
Previous Stream
SDO
Figure 8. SDO Stream Tag is Indicated in SYNC
7.1+2 Channel High Definition Audio Codec 12 Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
7.2.2. Outbound Frame – Multiple SDO
The HDA controller allows two SDO signals to be used to strip outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the ‘Strip Control’ bit in the controller’s Output Stream Control Register to initiate a
specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a stripped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not stripped. It
is always transmitted on SDO0, and copied on SDO1.
Stream 'A' Tag
Stream 'X' Tag
Stream 'Y' Tag
SYNC
Frame SYNC
Command Stream
Stream 'A' to Codec A
. . .
SDO
0
Stream 'X' to Codec X
Stream 'Y' to Codec Y
D
D
n
n-2
. . .
SDO
1
0s
Command Stream
0s
. . .
D
D
n-3
n-1
Stream A is "bit-stripped" on SDO0 and SDO1
Command Stream is unchanged, not stripped
Figure 9. Stripped Stream on Multiple SDO
7.1+2 Channel High Definition Audio Codec
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ALC882 Series
Datasheet
7.2.3. Inbound Frame – Single SDI
An Inbound Frame – Single SDI is composed of one 36-Bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each
rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 10).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-Bit stream tag, one 6-Bit data length, and n-Bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 11).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Previous Frame
Frame SYNC
Next Frame
SYNC
SDI
0s
Stream 'X'
Response Stream
Stream 'A'
Null Field
Padded at the end of Frame
Stream Tag
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
...
Block Y Null Pad
Block 1
Block 2
Sample 1 Sample 2
msb ...
...
Sample Z Z channels of PCM Sample
lsb msb first in a sample
Figure 10. SDI Inbound Stream
BCLK
SDI
n-Bit Sample Block
Null Pad
Next Stream
Stream Tag
Data Length in Bytes
B5 B4 B3 B2 B1
B8
Dn-1 Dn-2
0
0
B9
B7 B6
B0
D0
0
0
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 11. SDI Stream Tag and Data
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ALC882 Series
Datasheet
7.2.4. Inbound Frame – Multiple SDI
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI
Tag A
Data A
Response Stream
Stream 'X'
0s
Stream 'Y'
0s
0
Stream 'B'
Data B
SDI
Tag B
Response Stream
1
Stream A, B, X, and Y are independent and have separate IDs
Codec drives SDI0 and SDI1
Figure 12. Codec Transmits Data Over Multiple SDI
7.2.5. Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 16, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 16, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames. The cadence
“12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)”
interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term
frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this
cadence AND interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain
n sample blocks in the non-empty frame AND interleave an empty frame between non-empty
frames (Table 9, page 17).
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Datasheet
Table 7. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base 44.1kHz Base
1/6
1/4
1/3
1/2
2/3
1
8kHz (1 sample block every 6 frames)
12kHz (1 sample block every 4 frames)
16kHz (1 sample block every 3 frames)
11.025kHz (1 sample block every 4 frames)
22.05kHz (1 sample block every 2 frames)
32kHz (2 sample blocks every 3 frames)
48kHz (1 sample block per frame)
96kHz (2 sample blocks per frame)
192kHz (4 sample blocks per frame)
44.1kHz (1 sample block per frame)
88.2kHz (2 sample blocks per frame)
176.4kHz (4 sample blocks per frame)
2
4
Table 8. 48kHz Variable Rate of Delivery Timing
Rate
8kHz
Delivery Cadence
YNNNNN (repeat)
YNNN (repeat)
YNN (repeat)
Y2NN (repeat)
Y (repeat)
Description
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 4 frames
One sample block is transmitted in every 3 frames
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 6 frames
Two sample blocks are transmitted in each frame
Four sample blocks are transmitted in each frame
12kHz
16kHz
32kHz
48kHz
96kHz
192kHz
Y2 (repeat)
Y4 (repeat)
N: No sample block in a frame
Y: One sample block in a frame
Yx: X sample blocks in a frame
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Datasheet
Table 9. 44.1kHz Variable Rate of Delivery Timing
Delivery Cadence
Rate
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - } =NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz
88.2kHz
174.4kHz
12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.
122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.
124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.
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Datasheet
7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (for example, hot docking a codec to an HDA system)
7.3.1. Link Reset
A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 13, page 19, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)
Enter ‘Link Reset’:
n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
o As the controller completes the current frame, it does not signal the normal 8-Bit frame SYNC at the
end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
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Datasheet
Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
t Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
100µs provides time for the codec PLL to stabilize)
u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
>=100 usec >= 4 BCLK
Initialization Sequence
Previous Frame
4 BCLK
4 BCLK
Link in Reset
BCLK
SYNC
SDOs
SDIs
Normal Frame
SYNC
Normal Frame
SYNC is absent
Driven Low
Pulled Low
2
8
Driven Low
Driven Low
Pulled Low
Pulled Low
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 13. Link Reset Timing
7.3.2. Codec Reset
A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
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Datasheet
7.3.3. Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
o The codec will stop driving the SDI during this turnaround period
pqrs The controller drives SDI to assign a CAD to the codec
t The controller releases the SDI after the CAD has been assigned
u Normal operation state
Turnaround Frame
(Non-48kHz Frame)
Address Frame
(Non-48kHz Frame)
Exit from Reset Connection Frame
Normal Operation
BCLK
Frame SYNC
SYNC
Frame SYNC
Frame SYNC
5
4
6
Response
SDIx
SD14
SD0 SD1
3
1
2
7
8
RST#
Codec
Drives SDIx
Codec
Controller Drives SDIx
Controller
Codec Drives SDIx
Turnaround
(477 BCLK
Max.)
Turnaround
(477 BCLK
Max.)
Figure 14. Codec Initialization Sequence
7.4. Verb and Response Format
7.4.1. Command Verb Format
There are two types of verbs: one with 4-Bit identifiers (4-Bit verbs) and 16-Bits of data, the other with
12-Bit identifiers (12-Bit verbs) and 8-Bits of data. Table 10 shows the 4-Bit verb structure of a command
stream sent from the controller to operate the codec. Table 11 is the 12-Bit verb structure that gets and
controls parameters in the codec.
Table 10. 40-Bit Commands in 4-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 11. 40-Bit Commands in 12-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
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7.4.2. Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-Bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 12. Solicited Response Format
Bit [35]
Bit [34]
Bit [33:32]
Bit [31:0]
Valid
Unsol=0
Reserved
Response
Table 13. Unsolicited Response Format
Bit [35]
Valid
Bit [34]
Unsol=1
Bit [33:32]
Bit [31:28]
Tag
Bit [27:0]
Response
Reserved
Note: The response stream in the link protocol is 36-Bits wide. The response is placed in the lower
32-bit field. Bit-35 is a ‘Valid’bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that
an unsolicited response was sent.
7.5. Power Management
The ALC882 series does not support Wake-Up events when in low power mode. All power management
state changes in widgets are driven by software. Table 14 shows the System Power State Definitions.
In the ALC882 series, all the widgets, including output/input converters, support power control. Software
may have various power states depending on system configuration. Table 15 indicates those nodes that
support power management. To simplify power control, software can configure whole codec power states
through the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no
individual power control to supply fine-grained power control.
Table 14. System Power State Definitions
Power States Definitions
D0
D1
All power on. Individual DACs and ADCs can be powered up or down as required
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference
stays up
D2
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference is off (D1 + analog reference off)
D3 (Hot)
Power still supplied. The codec stops the internal clock. State is maintained
All power removed. State lost
D3 (Cold)
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Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h
Item
Audio Function
(NID=01h)
Description
LINK Response
D0
D1
Normal
PD
D2
Normal
PD
D3
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Link Reset
PD
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Front DAC
Surr DAC)
PD
PD
PD
PD
Cen/Lfe DAC
Side DAC
PD
PD
PD
PD
PD
PD
Fout DAC
PD
PD
PD
MIC ADC
PD
PD
PD
LINE ADC
PD
PD
PD
MIX ADC
PD
PD
PD
All Headphone Drivers
All Mixers
Normal
Normal
Normal
PD
Normal
Normal
Normal
PD
All Reference
PD
Note: PD=Powered Down
Table 16. Powered Down Conditions
Condition
Description
LINK Response powered down
Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with
pulled low 47K resistors internally. S/PDIF-IN is also floated. Detection of
‘Link Reset Entry’ and ‘Link Reset Exit’ sequences are supported. All
states are maintained if DVDD is supplied
Front DAC powered down
Surr DAC powered down
CEN/LFE DAC powered down
SIDESURR DAC powered down
Fout DAC powered down
MIC ADC powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
LINE ADC powered down
MIX ADC powered down
Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
Headphone Driver powered down
Mixers powered down
All headphone drivers are powered down
All internal mixer widgets are powered down. The DC reference and
VREFOUTx at individual pin complexes are still alive
Reference power down
All internal references, DC reference, and VREFOUTx at individual pin
complexes are off
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8. Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC882 series. If a
verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget,
some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
page 20, to get detailed information about supported parameters.
Table 17. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=00h Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
31:16
15:0
Description
Vendor ID=10ECh (Realtek’s PCI vendor ID)
Device ID=0882h
Note: The Root Node (NID=00h) supports this parameter.
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s
MajRev. The major version number (in decimal) of the HDA Spec to which the ALC882 series is fully
compliant
19:16
15:8
7:0
MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC882 series is fully
compliant
Revision ID. The vendor’s revision number.
00h is for the first silicon version, 01h is for the second version, etc.
Stepping ID. The vendor’s stepping number within the given Revision ID
Note: The Root Node (NID=00h in the ALC882 series) supports this parameter.
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8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h,
Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.
For function group nodes, it provides the total number of widgets associated with this function node.
Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24
23:16
Reserved. Read as 0’s
Starting Node Number
The starting node number in the sequential widgets
Reserved. Read as 0’s
15:8
7:0
Total Number of Nodes
For a root node, the total number of function groups in the root node
For a function group, the total number of widget nodes in the function group
8.1.4. Parameter – Function Group Type (Verb ID=F00h,
Parameter ID=05h)
Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
31:8
7:0
Description
Reserved. Read as 0’s
Function Group Type
00h: Reserved
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function
Note: The Audio Function Group (NID=01h) supports this parameter.
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8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h,
Parameter ID=08h)
Table 22. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
31:17
16
Description
Reserved. Read as 0’s
Beep Generator
A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group
15:12
11:8
7:4
Reserved. Read as 0’s
Input Delay
Reserved. Read as 0’s
Output Delay
3:0
Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h,
Parameter ID=09h)
Table 23. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s
Widget Type
0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex
5h: Power Widget 6h: Volume Knob Widget
7h~Eh: Reserved
Fh: Vendor defined audio widget
19:16
15:11
10
Delay. Samples delayed between the HDA link and widgets
Reserved. Read as 0’s
Power Control
0: Power state control is not supported on this widget
1: Power state is supported on this widget
Digital
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.)
ConnList. Connection List
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
UnsolCap. Unsolicited Capable
0: Unsolicited response is not supported
1: Unsolicited response is supported
ProcWidget. Processing Widget
9
8
7
6
0: No processing control
1: Processing control is supported
5
4
3
Reserved. Read as 0
Format Override
AmpParOvr, AMP Param Override
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Codec Response Format
Bit Description
2
1
0
OutAmpPre. Out AMP Present
InAmpPre. In AMP Present
Stereo
0: Mono Widget
1: Stereo Widget
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h,
Parameter ID=0Ah)
Parameter in audio function provides default information about formats. Individual converters have their
own parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
31:21
20
Description
Reserved. Read as 0’s
B32. 32-Bit audio format support
0: Not supported
1: Supported
19
18
17
16
B24. 24-bit audio format support
0: Not supported
1: Supported
B20. 20-bit audio format support
0: Not supported
1: Supported
B16. 16-bit audio format support
0: Not supported
1: Supported
B8. 24-bit audio format support
0: Not supported
1: Supported
15:12
11
Reserved. Read as 0’s
R12. 384kHz (=8*48kHz) rate support
0: Not supported
1: Supported
10
9
R11. 192kHz (=4*48kHz) rate support
0: Not supported
1: Supported
R10. 176.4kHz (=4*44.1kHz) rate support
0: Not supported
1: Supported
8
R9. 96kHz (=2*48kHz) rate support
0: Not supported
1: Supported
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Codec Response Format
Bit
Description
7
R8. 88.2kHz (=2*44.1kHz) rate support
0: Not supported
1: Supported
6
5
4
3
2
1
0
R7. 48kHz rate support
0: Not supported
1: Supported
R6. 44.1kHz rate support
0: Not supported
1: Supported
R5. 32kHz (=2/3*48kHz) rate support
0: Not supported
1: Supported
R4. 22.05kHz (=1/2*44.1kHz) rate support
0: Not supported
1: Supported
R3. 16kHz (=1/3*48kHz) rate support
0: Not supported
1: Supported
R2. 11.025kHz (=1/4*44.1kHz) rate support
0: Not supported
1: Supported
R1. 8kHz (=1/6*48kHz) rate support
0: Not supported
1: Supported
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h,
Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
31:3
2
Description
Reserved. Read as 0’s
AC3
0: Not supported
1: Supported
Float32
0: Not supported
1: Supported
PCM
1
0
0: Not supported
1: Supported
Note: Input converters and output converters support this parameter.
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8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 26. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
31:16
15:8
Description
Reserved. Read as 0’s
VREF Control Capability
‘1’ in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of
AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
L-R Swap. Indicates the capability of swapping the left and rights
Balanced I/O Pin
‘1’ indicates this pin complex has balanced pins
Input Capable
‘1’ indicates this pin complex supports input
Output Capable
‘1’ indicates this pin complex supports output
Headphone Drive Capable
‘1’ indicates this pin complex has an amplifier to drive a headphone
Presence Detect Capable
‘1’ indicates this pin complex can detect whether there is anything plugged in
Trigger Required
‘1’ indicates whether a software trigger is required for an impedance measurement
Impedance Sense Capable
5
4
3
2
1
0
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type
Note: Only Pin Complex widgets support this parameter.
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8.1.10. Parameter – Amplifier Capabilities
(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
31
Description
(Input) Mute Capable
30:23
22:16
Reserved. Read as 0
Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
15
Reserved. Read as 0
14:8
Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
7
Reserved. Read as 0
Offset
6:0
Indicates which step is 0dB
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output
Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
31
Description
(Output) Mute Capable
30:23
22:16
Reserved. Read as 0
Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
Reserved. Read as 0
15
14:8
Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
Reserved. Read as 0
7
6:0
Offset. Indicates which step is 0dB
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8.1.12. Parameter – Connect List Length (Verb ID=F00h,
Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0
Short Form
0: Short Form
1: Long Form
6:0
Connect List Length
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (Not a MUX widget)
8.1.13. Parameter – Supported Power States (Verb ID=F00h,
Parameter ID=0Fh)
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
31:4
3
Description
Reserved. Read as 0’s
D3Sup
1: Power state D3 is supported
D2Sup
1: Power state D2 is supported
D1Sup
1: Power state D1 is supported
D0Sup
2
1
0
1: Power state D0 is supported
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h,
Parameter ID=10h)
Table 31. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
31:16
15:8
7:1
Description
Reserved. Read as 0’s
NumCoeff. Number of Coefficient
Reserved. Read as 0’s
0
Benign
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant
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8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h,
Parameter ID=11h)
Table 32. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
Description
31
GPIWake=0
The ALC882 series does not support GPIO wake up function
GPIUnsol=1
30
The ALC882 series supports GPIO unsolicited response
Reserved. Read as 0’s
29:24
23:16
NumGPIs=00h
No GPI pin is supported
NumGPOs=00h
No GPO pin is supported
NumGPIOs=02h
15:8
7:0
Two GPIO pins are supported
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h,
Parameter ID=13h)
Table 33. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit
31:8
7
Description
Reserved. Read as 0’s
Delta
0: Software cannot modify the Volume Control Knob volume
1: Software can write a base volume to the Volume Control Knob
NumSteps
6:0
The number of steps in the range of the Volume Control Knob
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8.2. Verb – Get Connection Select Control (Verb ID=F01h)
Table 34. Verb – Get Connection Select Control (Verb ID=F01h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for Analog Port-A/B/C/D/E/F/G/H
Bit
31:8
7:0
Description
0’s
Connection Index currently Set (Default value is 00h)
00h: Sum Widget NID=0Ch
01h: Sum Widget NID=0Dh
02h: Sum Widget NID=0Eh
03h: Sum Widget NID=0Fh
04h: Sum Widget NID=26h
Other: Reserved
Codec Response for Digital Pin S/PDIF-OUT
Bit
31:8
7:0
Description
0’s
Connection Index currently Set (Default value is 00h)
00h: Digital Converter (S/PDIF-OUT)
01h: Pin Widget (S/PDIF-IN)
Other: Reserved
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.3. Verb – Set Connection Select (Verb ID=701h)
Table 35. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=701h
Select Index [7:0]
0’s for all nodes
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8.4. Verb – Get Connection List Entry (Verb ID=F02h)
Table 36. Verb – Get Connection List Entry (Verb ID=F02h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F02h
Offset Index - N[7:0]
32-bit Response
Codec Response for NID=07h (MIC ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 24h (Sum Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=08h (LINE ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 23h (Sum Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=09h (MIX ADC)
Bit
Description
15:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 22h (Sum Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Ah (S/PDIF-IN Converter)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3
Returns 00h for N>3
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Codec Response for NID=0Bh (Mixer)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
23:16
15:8
Connection List Entry (N+2)
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Returns 00h for N>7
Connection List Entry (N+1)
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11
Returns 00h for N>11
7:0
Connection List Entry (N)
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Returns 00h for N>11
Codec Response for NID=0Ch (Front Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 02h (Front DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Dh (Surround Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
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Codec Response for NID=0Dh (Surround Sum)
Bit
Description
7:0
Connection List Entry (N)
Returns 03h (Surround DAC) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Eh (Cen/Lfe Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 04h (Cen/Lfe DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Fh (Side-Surr Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 05h (Front DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=26h (Fout Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7.1+2 Channel High Definition Audio Codec
35
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
Codec Response for NID=26h (Fout Sum)
Bit
7:0
Description
Connection List Entry (N)
Returns 25h (Fout1 DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=14h~1Bh (Port-A to port-H)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 0Fh (Sum Widget NID=0Fh) for N=0~3
Returns 00h for n>3
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3
Returns 00h for N>3
Connection List Entry (N+1)
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3
Returns 00h for N>3
Connection List Entry (N)
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3
Returns 26h (Sum Widget NID=26h) for N=4~7
Returns 00h for N>7
Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT)
Bit
Description
31:16
Connection List Entry (N+3) and (N+2)
Returns 0000h
15:8
7:0
Connection List Entry (N+1)
Returns 1Fh (Pin Widget S/PDIF-IN) for N=0~3
Returns 00h for N>3
Connection List Entry (N)
Returns 06h (S/PDIF-OUT converter) for N=0~3
Returns 00h for N>3
Codec Response for NID= 22h/23h/24h (Sum Widget before MIX/LINE/MIC ADCs)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
23:16
Connection List Entry (N+2)
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Returns 0Bh (Sum Widget) for N=8~11
Returns 00h for N>11
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
Codec Response for NID= 22h/23h/24h (Sum Widget before MIX/LINE/MIC ADCs)
Bit
Description
15:8
Connection List Entry (N+1)
Returns 19h (Pin Complex – MIC2) for N=0~3
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11
Returns 00h for N>11
7:0
Connection List Entry (N)
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Returns 00h for N>11
Codec Response for Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.5. Verb – Get Processing State (Verb ID=F03h)
Table 37. Verb – Get Processing State (Verb ID=F03h)
Get Command Format
Codec Response Format
Response [31:0]
32-bit response
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F03h
0’s
Codec Response for All NID
Bit
Description
Not supported (returns 00000000h)
31:0
8.6. Verb – Set Processing State (Verb ID=703h)
Table 38. Verb – Set Processing State (Verb ID=703h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=703h
Processing State [7:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec
37
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.7. Verb – Get Coefficient Index (Verb ID=Dh)
Table 39. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=Dh
0’s
Bit [15:0] are Coefficient Index
Codec Response for NID=20h (Realtek Defined Hidden Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s
Coefficient Index
Codec Response for Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.8. Verb – Set Coefficient Index (Verb ID=5h)
Table 40. Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=5h
Coefficient Index [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec
38
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.9. Verb – Get Processing Coefficient (Verb ID=Ch)
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch)
Get Command Format
Codec Response Format
Response [31:0]
Processing Coefficient [15:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ch
0’s
Codec Response for NID=20h (Realtek Defined Hidden Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s
Processing Coefficient
Codec Response for Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.10. Verb – Set Processing Coefficient (Verb ID=4h)
Table 42. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=4h
Coefficient [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec
39
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.11. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 43. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=Bh
‘Get’ payload [15:0]
Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output
0: Input amplifier gain is requested
1: Output amplifier gain is requested
Reserved. Read as 0.
14
13
Get Left/Right
0: Right amplifier gain is requested
1: Left amplifier gain is requested
Reserved. Read as 0’s
12:4
3:0
Index[3:0] for Input Source
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored
Codec Response for NID=07h (MIC ADC), 08h(LINE ADC) and 09h (MIX ADC)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute, 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0. (No Output Amplifier Mute)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the
volume from –16.5B~+30dB in 1.5dB steps
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)
Codec Response for NID=0Bh (MIXER Sum Widget)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute 1: Mute (Default for all Index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0. (No Output Amplifier Mute)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the
volume from –34.5dB~+12dB in 1.5dB steps
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, Cen/Lfe, SIDESURR Sum)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute, 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute)
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. (No Input Amplifier Gain)
6:0
Bit-15 is 1 in ‘Get Amplifier Gain’:Output Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the
volume from –46.5dB~0dB in 1.5dB steps
Codec Response for NID=14h~1Bh (Pin Complex: Front/Surr/CenLfe/SIDESURR/MIC1/MIC2/LINE1/LINE2)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute, 0:Unmute, 1:Mute
(NID=14h~1Bh,Default=1)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0’s
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain)
Codec Response to Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec
41
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.12. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 44. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=3h
‘Set’ payload [7:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
Description
15
Set Output Amp
1 indicates output amplifier gain will be set
Set Input Amp
1 indicates input amplifier gain will be set
Set Left Amp
14
13
1 indicates left amplifier gain will be set
Set Right Amp
12
1 indicates right amplifier gain will be set
Index Offset (for input amplifiers on Sum widgets and Selector Widgets)
11:8
5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is
not set
7
Mute
0: Unmute
1: Mute (-∞ gain)
6:0
Gain[6:0]
A 7-bit step value specifying the amplifier gain
7.1+2 Channel High Definition Audio Codec
42
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.13. Verb – Get Converter Format (Verb ID=Ah)
Table 45. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format
Codec Response Format
Response [31:0]
Bit[15:0] are converter format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ah
0’s
Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/Lfe, Side-Surr, Fout DAC, S/PDIF-OUT).
Codec Response for NID=07h~0Ah (Input Converters: MIC, LINE, UIO1, UIO2, MIX DAC, and S/PDIF-IN)
Bit
31:16
15
Description
Reserved. Read as 0
Stream Type (TYPE)
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE)
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5
The ALC882 series does not support Divisor. Always read as 000b
Reserved. Read as 0.
101b: /6 110b: /7 111b: /8
7
6:4
Bits per Sample (BITS)
000b: 8 bits
001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: reserved
3:0
Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels ….. 15: 16 channels
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec
43
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.14. Verb – Set Converter Format (Verb ID=2h)
Table 46. Verb – Set Converter Format (Verb ID=2h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=2h
Set format [15:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
31:16
15
Description
Reserved. Read as 0
Stream Type (TYPE)
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE)
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5
Reserved. Read as 0
101b: /6 110b: /7 111b: /8
7
6:4
Bits per Sample (BITS)
000b: 8 bits
001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved
3:0
Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels …..… 15: 16 channels
7.1+2 Channel High Definition Audio Codec
44
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.15. Verb – Get Power State (Verb ID=F05h)
Table 47. Verb – Get Power State (Verb ID=F05h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=Ah
0’s
Power State [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:6
5:4
Description
Reserved. Read as 0’s
PS-Act. Actual Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set
3:2
1:0
Reserved. Read as 0’s
PS-Set, Set Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Set controls the current power setting of the referenced node
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec
45
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.16. Verb – Set Power State (Verb ID=705h)
Table 48. Verb – Set Power State (Verb ID=705h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=705h
Power State [7:0]
0’s for all nodes
‘Power State’ in Command Bit[7:0]
Bit
7:6
5:4
Description
Reserved. Read as 0’s
PS-Act. Actual Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node.
Reserved. Read as 0’s
3:2
1:0
PS-Set. Set Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
8.17. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/Lfe, Side-Surr, Fout DAC, S/PDIF-OUT)
Codec Response for NID=07h~0Ah (Input Converters: MIC ADC, LINE ADC, MIX DAC, and S/PDIF-IN)
Bit
31:8
7:4
Description
Reserved. Read as 0’s
Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Channel[3:0]
3:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec
46
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.18. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h)
Codec Response Format
Set Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=706h
Stream & Channel [7:0]
0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
31:8
7:4
Description
Reserved. Read as 0’s
Set Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Set Channel[3:0]
1:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel
Note: This verb assigns stream and channel for output converters (NID=02h~06h, 25h) and input converters
(NID=07h~0Ah). Other widgets will ignore this verb.
8.19. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 50. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F07h
0’s
Pin Control [7:0]
Codec Response for NID=14h~1Bh
(Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, and LINE2)
Bit
31:1
7
Description
Reserved. Read as 0’s
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit)
0: Disabled
1: Enabled
6
5
Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
0: Disabled
1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
Reserved
4:
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
Codec Response for NID=14h~1Bh
(Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, and LINE2)
Bit
Description
2:0
VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD
101b: 100% of AVDD
110b~111b: Reserved
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.20. Verb – Set Pin Widget Control (Verb ID=707h)
Table 51. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=707h
Pin Control [7:0]
‘Pin Control’ in command [7:0]: (Pin: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, and LINE2)
Bit
31:1
7
Description
Reserved. Read as 0’s
H-Phn Enable
0: Disabled
1: Enabled
6
5
Out Enable
0: Disabled
1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
4:
Reserved
2:0
VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD)
101b: 100% of AVDD
110b~111b: Reserved
7.1+2 Channel High Definition Audio Codec
48
Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.21. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real-time event.
Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F08h
0’s
32-bit Response
Codec Response for NID=01h (GPIO), 0Ah (S/PDIF-IN), 14h~1Bh (Port), 21h (Volume in Step)
Bit
31:8
7
Description
Reserved. Read as 0’s
Unsolicited Response is Enabled
0: Disabled
1: Enabled
6:4
3:0
Reserved. Read as 0’s
Assigned Tag for Unsolicited Response
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.22. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enable a widget to generate an unsolicited response.
Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=708h
EnableUnsol [7:0]
0’s for all nodes
‘EnableUnsol’ in Command Bit[7:0]
Bit
31:8
7
Description
Reserved. Read as 0’s
Enable Unsolicited Response
0: Disable
1: Enable
6:4
3:0
Reserved. Read as 0’s
Tag for Unsolicited Response
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses
7.1+2 Channel High Definition Audio Codec
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Datasheet
8.23. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 54. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F09h
0’s
32-bit Response
Codec Response for NID = 14h~1Bh, 1Eh, 1Fh
Bit
Description
31
Presence Detect Status
0: No device is attached to the pin
1: Device is attached to the pin
Measured Impedance
30:0
0x7FFFFFFF or 0xFFFFFFFF: Valid sense is not available or busy
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.24. Verb – Execute Pin Sense (Verb ID=709h)
Table 55. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= 709h
Right Channel[0]
0’s for all nodes
‘Payload’ in Command Bit[7:0]
Bit
7:1
0
Description
Reserved. Read as 0’s
Right (Ring) Channel Select
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
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Datasheet
8.25. Verb – Get Configuration Default (Verb ID=F1Ch)
Read the 32-bit sticky register for each Pin Widget configured by software.
Table 56. Verb – Get Configuration Default (Verb ID=F1Ch)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F1Ch
0’s
32-bit Response
Codec Response for NID=14h, 15h, 16h, 17h, 18h, 19h, 1Ah, 1Bh, 1Eh, and 1Fh
Bit
Description
31:0
32-bit configuration information for each pin widget
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
8.26. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh such as placement and expected default device.
Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=71Ch,
Label [7:0]
0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~1Bh, 1Eh and 1Fh. Other widgets will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.27. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 58. Verb – Get BEEP Generator (Verb ID= F0Ah)
Get Command Format
Codec Response Format
Response [31:0]
Divider [7:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID= F1Bh
0’s
‘Response’ for NID=01h (Audio Function Group)
Bit
Description
31:8
7:0
Reserved
Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input
Codec Response for Other NID
Bit
Description
31:0
0’s
8.28. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=71Bh
Divider [7:0]
0’s for all nodes
‘Divider’ in Set Command
Bit
31:8
7:0
Description
Reserved
Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.29. Verb – Get GPIO Data (Verb ID= F15h)
Table 60. Verb – Get GPIO Data (Verb ID= F15h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=F15h
0’s
32-bit Response
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Data. Not supported in the ALC882 series
GPIO[1:0] Data
1:0
The value written (output) or sensed (input) on the corresponding pin if it is enabled
Codec Response for Other NID
Bit
Description
31:0
0’s
8.30. Verb – Set GPIO Data (Verb ID= 715h)
Table 61. Verb – Set GPIO Data (Verb ID= 715h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=715h
Data [7:0]
0’s for all nodes
‘Data’ in Set command for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] output Data. Not supported in the ALC882 series
GPIO[1:0] Output Data
1:0
The value written determines the value driven on a pin that is configured as an output pin
Codec Response for All NID
Bit
Description
31:0
0’s
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.31. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Table 62. Verb – Get GPIO Enable Mask (Verb ID= F16h)
Get Command Format
Codec Response Format
Response [31:0]
EnableMask [7:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F16h
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
Reserved
1:0
GPIO[1:0] Enable mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
8.32. Verb – Set GPIO Enable Mask (Verb ID=716h)
Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=716h
Enable Mask [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Enable Mask. Not supported in the ALC882 series
GPIO[1:0] Enable Mask
1:0
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.33. Verb – Get GPIO Direction (Verb ID=F17h)
Table 64. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F17h
0’s
Direction [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Direction Control. Not supported in the ALC882 series
GPIO[1:0] Direction Control
1:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
8.34. Verb – Set GPIO Direction (Verb ID=717h)
Table 65. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=717h
Direction [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Direction Control. Not supported in the ALC882 series
GPIO[1:0] Direction Control
1:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.35. Verb – Get GPIO Unsolicited Response Enable Mask
(Verb ID=F19h)
Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Response [31:0]
UnsolEnable [7:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=F19h
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC882 series
GPIO[1:0] Unsolicited Enable mask
1:0
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
8.36. Verb – Set GPIO Unsolicited Response Enable Mask
(Verb ID=719h)
Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=719h
UnsolEnable [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC882 series
GPIO[1:0] Unsolicited Enable Mask
1:0
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’and Verb-‘Unsolicited
Response’for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
8.37. Verb – Function Reset (Verb ID=7FFh)
Table 68. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01H)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=7FFh
0’s
0’s
Codec Response
Bit
Description
31:0
Reserved. Read as 0’s
Note: The Function Reset command causes all widgets in the ALC882 series to return to their power on default state.
8.38. Verb – Get Digital Converter Control 1 & Control 2 (Verb
ID= F0Dh, F0Eh)
Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F0Dh/
F0Eh
0’s
Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0])
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit
31:16
15
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Read as 0’s
Reserved. Read as 0’s
14:8
7
CC[6:0] (Category Code)
LEVEL (Generation Level)
PRO (Professional or Consumer format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (control V bit and data in Sub-Frame)
V for Validity Control (control V bit and data in Sub-Frame)
2
1
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Datasheet
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0])
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit
Description – SIC (S/PDIF IEC Control) Bit[7:0]
0
Digital Enable. DigEn
0: OFF
1: ON
NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Dh)’
NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Eh)’
Bit
31:16
15
Description (part of S/PDIF-IN Channel Status)
Reserved. Read as 0’s
Reserved. Read as 0’s
14:8
7
CC[6:0] (Category Code)
LEVEL (Generation Level)
PRO (Professional or Consumer format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
Reserved
2
1
In‘V’alid. V bit in sub-frame of S/PDIF-IN
0: Data X and Y are valid, or S/PDIF-IN is not locked
1: At least one of data X and Y is invalid
Digital Enable. DigEn
0
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0’s
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Datasheet
8.39. Verb – Set Digital Converter Control 1 & Control 2
(Verb ID=70Dh, 70Eh)
Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Xh, Set Control 1)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=70Dh
SIC [7:0]
Set Command Format (Verb ID=70Yh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=70Eh
SIC [15:8]
‘Payload’ in Set Control 1 for NID=06h (S/PDIF-OUT)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
LEVEL (Generation Level)
PRO (Professional or Consumer format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (control V bit and data in Sub-Frame)
V for Validity Control (control V bit and data in Sub-Frame)
Digital Enable. DigEn
2
1
0
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s
6:0
CC[6:0] (Category Code)
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Datasheet
‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN)
Bit
7:1
0
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved
Digital Enable. DigEn
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN)
Bit Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s
7:0
Note: Other widgets will ignore this verb.
8.40. Get/Set Volume Knob Widget (NID=21h)
(Verb ID= F0Fh/70Fh)
Table 71. Get/Set Volume Knob Widget (NID=21h) (Verb ID= F0Fh/70Fh)
Get Command Format Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=F0Fh
0’s
Bit[31:8]=0’s, Bit[7:0] is volume
Codec Response for NID=21h (Volume Knob Widget)
Bit
31:8
7
Description
Reserved
Direct
0: The volume generated by an external HW volume control will be sent by unsolicited
response. Software is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
Volume in steps
6:0
Set Command Format (Verb ID=70Yh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=70Fh Bit[7] is ‘Direct’ control
‘Payload’ in Set Command for NID=21h (Volume Knob Widget)
Bit
Description
Reserved
Direct
31:8
7
0: The volume generated by an external HW volume control will be sent by unsolicited
response. Software is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
Reserved
6:0
Note: Other nodes will ignore this verb.
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Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 72. Absolute Maximum Ratings
Parameter
Power Supplies:
Digital
Symbol
Minimum
Typical
Maximum
Units
DVDD
AVDD
Ta
3.0
3.6
0
3.3
5.0
-
3.6
5.5
V
V
oC
Analog
Ambient Operating
Temperature
+70
Storage Temperature
All Pins
Ts
+125
oC
ESD (Electrostatic Discharge)
Susceptibility Voltage
4500V
9.1.2. Threshold Voltage
DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load.
Table 73. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
Units
V
Input Voltage Range
-0.30
-
-
-
DVDD +0.30
0.30*DVDD
(1.00)
Low Level Input Voltage
(BCLK, RST#, SDO, SYNC, SDI)
High Level Input Voltage
(BCLK, RST#, SDO, SYNC, SDI)
Low Level Input Voltage
(S/PDIF-IN/OUT, GPIOs)
High Level Input Voltage
(S/PDIF-IN/OUT, GPIOs)
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
VIL
V
VIH
VIL
VIH
0.65* DVDD
-
-
-
-
V
V
V
(2.00)
-
0.44*DVDD
(1.45)
-
0.56* DVDD
(1.85)
VOH
0.9*DVDD
-
V
V
VOL
-
-10
-10
-
-
-
0.1*DVDD
-
-
-
-
10
10
-
µA
µA
mA
Ω
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance
-
5
-
50k
-
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Datasheet
9.1.3. Digital Filter Characteristics
Table 74. Digital Filter Characteristics
Filter
Symbol
Passband
Minimum
Typical
Maximum
Units
kHz
kHz
dB
ADC Lowpass Filter
0
-
19.2
Stopband
28.8
Stopband Rejection
Passband
-76.0
dB
±0.20
Frequency Response
Passband
DAC Lowpass Filter
0
-
19.2
kHz
kHz
dB
Stopband
28.8
Stopband Rejection
Passband
-78.5
dB
±0.20
Frequency Response
9.1.4. S/PDIF Input/Output Characteristics
DVDD= 3.3V, Tambient=25°C, with 75Ω external load.
Table 75. S/PDIF Input/Output Characteristics
Parameter
Symbol
VOH
VOL
VIH
Minimum
Typical
Maximum
Units
V
S/PDIF-OUT High Level Output
S/PDIF-OUT Low Level Output
S/PDIF-IN High Level Input
S/PDIF-IN Low Level Input
S/PDIF-IN Bias Level
3.0
3.3
0
-
0.3
-
-
V
1.85
-
V
VIL
-
-
-
1.45
-
V
Vt
1.5
V
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Datasheet
9.2. AC Characteristics
9.2.1. Link Reset and Initialization Timing
Table 76. Link Reset and Initialization Timing
Parameter
Symbol
TRST
Minimum
Typical
Maximum
Units
µs
RESET# Active Low Pulse Width
RESET# Inactive to BCLK
Startup delay for PLL ready time
SDI Initialization Request
1.0
20
-
-
-
-
TPLL
µs
TFRAME
-
-
1
Frame Time
Initialization
Sequence
>= 4 BCLK
4 BCLK
4 BCLK
BCLK
SYNC
Normal Frame
SYNC
SDO
SDI
Initialization
Request
RESET#
TRST
TPLL
TFRAME
Figure 15. Link Reset and Initialization Timing
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ALC882 Series
Datasheet
9.2.2. Link Timing Parameters at the Codec
Table 77. Link Timing Parameters at the Codec
Parameter
Symbol
Minimum
Typical
Maximum
Units
MHz
ns
BCLK Frequency
BCLK Period
-
24.0
-
Tcycle
Tjitter
Thigh
-
41.67
-
BCLK Jitter
-
-
-
2.0
ns
BCLK High Pulse Width
18.75
(45%)
18.75
(45%)
2.1
22.91
(55%)
22.91
(55%)
-
ns
(%)
ns
(%)
ns
BCLK Low Pulse Width
Tlow
-
SDO Setup Time at Both Rising
and Falling Edge of BCLK
Tsetup
Thold
Ttco
-
SDO Hold Time at Both Rising and
Falling Edge of BCLK
2.1
-
-
8.0
-
ns
ns
ns
SDI Valid Time After Rising Edge
of BCLK (1: 50pF external load)
-
-
7.5
2.0
SDI Flight Time
Tflight
T_cycle
T_high
V
IH
BCLK
SDO
V
V
T
IL
T_low
T_setup T_hold
T_tco
V
OH
SDI
V
OL
T_flight
Figure 16. Link Signals Timing
7.1+2 Channel High Definition Audio Codec
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ALC882 Series
Datasheet
9.2.3. S/PDIF Output and Input Timing
Table 78. S/PDIF Output and Input Timing
Parameter
Symbol
-
Minimum
Typical
6.144
Maximum
Units
MHz
ns
S/PDIF-OUT Frequency *1
S/PDIF-OUT Period *1
S/PDIF-OUT Jitter
-
-
Tcycle
Tjitter
THigh
-
162.8
-
-
-
4
ns
S/PDIF-OUT High Level Width
78.1 (48%)
81.4 (50%)
84.6 (52%)
ns (%)
*1
S/PDIF-OUT Low Level Width*1
S/PDIF-OUT Rising Time
S/PDIF-OUT Falling Time
S/PDIF-IN Period *2
TLow
Trise
78.1 (48%)
81.4 (50%)
2.0
84.6 (52%)
ns (%)
ns
-
-
Tfall
-
2.0
-
ns
Tcycle
Tjitter
THigh
TLow
-
162.8
-
ns
S/PDIF-IN Jitter
-
-
10
ns
S/PDIF-IN High Level Width*2
S/PDIF-IN Low Level Width*2
73.2 (45%)
73.2 (45%)
81.4 (50%)
81.4 (50%)
89.5 (55%)
89.5 (55%)
ns (%)
ns (%)
*1: Bit parameters for 48kHz sample rate of S/PDIF-OUT
*2: Bit parameters for 48kHz sample rate of S/PDIF-IN
T
cycle
T
T
low
high
V
OH
V
IH
V
t
V
IL
V
OL
T
T
rise
fall
Figure 17. Output and Input Timing
9.2.4. Test Mode
The ALC882 series does not support codec test mode or Automatic Test Equipment (ATE) mode.
7.1+2 Channel High Definition Audio Codec
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ALC882 Series
Datasheet
9.3. Analog Performance
• Tambient=25 oC, DVDD=3.3V ±5%, AVDD=5.0V±5%
Standard Test Conditions
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz,
0dB attenuation
Table 79. Analog Performance
Parameter
Min
Typical
Max
Units
Full Scale Input Voltage
All Inputs (gain=0dB)
All ADC
-
-
1.6
1.1
-
-
Vrms
Vrms
Full Scale Output Voltage
All DAC
-
1.2
1.5
Vrms
S/N (A Weighted)
Analog Inputs to Outputs
All ADC
-
-
-
95
90
101
100
-
104
dB FSA
dB FSA
dB FSA
All DAC
THD+N
Analog Inputs to Outputs
ADC
All DAC
-
-
-
-90
-82
-90
-
-
-
dB FS
dB FS
dB FS
Frequency Response
Mixers
10
16
-
-
-
22,000
19,200
Hz
Hz
dB
dB
dB
dB
KΩ
ADC, DAC
Power Supply Rejection
Total Out-of-Band Noise (28.8kHz~100kHz)
Amplifier Gain Step
Crosstalk Between Input Channels
Input Impedance (gain=0dB)
Output Impedance
Amplified Output
Non-amplified Output
-40
-60
1.5
-80
47
-
-
-
-
-
-
1
100
Ω
Ω
Digital Power Supply Current (normal operation)
DVDD=3.3V
-
-
-
35
-
-
600
-
mA
µA
Digital Power Supply Current (power down mode)
DVDD=3.3V
Analog Power Supply Current (normal operation)
AVDD=5.0V
68
mA
Analog Power Supply Current (power down mode)
AVDD=5.0V
-
-
2.50
5
600
µA
V
VREFOUTx Output Voltage
VREFOUTx Output Current
2.25
3.75
mA
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
10. Application Notes
10.1. Standard Application Circuit
Please contact Realtek for the latest application circuits. To get the best compatibility in hardware design
and software driver, any modification should be confirmed by Realtek. Realtek may update the latest
application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet.
+5VA
R3
Ext.Volume Control
VAR 10K
MIC1-VREFO-R
External Volume Control
LINE2-VREFO
Ext.Volume Control
MIC2-VREFO
LINE1-VREFO
MIC1-VREFO-L
+12V
+5VA
SIDESURR-JD
CEN-JD
R7
R6
Sense B
U1
5.1K,1%
L1
LM7805CT/200mA
FERB
+5VA
3
1
10K,1%
OUT
IN
FRONT-IO-SENSE
R42
0
FRONT-L
FRONT-R
C1
C7
10u
C8
+
+
+C2
+10u
+10u
10u
Reserved for 100dB SNR
+5VA
U6
C26
1u
37
24
23
22
21
20
19
18
17
16
15
14
13
LINE1-R
LINE1-L
MIC1-R
MIC1-L
VRDA
LINE1-R
LINE1-L
MIC1-R
MIC1-L
CD-R
38
AVDD2
SURR-L
20K,1%
SURR-R
39
40
41
42
43
44
45
46
47
48
SURR-L
JDREF
C15
10u
+
R41
CD-IN Header
C17
1u
1u
1u
SURR-R
AVSS2
4
3
2
1
J1
C20
C21
CD-GND
CD-L
CEN
LFE
ALC882
CEN
MIC2-R
LFE
MIC2-R
MIC2-L
LINE2-R
LINE2-L
Sense A
SIDESURR-L
SIDESURR-R
MIC2-L
LINE2-R
LINE2-L
SIDESURR-L
SIDESURR-R
SPDIFI/EAPD
SPDIFO
Sense A
R16
R13
R12
R11
FRONT-JD
LINE1-JD
MIC1-JD
5.1K,1%
10K,1%
20K,1%
39.2K,1%
S/PDIF-IN
Split by DGND
SURR-JD
S/PDIF-OUT
+3.3VD
R17
47K
C30
C29
1u
+
Ext. PCBEEP
10u
R48
4.7k
RESET#
SYNC
SDIN
R19
22
R22
22
BCLK
C34
22P
DGND
AGND
Tied at one point only under
the codec or near the codec
SDOUT
Figure 18. Filter Connection
7.1+2 Channel High Definition Audio Codec
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ALC882 Series
Datasheet
Figure 19. IO Connection
7.1+2 Channel High Definition Audio Codec
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ALC882 Series
Datasheet
Figure 20. On board Front Panel Header & Front I/O Module Connection
7.1+2 Channel High Definition Audio Codec
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ALC882 Series
Datasheet
10.2. Volume Control by External Variable Resistor
The input range of DCVOL is from GND to AVDD. A 5-bit resolution ADC is used to convert the DC
level on a variable resistor into 32 steps for Volume knob use. DC level changes are reflected to software
to control the master volume.
ALC882
AVDD=5V
5-bit
Variable
Resistor
DCVOL (Pin 33)
ADC
Volume Code [4:0]
+5V: DCVOL=31
0V: DCVOL=0
Figure 21. Volume Control by External Variable Resistor
10.3. Volume Control by GPIO0/GPIO1
Detect Low pulses generated at GPIO0 and GPIO1 calculate the Up and Down count into 7 bits of
volume step. ‘Mute’ is also sampled to toggle the mute status. Hardware does not adjust volume. The
count value is reported via unsolicited response to software to control the master volume.
Figure 22. Volume Control by GPIO0 and GPIO1
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
11. Mechanical Dimensions
L
L1
See the Mechanical Dimensions notes on the next page.
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
11.1. Mechanical Dimensions Notes
MILLIMETER
INCH
SYMBOL
MIN. TYP MAX. MIN. TYP MAX
A
A1
A2
c
1.60
0.15 0.002
0.063
0.006
0.05
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING,
FOOTPRINT 2.0mm
1.35 1.40 1.45 0.053 0.055 0.057
0.09 0.20 0.004 0.008
0.354 BSC
D
9.00 BSC
7.00 BSC
5.50
LEADFRAME MATERIAL
D1
D2
E
E1
E2
b
0.276 BSC
0.217
0.354 BSC
0.276 BSC
0.217
APPROVE
CHECK
DOC. NO.
VERSION 02
DWG NO. PKGC-065
DATE
9.00 BSC
7.00BSC
5.50
REALTEK SEMICONDUCTOR CORP.
0.17 0.20 0.27 0.007 0.008 0.011
e
TH
L
0.50 BSC
0.0196 BSC
0o
3.5o
7o
0o
3.5o 7o
0.45 0.60 0.75 0.018 0.0236 0.030
1.00 0.0393
L1
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
ALC882 Series
Datasheet
12. Ordering Information
Table 80. Ordering Information
Part Number
ALC882-VB1-LF
ALC882D-LF
Description
Status
LQFP-48 & Lead (Pb)-Free package
Production
Production
Production
Production
Production
ALC882-VB1-LF + Dolby® Digital Live (software feature)
ALC882-VB1-LF + Dolby® Home Theater (software feature)
ALC882-VB1-LF + Dolby® Master Studio (software feature)
ALC882-VB1-LF + DTS® CONNECT™ (software feature)
ALC882H-LF
ALC882M-LF
ALC882DTS-LF
Note 1: See page 6 for lead (Pb)-free package and version identification.
Note 2: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact
Realtek sales representatives or agents.
Realtek Semiconductor Corp.
Headquarters
No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
7.1+2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.5
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