ALC888-GR [REALTEK]
7.12 CHANNEL HIGH DEFINITION AUDIO CODEC;
| 型号： | ALC888-GR |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | 7.12 CHANNEL HIGH DEFINITION AUDIO CODEC |
| 文件： | 总80页 (文件大小：1185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC888
(ALC888-GR, ALC888DD-GR, ALC888H-GR,
ALC888-VA2-GR, ALC888-VC2-GR)
7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC
DATASHEET
Rev. 1.4
07 April 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC888
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC888 Audio Codec ICs.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date Summary
1.0
2006/4/25
2007/2/5
First release.
1.1
Update section 12 Ordering Information, page 72.
Correct ADC support data in section 2.1 Hardware Features, page 2.
Add part ALC888-VA2-GR in section 12 Ordering Information, page 72.
Add part ALC888-VC-GR in section 12 Ordering Information, page 72.
Update ALC888 version C part number in section 12 Ordering Information, page 72.
1.2
1.3
1.4
2007/3/6
2007/11/21
2008/04/07
7.1+2 Channel High Definition Audio Codec
ii
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Table of Contents
1.
2.
GENERAL DESCRIPTION ...................................................................................................................................1
FEATURES ..............................................................................................................................................................2
2.1.
2.2.
2.3.
HARDWARE FEATURES................................................................................................................................................2
ALC888-VC-GR SPECIFIC FEATURES........................................................................................................................3
SOFTWARE FEATURES .................................................................................................................................................3
3.
4.
SYSTEM APPLICATIONS ....................................................................................................................................4
BLOCK DIAGRAM................................................................................................................................................5
ANALOG INPUT/OUTPUT UNIT....................................................................................................................................6
PIN ASSIGNMENTS...............................................................................................................................................7
GREEN PACKAGE AND VERSION IDENTIFICATION .......................................................................................................7
PIN DESCRIPTIONS..............................................................................................................................................8
4.1.
5.1.
5.
6.
6.1.
6.2.
6.3.
6.4.
DIGITAL I/O PINS........................................................................................................................................................8
ANALOG I/O PINS .......................................................................................................................................................8
FILTER/REFERENCE/NC..............................................................................................................................................9
POWER/GROUND ........................................................................................................................................................9
7.
HIGH DEFINITION AUDIO LINK PROTOCOL.............................................................................................10
7.1.
LINK SIGNALS ..........................................................................................................................................................10
7.1.1. Signal Definitions.................................................................................................................................................11
7.1.2. Signaling Topology...............................................................................................................................................12
7.2.
FRAME COMPOSITION...............................................................................................................................................13
7.2.1. Outbound Frame – Single SDO............................................................................................................................13
7.2.2. Outbound Frame – Multiple SDOs.......................................................................................................................14
7.2.3. Inbound Frame – Single SDI................................................................................................................................15
7.2.4. Inbound Frame – Multiple SDIs...........................................................................................................................16
7.2.5. Variable Sample Rates..........................................................................................................................................16
7.3.
RESET AND INITIALIZATION ......................................................................................................................................19
7.3.1. Link Reset .............................................................................................................................................................19
7.3.2. Codec Reset..........................................................................................................................................................20
7.3.3. Codec Initialization Sequence ..............................................................................................................................21
7.4.
VERB AND RESPONSE FORMAT .................................................................................................................................22
7.4.1. Command Verb Format ........................................................................................................................................22
7.4.2. Response Format..................................................................................................................................................22
7.5.
POWER MANAGEMENT .............................................................................................................................................23
7.5.1. System Power State Definitions............................................................................................................................23
7.5.2. Power Controls in NID 01h..................................................................................................................................23
7.5.3. Powered Down Conditions...................................................................................................................................24
7.5.4. ALC888-VC Additional Power Features ..............................................................................................................24
8.
SUPPORTED VERBS AND PARAMETERS .....................................................................................................25
8.1.
VERB – GET PARAMETERS (VERB ID=F00H)............................................................................................................25
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................25
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................25
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................26
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)...........................................................26
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................27
7.1+2 Channel High Definition Audio Codec
iii
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................27
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................28
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................29
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................29
8.1.10.
8.1.11.
8.1.12.
8.1.13.
8.1.14.
8.1.15.
8.1.16.
Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)...........................30
Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h).........................30
Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)........................................................31
Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)..................................................31
Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..................................................31
Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)...........................................................32
Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)...............................................32
VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)...............................................................................33
VERB – SET CONNECTION SELECT (VERB ID=701H)................................................................................................33
VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) ........................................................................................34
VERB – GET PROCESSING STATE (VERB ID=F03H)...................................................................................................37
VERB – SET PROCESSING STATE (VERB ID=703H) ...................................................................................................37
VERB – GET COEFFICIENT INDEX (VERB ID=DH).....................................................................................................38
VERB – SET COEFFICIENT INDEX (VERB ID=5H)......................................................................................................38
VERB – GET PROCESSING COEFFICIENT (VERB ID=CH)...........................................................................................39
VERB – SET PROCESSING COEFFICIENT (VERB ID=4H) ............................................................................................39
VERB – GET AMPLIFIER GAIN (VERB ID=BH)..........................................................................................................40
VERB – SET AMPLIFIER GAIN (VERB ID=3H) ...........................................................................................................42
VERB – GET CONVERTER FORMAT (VERB ID=AH)...................................................................................................43
VERB – SET CONVERTER FORMAT (VERB ID=2H) ....................................................................................................44
VERB – GET POWER STATE (VERB ID=F05H)...........................................................................................................45
VERB – SET POWER STATE (VERB ID=705H)............................................................................................................45
VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H)..............................................................................46
VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)...............................................................................46
VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) .............................................................................................47
VERB – SET PIN WIDGET CONTROL (VERB ID=707H)..............................................................................................48
VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H)..........................................................................49
VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H)...........................................................................49
VERB – GET PIN SENSE (VERB ID=F09H) ................................................................................................................50
VERB – EXECUTE PIN SENSE (VERB ID=709H) ........................................................................................................50
VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH).......................................................................................51
VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 51
VERB – GET BEEP GENERATOR (VERB ID=F0AH) ..................................................................................................52
VERB – SET BEEP GENERATOR (VERB ID=70AH) ...................................................................................................52
VERB – GET GPIO DATA (VERB ID=F15H) ..............................................................................................................53
VERB – SET GPIO DATA (VERB ID=715H) ...............................................................................................................53
VERB – GET GPIO ENABLE MASK (VERB ID=F16H) ...............................................................................................54
VERB – SET GPIO ENABLE MASK (VERB ID=716H)................................................................................................54
VERB – GET GPIO DIRECTION (VERB ID=F17H) .....................................................................................................55
VERB – SET GPIO DIRECTION (VERB ID=717H)......................................................................................................55
VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) .......................................................56
VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ........................................................57
VERB – FUNCTION RESET (VERB ID=7FFH).............................................................................................................57
VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) .........................................58
VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ...........................................59
VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/D22H/F23H).................................................................60
VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
[7:0]) ........................................................................................................................................................................61
VERB – GET/SET EAPD ENABLE (VID=70CH/F0CH) [31:0] ...................................................................................61
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41.
8.42.
7.1+2 Channel High Definition Audio Codec
iv
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
9.
ELECTRICAL CHARACTERISTICS................................................................................................................62
9.1.
DC CHARACTERISTICS .............................................................................................................................................62
9.1.1. Absolute Maximum Ratings..................................................................................................................................62
9.1.2. Threshold Voltage.................................................................................................................................................62
9.1.3. Digital Filter Characteristics...............................................................................................................................63
9.1.4. S/PDIF Input/Output Characteristics...................................................................................................................63
9.2.
AC CHARACTERISTIC ...............................................................................................................................................64
9.2.1. Link Reset and Initialization Timing.....................................................................................................................64
9.2.2. Link Timing Parameters at the Codec ..................................................................................................................65
9.2.3. S/PDIF Output and Input Timing .........................................................................................................................66
9.2.4. Test Mode..............................................................................................................................................................66
9.3.
ANALOG PERFORMANCE ..........................................................................................................................................67
10.
APPLICATION CIRCUITS .................................................................................................................................68
10.1.
FILTER CONNECTION ................................................................................................................................................68
ONBOARD FRONT PANEL HEADER CONNECTION ......................................................................................................69
JACK CONNECTION ON REAR PANEL.........................................................................................................................70
S/PDIF INPUT/OUTPUT CONNECTION.......................................................................................................................70
10.2.
10.3.
10.4.
11.
12.
MECHANICAL DIMENSIONS...........................................................................................................................71
ORDERING INFORMATION .............................................................................................................................72
7.1+2 Channel High Definition Audio Codec
v
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS .........................................................................................................................................................8
TABLE 2. ANALOG I/O PINS.........................................................................................................................................................8
TABLE 3. FILTER/REFERENCE/NC ...............................................................................................................................................9
TABLE 4. POWER/GROUND..........................................................................................................................................................9
TABLE 5. LINK SIGNAL DEFINITIONS.........................................................................................................................................11
TABLE 6. HDASIGNAL DEFINITIONS ........................................................................................................................................11
TABLE 7. DEFINED SAMPLE RATE AND TRANSMISSION RATE ....................................................................................................17
TABLE 8. 48KHZ VARIABLE RATE OF DELIVERY TIMING ...........................................................................................................17
TABLE 9. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING ........................................................................................................18
TABLE 10. 40-BIT COMMANDS IN 4-BIT VERB FORMAT..............................................................................................................22
TABLE 11. 40-BIT COMMANDS IN 12-BIT VERB FORMAT............................................................................................................22
TABLE 12. SOLICITED RESPONSE FORMAT ..................................................................................................................................22
TABLE 13. UNSOLICITED RESPONSE FORMAT .............................................................................................................................22
TABLE 14. SYSTEM POWER STATE DEFINITIONS .........................................................................................................................23
TABLE 15. POWER CONTROLS IN NID 01H..................................................................................................................................23
TABLE 16. POWERED DOWN CONDITIONS...................................................................................................................................24
TABLE 17. VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................25
TABLE 18. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H)..........................................................................25
TABLE 19. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H) ........................................................................25
TABLE 20. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H)................................................26
TABLE 21. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H).......................................................26
TABLE 22. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H) ..........................................27
TABLE 23. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H)..............................................27
TABLE 24. PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH) ............................................28
TABLE 25. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH)............................................29
TABLE 26. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH) ................................................................29
TABLE 27. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH)........................30
TABLE 28. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H) .....................30
TABLE 29. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH).......................................................31
TABLE 30. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) .................................................31
TABLE 31. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H)...................................................31
TABLE 32. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H) .............................................................32
TABLE 33. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H)..............................................32
TABLE 34. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................33
TABLE 35. VERB – SET CONNECTION SELECT (VERB ID=701H).................................................................................................33
TABLE 36. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................34
TABLE 37. VERB – GET PROCESSING STATE (VERB ID=F03H)....................................................................................................37
TABLE 38. VERB – SET PROCESSING STATE (VERB ID=703H).....................................................................................................37
TABLE 39. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................38
TABLE 40. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................38
TABLE 41. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................39
TABLE 42. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................39
TABLE 43. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................40
TABLE 44. VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................42
TABLE 45. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................43
TABLE 46. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................44
TABLE 47. VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................45
TABLE 48. VERB – SET POWER STATE (VERB ID=705H).............................................................................................................45
TABLE 49. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)................................................................................46
TABLE 50. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................47
TABLE 51. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................48
TABLE 52. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H)...........................................................................49
7.1+2 Channel High Definition Audio Codec
vi
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
TABLE 53. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H)............................................................................49
TABLE 54. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................50
TABLE 55. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................50
TABLE 56. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH)........................................................................................51
TABLE 57. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)51
TABLE 58. VERB – GET BEEP GENERATOR (VERB ID= F0AH)...................................................................................................52
TABLE 59. VERB – SET BEEP GENERATOR (VERB ID= 70AH)....................................................................................................52
TABLE 60. VERB – GET GPIO DATA (VERB ID= F15H)...............................................................................................................53
TABLE 61. VERB – SET GPIO DATA (VERB ID= 715H)................................................................................................................53
TABLE 62. VERB – GET GPIO ENABLE MASK (VERB ID= F16H)................................................................................................54
TABLE 63. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................54
TABLE 64. VERB – GET GPIO DIRECTION (VERB ID=F17H) ......................................................................................................55
TABLE 65. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................55
TABLE 66. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................56
TABLE 67. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................57
TABLE 68. VERB – FUNCTION RESET (VERB ID=7FFH)..............................................................................................................57
TABLE 69. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH)...........................................58
TABLE 70. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH).............................................59
TABLE 71. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H)...................................................................60
TABLE 72. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
[7:0]) ........................................................................................................................................................................61
TABLE 73. VERB – GET/SET EAPD ENABLE (VID=70CH/F0CH) [31:0].....................................................................................61
TABLE 74. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................62
TABLE 75. THRESHOLD VOLTAGE ...............................................................................................................................................62
TABLE 76. DIGITAL FILTER CHARACTERISTICS ...........................................................................................................................63
TABLE 77. S/PDIF INPUT/OUTPUT CHARACTERISTICS................................................................................................................63
TABLE 78. LINK RESET AND INITIALIZATION TIMING..................................................................................................................64
TABLE 79. LINK TIMING PARAMETERS AT THE CODEC ................................................................................................................65
TABLE 80. S/PDIF OUTPUT AND INPUT TIMING ..........................................................................................................................66
TABLE 81. ANALOG PERFORMANCE............................................................................................................................................67
TABLE 82. ORDERING INFORMATION ..........................................................................................................................................72
7.1+2 Channel High Definition Audio Codec
vii
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................5
FIGURE 2. ANALOG INPUT/OUTPUT UNIT....................................................................................................................................6
FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................7
FIGURE 4. HDALINK PROTOCOL ..............................................................................................................................................10
FIGURE 5. BIT TIMING...............................................................................................................................................................11
FIGURE 6. SIGNALING TOPOLOGY .............................................................................................................................................12
FIGURE 7. SDO OUTBOUND FRAME..........................................................................................................................................13
FIGURE 8. SDO STREAM TAG IS INDICATED IN SYNC...............................................................................................................13
FIGURE 9. STRIPED STREAM ON MULTIPLE SDOS.....................................................................................................................14
FIGURE 10. SDI INBOUND STREAM.............................................................................................................................................15
FIGURE 11. SDI STREAM TAG AND DATA ....................................................................................................................................15
FIGURE 12. CODEC TRANSMITS DATA OVER MULTIPLE SDIS .....................................................................................................16
FIGURE 13. LINK RESET TIMING .................................................................................................................................................20
FIGURE 14. CODEC INITIALIZATION SEQUENCE ..........................................................................................................................21
FIGURE 15. LINK RESET AND INITIALIZATION TIMING ................................................................................................................64
FIGURE 16. LINK SIGNALS TIMING .............................................................................................................................................65
FIGURE 17. OUTPUT AND INPUT TIMING .....................................................................................................................................66
FIGURE 18. FILTER CONNECTION (ALC888, ALC888-VC, LQFP-48)........................................................................................68
FIGURE 19. ONBOARD FRONT PANEL HEADER CONNECTION......................................................................................................69
FIGURE 20. JACK CONNECTION ON REAR PANEL ........................................................................................................................70
FIGURE 21. S/PDIF INPUT/OUTPUT CONNECTION ......................................................................................................................70
7.1+2 Channel High Definition Audio Codec
viii
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
1. General Description
The ALC888 audio codecs are high-performance 7.1+2 Channel High Definition audio codecs providing
ten DAC channels that simultaneously support 7.1 sound playback, plus 2 channels of independent stereo
sound output (multiple streaming) through the front panel stereo outputs. The ALC888 integrates two
stereo ADCs that can support a stereo microphone, and feature Acoustic Echo Cancellation (AEC), Beam
Forming (BF), and Noise Suppression (NS) technology.
The ALC888 audio codecs incorporates Realtek proprietary converter technology to achieve good
playback and recording quality, and meets the latest WLP3.10 (Windows Logo Program) requirements.
The ALC888-VC meets requirements in the future Windows Logo Program (WLP), which will be
effective from 01 June 2008. The ALC888-VC conforms to Intel’s Audio Codec low power state white
paper and is ECR compliant. The enhanced functions and new features are listed in section 2.2
ALC888-VC-GR Specific Features, page 3.
All analog IO are input and output capable, and headphone amplifiers are also integrated at each analog
output. All analog IOs can be re-tasked according to user’s definitions, or automatically switched
depending on the connected device type.
Support for 16/20/24-bit S/DPIF input and output functions with sampling rate of up to 192kHz, offers
easy connection of PCs to high-quality consumer electronic products such as digital decoders and mini
disk device.
The ALC888 audio codecs support host audio controller from the Intel ICH series chipset, and also from
any other HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and
excellent software utilities like environment sound emulation, multiple bands of software equalizer and
dynamic range control, optional Dolby® Digital Live, DTS® CONNECT™, and Dolby® Home Theater
programs, the ALC888 audio codecs provides an excellent home entertainment package and game
experience for PC users.
Note: ALC888 model differences are listed in section 12 Ordering Information, page 72.
7.1+2 Channel High Definition Audio Codec
1
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
2. Features
2.1. Hardware Features
High-performance DACs with 97dB SNR (A-Weighting), ADCs with 90dB SNR (A-Weighting)
Meets premium performance requirements for Microsoft WLP 3.10
ALC888 Ver.C meets future WLP performance requirements (effective from 01 June 2008)
Ten DAC channels support 7.1 sound playback, plus 2 channels of independent stereo sound output
(multiple streaming) through the front panel output
Two stereo ADCs support one stereo microphone and one legacy mixer recording simultaneously
All DACs support independent 16/20/24-bit, 44.1k/48k/96k/192kHz sample rate
All ADCs support independent 16/20-bit, 44.1k/48k/96k sample rate
All ADCs support independent 16/20/24-btt, 44.1k/48k/96k/192kHz sample rate (ALC888 Ver.C)
16/20/24-bit S/PDIF-OUT supports 44.1k/48k/96k/192kHz sample rate
16/20/24-bit S/PDIF-OUT supports 44.1k/48k/88.2k/96k/192kHz sample rate (ALC888 Ver.C)
16/20/24-bit S/PDIF-IN supports 44.1k/48k/96k/192kHz sample rate
Up to four channels of microphone array input are supported for AEC/BF application
High-quality analog differential CD input
Supports external PCBEEP input and built-in digital BEEP generator
Software selectable 2.5V/3.75V VREFOUT
Two jack detection pins each designed to detect up to 4 jacks
Supports legacy analog mixer architecture
Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain
Software selectable boost gain (+10/+20/+30dB) for analog microphone input
All analog jacks are stereo input and output re-tasking for analog plug & play
Built-in headphone amplifiers for each re-tasking jack
7.1+2 Channel High Definition Audio Codec
2
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Two GPIOs (General Purpose Input and Output) for customized applications
Supports anti-pop mode when analog power AVDD is on and digital power is off.
Supports stereo digital microphone interface for improved voice quality
48-pin LQFP ‘Green’ package
2.2. ALC888-VC-GR Specific Features
Integrated high-pass filter to cancel DC offset generated from digital microphone
Supports low voltage IO (1.5V~3.3V) for HDA Link
Intel low power ECR compliant, supports power status control for each analog converter and pin
widget, supports jack detection and wake-up event in D3 mode
PCBEEP pass-through function is supported when the ALC888 version C is in D3 mode
2.3. Software Features
Meets Microsoft WLP 3.10 and future WLP audio requirements
WaveRT-based audio function driver for Windows Vista
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
Emulation of 26 sound environments to enhance gaming experience
Multi-band software equalizer and related tools are provided
Voice Cancellation and Key Shifting effect
Dynamic range control (expander, compressor and limiter) with adjustable parameters
Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience
Provides 10-foot GUI for easy menu navigation on Windows Media Center
7.1+2 Channel High Definition Audio Codec
3
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice application
Smart multiple streaming operation
HDMI audio driver for AMD platform
Dolby® PCEE program™ (optional software feature)
DTS® CONNECT™ (optional software feature)
SRS® TrueSurround HD (optional software feature)
Fortemedia® SAM™ technology for voice processing (Beam Forming and Acoustic Echo
Cancellation) (optional software feature)
Creative® Host Audio program (optional software feature)
Voice recognition and Realtek proprietary API (SkyTel) is supported (Optional software feature)
3. System Applications
Desktop multimedia PCs
Notebook PCs
Information appliances (IA) e.g., set-top box
7.1+2 Channel High Definition Audio Codec
4
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
4. Block Diagram
Figure 1. Block Diagram
7.1+2 Channel High Definition Audio Codec
5
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
4.1. Analog Input/Output Unit
Pin Complex widgets NID=14h~1Bh are re-tasking IOs.
Left
A
R
EN_OBUF
EN_AMP
Right
R
Output_Signal_Left
Output_Signal_Right
Input_Signal_Left
Input_Signal_Right
EN_OBUF
EN_IBUF
Figure 2. Analog Input/Output Unit
7.1+2 Channel High Definition Audio Codec
6
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
5. Pin Assignments
36 35 34 33 32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
16
15
14
13
LINE1-R (Port-C-R)
37
38
39
40
41
42
43
44
45
46
47
48
PIN37-VREFO
AVDD2
SURR-L (Port-A-L)
JDREF
SURR-R (Port-A-R)
AVSS2
CENTER (Port-G-L)
LFE (Port-G-R)
LINE1-L (Port-C-L)
MIC1-R (Port-B-R)
MIC1-L (Port-B-L)
CD-R
CD-GND
CD-L
ALC888
MIC2-R (Port-F-R)
LLLLLLL
TXXXVV
SIDE-L (Port-H-L)
SIDE-R (Port-H-R)
MIC2-L (Port-F-L)
LINE2-R (Port-E-R)
LINE2-L (Port-E-L)
Sense A
SPDIFI/EAPD
SPDIFO
1
2
3
4
5
6
7
8
9 10 11 12
Figure 3. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version number is shown
in the location marked ‘VV’. For example, ‘VV=C0’ indicates silicon version ‘C’ and stepping version
‘0’, which is the first stepping of the ALC888-VC.
7.1+2 Channel High Definition Audio Codec
7
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Pin Description Characteristic Definition
Name
Type
RESET#
SYNC
I
I
11
10
6
H/W Reset
Vt=0.5*DVDD
Vt=0.5*DVDD
Vt=0.5*DVDD
Vt=0.5*DVDDIO
Sample Sync (48kHz)
24MHz Bit Clock Input
Serial TDM Data Input
Serial TDM Data Output
S/PDIF Input /
BITCLK
SDATA-OUT
SDATA-IN
SPDIFI /
EAPD
I
I
5
O
IO
8
Vt=0.5*DVDDIO, VOH=DVDDIO, VOL=DVSS
VIL=1.45V, VIH=1.85V /
47
Signal to power down ext. amp
S/PDIF Output
V
OH=DVDD, VOL=DVSS
Output has 12mA@75Ω driving capability
OH=DVDD, VOL=DVSS
SPDIFO
O
48
2
V
GPIO0/
DMIC-CLK
GPIO1/
IO
IO
General Purpose Input/Output 0
Clock output to digital MIC
General Purpose Input/Output 1
Serial data from digital MIC
Input: Vt=(2/3)*DVDD
Output: VOH=DVDD, VOL=DVSS
Input: Vt=(2/3)*DVDD
Output: VOH=DVDD, VOL=DVSS
Total: 9 Pins
3
DMIC-DATA
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Name
Type
IO
Pin Description
Characteristic Definition
LINE2-L
LINE2-R
MIC2-L
14
15
16
2nd Line Input Left Channel
2nd Line Input Right Channel
Analog input/output, default is input (JACK-E)
Analog input/output, default is input (JACK -E)
IO
IO
2
nd Stereo Microphone Input Left Analog input/output, default is input (JACK -F)
Channel
MIC2-R
IO
17
2
nd Stereo Microphone Input
Analog input/output, default is input (JACK -F)
Right Channel
CD-L
I
I
18
19
20
21
CD Input Left Channel
CD Input Reference Ground
CD Input Right Channel
Analog input, 1.6Vrms of full scale input
Analog input, 1.6Vrms of full scale input
Analog input, 1.6Vrms of full scale input
CD-GND
CD-R
I
MIC1-L
IO
1st Stereo Microphone Input Left Analog input/output, default is input (JACK -B)
Channel
MIC1-R
IO
22
1st Stereo Microphone Input
Right Channel
Analog input/output, default is input (JACK -B)
LINE1-L
LINE1-R
PCBEEP
FRONT-L
FRONT-R
SURR-L
IO
IO
I
23
24
12
35
36
39
1st Line Input Left Channel
1st Line Input Right Channel
External PCBEEP Input
Analog input/output, default is input (JACK -C)
Analog input/output, default is input (JACK -C)
Analog input, 1.6Vrms of full scale input
Analog output (JACK -D)
IO
IO
IO
Front Output Left Channel
Front Output Right Channel
Surround Out Left Channel
Analog output (JACK -D)
Analog output (JACK -A)
7.1+2 Channel High Definition Audio Codec
8
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Name
Type
IO
O
Pin Description
Characteristic Definition
Analog output (JACK -A)
Analog output (JACK -G)
Analog output (JACK -G)
Analog output (JACK -H)
Analog output (JACK -H)
Jack resistor network input 1
Jack resistor network input 2
Total: 22 Pins
SURR-R
CENTER
LFE
41
43
44
45
46
13
34
Surround Out Right Channel
Center Output
O
Low Frequency Output
Side Output Left Channel
Side Output Right Channel
Jack Detect Pin L
SIDE-L
SIDE-R
Sense A
Sense B
O
O
I
I
Jack Detect Pin 2
6.3. Filter/Reference/NC
Table 3. Filter/Reference/NC
Type Pin Description
Name
Characteristic Definition
10µf capacitor to analog ground
2.5V/3.75V reference voltage
2.5V/3.75V reference voltage
2.5V/3.75V reference voltage
2.5V/3.75V reference voltage
2.5V/3.75V reference voltage
-
VREF
-
27 2.5V Reference Voltage
MIC1-VREFO-L
LINE1-VREFO
MIC2-VREFO
LINE2-VREFO
MIC1-VREFO-R
NC
O
O
O
O
O
-
28 Bias Voltage for MIC1 Jack
29 Bias Voltage for LINE1 Jack
30 Bias Voltage for MIC2 Jack
31 Bias Voltage for LINE2 Jack
32 Bias Voltage for MIC1 Jack
33 Not Connected
PIN37-VREFO
JDREF
O
-
37 Bias Voltage for Software Select Jack 2.5V/3.75V reference voltage
40 Reference Resistor for Jack Detection 20K, 1% external resistor to analog ground
Total: 9 Pins
6.4. Power/Ground
Table 4. Power/Ground
Type Pin Description
Name
Characteristic Definition
AVDD1
AVSS1
AVDD2
AVSS2
DVDD
DVSS
I
I
I
I
I
I
I
I
25 Analog VDD
Analog power for mixer and amplifier
Analog ground for mixer and amplifier
Analog power for DACs and ADCs
Analog ground for DACs and ADCs
Digital power for core
26 Analog GND
38 Analog VDD
42 Analog GND
1
4
9
7
Digital VDD
Digital GND
Digital VDD
Digital GND
Digital ground for core
DVDD-IO
DVSS
Digital IO power for HDA bus
Digital ground for HDA bus
Total: 8 Pins
7.1+2 Channel High Definition Audio Codec
9
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7. High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
T
= 20.833 盜 (48KHz)
frame_sync
Previous Frame
BCLK
Next Frame
Frame SYNC= 8 BCLK
Stream 'A' Tag
(Here 'A' = 5)
Stream 'B' Tag
(Here 'B' = 6)
SYNC
SDO
SDI
Command Stream
(40-bit data)
Stream 'B' Data
Stream 'A' Data
Stream
'C' Tag
Stream 'C' Data
Response Stream
(36-bit data)
(n bytes + 10-bit data)
RST#
Figure 4. HDA Link Protocol
7.1+2 Channel High Definition Audio Codec
10
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.1.1.
Signal Definitions
Table 5. Link Signal Definitions
Item
Description
BCLK
SYNC
24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.
48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are
carried on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec
samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at
least one SDO. To extend outbound bandwidth, multiple SDOs may be supported.
SDI
Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be
supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each
rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Table 6. HDA Signal Definitions
Signal Name
Source
Controller
Type for Controller Description
BCLK
SYNC
SDO
Output
Output
Global 24.0MHz Bit Clock
Controller
Global 48kHz Frame Sync and Outbound Tag Signal
Serial Data Output from Controller
Controller
Output
SDI
Codec/Controller
Input/Output
Serial data input from codec. Weakly pulled down by the
controller
RST#
Controller
Output
Global Active Low Reset Signal
BCLK
8-Bit Frame SYNC
SYNC
Start of Frame
7
6
5
4
3
2
1
0
999 998 997 996995 994 993 992 991 990
SDO
SDI
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK
Controller samples SDI at rising edge of BCLK
Figure 5. Bit Timing
7.1+2 Channel High Definition Audio Codec
11
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.1.2.
Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 6 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 13 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 6 can be implemented concurrently in an HDA system. The ALC888
audio codecs are designed to receive a single SDO stream.
SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA
Controller
SDI1
SDI0
SDO1
SDO0
SYNC
BCLK
RST#
. . .
Codec 0
Codec 1
Codec 2
Codec N
Single SDO
Single SDI
Two SDOs
Single SDI
Single SDO
Two SDIs
Two SDOs
Multiple SDIs
Figure 6. Signaling Topology
7.1+2 Channel High Definition Audio Codec
12
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.2. Frame Composition
7.2.1.
Outbound Frame – Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be two blocks in the same stream to carry
96kHz samples (Figure 7).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 8).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
A 48kHz Frame is composed of Command stream and multiple Data streams
Previous Frame
Next Frame
Frame SYNC
Stream 'A' Tag
(Here 'A' = 5)
Stream 'X' Tag
(Here 'X' = 6)
SYNC
SDO
Command Stream
0s
Stream 'A' Data
Stream 'X' Data
Padded at the
end of Frame
Null Field
One or multiple blocks in a stream
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples
..
.
Block 1
Block 2
Block Y
..
.
Sample 1 Sample 2
Sample Z
Z channels of PCM Sample
...
msb first in a sample
msb
lsb
Figure 7. SDO Outbound Frame
BCLK
SYNC
Stream Tag
msb lsb
1 0 1 0
Stream=10
(4-Bit)
Preamble
(4-Bit)
Data of Stream 10
7 6 5 4 3 2 1 0
Previous Stream
SDO
Figure 8. SDO Stream Tag is Indicated in SYNC
7.1+2 Channel High Definition Audio Codec 13 Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.2.2.
Outbound Frame – Multiple SDOs
The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the ‘Stripe Control’ bit in the controller’s Output Stream Control Register to initiate
a specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
the data stream is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not striped. It
is always transmitted on SDO0, and copied on SDO1.
Figure 9. Striped Stream on Multiple SDOs
7.1+2 Channel High Definition Audio Codec
14
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.2.3.
Inbound Frame – Single SDI
An Inbound Frame – A single SDI is composed of one 36-bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), the SDI is driven by the codec at
each rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 10).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 11).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Previous Frame
Frame SYNC
Next Frame
SYNC
SDI
0s
Stream 'X'
Response Stream
Stream 'A'
Null Field
Padded at the end of Frame
Stream Tag
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
...
Block Y Null Pad
Block 1
Block 2
Sample 1 Sample 2
msb ...
...
Sample Z Z channels of PCM Sample
lsb msb first in a sample
Figure 10. SDI Inbound Stream
BCLK
SDI
n-Bit Sample Block
Null Pad
Next Stream
Stream Tag
Data Length in Bytes
B5 B4 B3 B2 B1
B8
Dn-1 Dn-2
0
0
B9
B7 B6
B0
D0
0
0
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 11. SDI Stream Tag and Data
7.1+2 Channel High Definition Audio Codec
15
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.2.4.
Inbound Frame – Multiple SDIs
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data into separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI
Tag A
Data A
Response Stream
Stream 'X'
0s
Stream 'Y'
0s
0
Stream 'B'
Data B
SDI
Response Stream Tag B
1
Stream A, B, X, and Y are independent and have separate IDs
Codec drives SDI0 and SDI1
Figure 12. Codec Transmits Data Over Multiple SDIs
7.2.5.
Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 17, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 17, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames.
The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’ interleaves 13 frames containing no
sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence AND interleave n empty frames.
Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame
AND interleave an empty frame between non-empty frames (Table 9, page 18).
7.1+2 Channel High Definition Audio Codec
16
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Table 7. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base
44.1kHz Base
1/6
1/4
1/3
1/2
2/3
1
8kHz (1 sample block every 6 frames)
12kHz (1 sample block every 4 frames)
16kHz (1 sample block every 3 frames)
-
-
11.025kHz (1 sample block every 4 frames)
-
22.05kHz (1 sample block every 2 frames)
-
32kHz (2 sample blocks every 3 frames)
48kHz (1 sample block per frame)
96kHz (2 sample blocks per frame)
192kHz (4 sample blocks per frame)
44.1kHz (1 sample block per frame)
88.2kHz (2 sample blocks per frame)
176.4kHz (4 sample blocks per frame)
2
4
Table 8. 48kHz Variable Rate of Delivery Timing
Rate
8kHz
Delivery Cadence
YNNNNN (repeat)
YNNN (repeat)
YNN (repeat)
Y2NN (repeat)
Y (repeat)
Description
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 4 frames
One sample block is transmitted in every 3 frames
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 6 frames
Two sample blocks are transmitted in each frame
Four sample blocks are transmitted in each frame
12kHz
16kHz
32kHz
48kHz
96kHz
192kHz
Y2 (repeat)
Y4 (repeat)
N: No sample block in a frame
Y: One sample block in a frame
Yx: X sample blocks in a frame
7.1+2 Channel High Definition Audio Codec
17
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Table 9. 44.1kHz Variable Rate of Delivery Timing
Delivery Cadence
Rate
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz
{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz
88.2kHz
174.4kHz
12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - } =NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz
88.2kHz
174.4kHz
12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.
122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.
124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.
7.1+2 Channel High Definition Audio Codec
18
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (for example, hot docking a codec to an HDA system)
7.3.1.
Link Reset
A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 13, page 20, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)
Enter ‘Link Reset’:
n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at
the end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
7.1+2 Channel High Definition Audio Codec
19
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
t Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
>=100 usec >= 4 BCLK
Initialization Sequence
Previous Frame
4 BCLK
4 BCLK
Link in Reset
BCLK
SYNC
SDOs
SDIs
Normal Frame
SYNC
Normal Frame
SYNC is absent
Driven Low
Driven Low
Driven Low
Pulled Low
2
8
Pulled Low
Pulled Low
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 13. Link Reset Timing
7.3.2.
Codec Reset
A ‘Codec Reset’ is initiated via the codec RESET command verb. It results in the target codec being reset
to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
7.1+2 Channel High Definition Audio Codec
20
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.3.3.
Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
o The codec will stop driving the SDI during this turnaround period
pqrs The controller drives SDI to assign a CAD to the codec
t The controller releases the SDI after the CAD has been assigned
u Normal operation state
Turnaround Frame
(Non-48kHz Frame)
Address Frame
(Non-48kHz Frame)
Exit from Reset Connection Frame
Normal Operation
BCLK
Frame SYNC
SYNC
Frame SYNC
Frame SYNC
5
4
6
Response
SDIx
SD14
SD0 SD1
3
1
2
7
8
RST#
Codec
Drives SDIx
Codec
Controller Drives SDIx
Controller
Codec Drives SDIx
Turnaround
(477 BCLK
Max.)
Turnaround
(477 BCLK
Max.)
Figure 14. Codec Initialization Sequence
7.1+2 Channel High Definition Audio Codec
21
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.4. Verb and Response Format
7.4.1.
Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and
controls parameters in the codec.
Table 10. 40-Bit Commands in 4-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 11. 40-Bit Commands in 12-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
7.4.2.
Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 12. Solicited Response Format
Bit [35]
Bit [34]
Bit [33:32]
Bit [31:0]
Valid
Unsol=0
Reserved
Response
Table 13. Unsolicited Response Format
Bit [35]
Valid
Bit [34]
Unsol=1
Bit [33:32]
Bit [31:28]
Tag
Bit [27:0]
Reserved
Response
Note: The response stream in the link protocol is 36-bits wide. The response is placed in the lower 32-bit
field. Bit-35 is a ‘Valid’bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that an unsolicited
response was sent.
7.1+2 Channel High Definition Audio Codec
22
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.5. Power Management
In the ALC888, all power management state changes in widgets are driven by software. Table 14 shows
the System Power State Definitions.
Note that only the ALC888-VC supports Wake-Up events when in low power mode.
All widgets, including output/input converters, support power control. Software may have various power
states depending on system configuration.
Table 15 indicates those nodes that support power management. To simplify power control, software can
configure codec power states through the audio function (NID=01h). In the ALC888-VC, output
converters (DACs) and input converters (ADCs) have no individual power control to supply fine-grained
power control.
7.5.1.
System Power State Definitions
Table 14. System Power State Definitions
Power States
Definitions
D0
D1
All power on. Individual DACs and ADCs can be powered up or down as required.
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog
reference stays up.
D2
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference is off (D1 + analog reference off).
D3 (Hot)
Power still supplied. The codec stops the internal clock. State is maintained.
All power removed. State lost.
D3 (Cold)
7.5.2.
Power Controls in NID 01h
Table 15. Power Controls in NID 01h
Item
Description
D0
D1
Normal
PD
D2
Normal
PD
D3
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Link Reset
PD
Audio Function LINK Response
(NID=01h)
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Front DAC
PD
Surr DAC
PD
PD
PD
Cen/LFE DAC
Side DAC
PD
PD
PD
PD
PD
PD
Fout DAC
PD
PD
PD
LINE ADC
PD
PD
PD
MIX ADC
PD
PD
PD
All Headphone Drivers
All Mixers
Normal
Normal
Normal
PD
Normal
Normal
Normal
PD
All Reference
PD
Note: PD=Powered Down
7.1+2 Channel High Definition Audio Codec
23
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
7.5.3.
Powered Down Conditions
Table 16. Powered Down Conditions
Condition
Description
LINK Response powered down
Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with internally
pulled low 47K resistors. S/PDIF-IN is also floated. Detection of ‘Link Reset
Entry’ and ‘Link Reset Exit’ sequences are supported. All states are maintained if
DVDD is supplied
Front DAC powered down
Surr DAC powered down
CEN/LFE DAC powered down
SIDESURR DAC powered down
Fout DAC powered down
LINE ADC powered down
MIX ADC powered down
Headphone Driver powered down
Mixers powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down. Data on SDATA-IN is quiet
Analog block and digital filter are powered down. Data on SDATA-IN is quiet
All headphone drivers are powered down
All internal mixer widgets are powered down. The DC reference and VREFOUTx
at individual pin complexes are still alive
Reference power down
All internal references, DC reference, and VREFOUTx at individual pin
complexes are off
7.5.4.
ALC888-VC Additional Power Features
The ALC888-VC is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B
compliant. It meets the five attributes discussed in the white paper:
1. D3 state power < 30mW.
2. Exit latency (D3 to D0 transfer) < 10ms.
3. Audio pop/click suppression during D3 and D0 transition < -65dBV.
4. Supports Jack detection in D3 state.
5. D3 functions with or without the BITCLK
The ALC888-VC minimizes D3 state idle mode power consumption and increases overall battery life in
mobile systems.
In D3 mode, only a power on reset or a ‘double function reset’ resets all ALC888-VC settings, cutting
software configuration time spent entering/leaving D3 state, and reducing latency time for D3 to D0
transitions.
The ALC888-VC supports Wake-Up events in D3 mode, including jack detection and GPIO status
changes. If the HDA-Link was alive (with BCLK), the ALC888-VC Wake-Up response is as normal. If
no BITCLK is present, the ALC888-VC drives the SDI high in order to wake up the system.
7.1+2 Channel High Definition Audio Codec
24
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8. Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC888. If a verb is
not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget,
some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
page 22, to get detailed information about supported parameters.
Table 17. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=00h
Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1.
Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
Description
31:16
15:0
Vendor ID=10ECh (Realtek’s PCI vendor ID)
Device ID=0888h
Note: The Root Node (NID=00h) supports this parameter.
8.1.2.
Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s
MajRev. The major version number (in decimal) of the HDA Spec to which the ALC888 is fully
compliant
19:16
15:8
MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC888 is fully
compliant
Revision ID. The vendor’s revision number
00h is for ALC888 version A, 01h is for ALC888 version B, 02h is for ALC888-VC, etc.
Stepping ID. The vendor’s stepping number within the given Revision ID
7:0
Note: The Root Node (NID=00h in the ALC888) supports this parameter.
7.1+2 Channel High Definition Audio Codec
25
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.1.3.
Parameter – Subordinate Node Count
(Verb ID=F00h, Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.
For function group nodes, it provides the total number of widgets associated with this function node.
Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24
23:16
Reserved. Read as 0’s
Starting Node Number.
The starting node number in the sequential widgets
Reserved. Read as 0’s
15:8
7:0
Total Number of Nodes.
For a root node, the total number of function groups in the root node
For a function group, the total number of widget nodes in the function group
8.1.4.
Parameter – Function Group Type
(Verb ID=F00h, Parameter ID=05h)
Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
31:9
8
Description
Reserved. Read as 0’s
UnSol Capable.
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
Function Group Type.
7:0
00h: Reserved
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function
Note: The Audio Function Group (NID=01h) supports this parameter.
7.1+2 Channel High Definition Audio Codec
26
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.1.5.
Parameter – Audio Function Capabilities
(Verb ID=F00h, Parameter ID=08h)
Table 22. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
Description
31:17 Reserved. Read as 0’s.
16
Beep Generator. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group.
15:12 Reserved. Read as 0’s.
11:8 Input Delay.
7:4
3:0
Reserved. Read as 0’s.
Output Delay.
Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.6.
Parameter – Audio Widget Capabilities
(Verb ID=F00h, Parameter ID=09h)
Table 23. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit Description
31:24 Reserved. Read as 0’s.
23:20 Widget Type.
0h: Audio Output
1h: Audio Input
4h: Pin Complex
7h~Eh: Reserved
2h: Mixer
5h: Power Widget
Fh: Vendor defined audio widget
3h: Selector
6h: Volume Knob Widget
19:16 Delay. Samples delayed between the HDA link and widgets.
15:11 Reserved. Read as 0’s.
10
Power Control.
0: Power state control is not supported on this widget
1: Power state is supported on this widget
9
Digital.
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.)
8
ConnList. Connection List.
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
7
6
UnsolCap. Unsolicited Capable.
0: Unsolicited response is not supported
1: Unsolicited response is supported
1: Processing control is supported
ProcWidget. Processing Widget.
0: No processing control
5
4
3
2
1
0
Reserved. Read as 0.
Format Override.
AmpParOvr, AMP Param Override.
OutAmpPre. Out AMP Present.
InAmpPre. In AMP Present.
Stereo.
0: Mono Widget
1: Stereo Widget
7.1+2 Channel High Definition Audio Codec
27
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.1.7.
Parameter – Supported PCM Size, Rates
(Verb ID=F00h, Parameter ID=0Ah)
Parameters here provide default information about formats. Individual converters have their own
parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
31:21
20
Description
Reserved. Read as 0’s.
B32. 32-Bit Audio Format Support.
0: Not supported
1: Supported
1: Supported
1: Supported
1: Supported
1: Supported
19
18
17
16
B24. 24-Bit Audio Format Support.
0: Not supported
B20. 20-Bit Audio Format Support.
0: Not supported
B16. 16-Bit Audio Format Support.
0: Not supported
B8. 24-Bit Audio Format Support.
0: Not supported
15:12
11
Reserved. Read as 0’s.
R12. 384kHz (=8*48kHz) Rate Support.
0: Not supported
1: Supported
10
9
8
7
6
5
4
3
2
1
0
R11. 192kHz (=4*48kHz) Rate Support.
0: Not supported
1: Supported
R10. 176.4kHz (=4*44.1kHz) Rate Support.
0: Not supported
1: Supported
R9. 96kHz (=2*48kHz) Rate Support.
0: Not supported
1: Supported
R8. 88.2kHz (=2*44.1kHz) Rate Support.
0: Not supported
1: Supported
R7. 48kHz Rate Support.
0: Not supported
1: Supported
1: Supported
R6. 44.1kHz Rate Support.
0: Not supported
R5. 32kHz (=2/3*48kHz) Rate Support.
0: Not supported
1: Supported
R4. 22.05kHz (=1/2*44.1kHz) Rate Support.
0: Not supported
1: Supported
R3. 16kHz (=1/3*48kHz) Rate Support.
0: Not supported
1: Supported
R2. 11.025kHz (=1/4*44.1kHz) Rate Support.
0: Not supported
R1. 8kHz (=1/6*48kHz) Rate Support.
0: Not supported 1: Supported
1: Supported
7.1+2 Channel High Definition Audio Codec
28
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.1.8.
Parameter – Supported Stream Formats
(Verb ID=F00h, Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
31:3
2
Description
Reserved. Read as 0’s.
AC3.
0: Not supported
Float32.
0: Not supported
PCM.
1: Supported
1: Supported
1: Supported
1
0
0: Not supported
Note: Input converters and output converters support this parameter.
8.1.9.
Parameter – Pin Capabilities
(Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 26. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
31:16
15:8
Description
Reserved. Read as 0’s.
VREF Control Capability. ‘1’ in corresponding bit field indicates signal levels of associated Vrefout are
specified as a percentage of AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
5
4
3
2
1
0
L-R Swap. Indicates the capability of swapping the left and rights.
Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins.
Input Capable. ‘1’ indicates this pin complex supports input.
Output Capable. ‘1’ indicates this pin complex supports output.
Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone.
Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in.
Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement.
Impedance Sense Capable.
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type.
Note: Only Pin Complex widgets support this parameter.
7.1+2 Channel High Definition Audio Codec
29
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.1.10.
Parameter – Amplifier Capabilities
(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
31
Description
(Input) Mute Capable.
30:23
22:16
Reserved. Read as 0.
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB.
15
Reserved. Read as 0.
14:8
Number of Steps.
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
7
Reserved. Read as 0.
Offset.
6:0
Indicates which step is 0dB.
8.1.11.
Parameter – Amplifier Capabilities
(Verb ID=F00h, Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
31
Description
(Output) Mute Capable.
30:23
22:16
Reserved. Read as 0.
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB.
Reserved. Read as 0.
15
14:8
Number of Steps.
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
Reserved. Read as 0.
7
6:0
Offset. Indicates which step is 0dB.
7.1+2 Channel High Definition Audio Codec
30
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.1.12.
Parameter – Connect List Length
(Verb ID=F00h, Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0.
Short Form.
0: Short Form
1: Long Form
6:0
Connect List Length.
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (not a MUX widget).
8.1.13.
Parameter – Supported Power States
(Verb ID=F00h, Parameter ID=0Fh)
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
31:4
3
Description
Reserved. Read as 0’s.
D3Sup.
1: Power state D3 is supported
D2Sup.
1: Power state D2 is supported
D1Sup.
1: Power state D1 is supported
D0Sup.
2
1
0
1: Power state D0 is supported
8.1.14.
Parameter – Processing Capabilities
(Verb ID=F00h, Parameter ID=10h)
Table 31. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
31:16
15:8
7:1
Description
Reserved. Read as 0’s.
NumCoeff. Number of Coefficient.
Reserved. Read as 0’s.
0
Benign.
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant
7.1+2 Channel High Definition Audio Codec
31
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.1.15.
Parameter – GPIO Capabilities
(Verb ID=F00h, Parameter ID=11h)
Table 32. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
Description
31
GPIWake=0.
Only the ALC888-VC-GR supports GPIO wake up functions.
GPIUnsol=1.
30
The ALC888 supports GPIO unsolicited response.
Reserved. Read as 0’s.
29:24
23:16
NumGPIs=00h.
No GPI pin is supported.
NumGPOs=00h.
No GPO pin is supported.
NumGPIOs=03h.
15:8
7:0
Three GPIO pins are supported.
8.1.16.
Parameter – Volume Knob Capabilities
(Verb ID=F00h, Parameter ID=13h)
Table 33. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit
Description
31:0
Reserved. Read as 0’s.
Note: The ALC888 does not support volume knob and will respond with 0s to this parameter.
7.1+2 Channel High Definition Audio Codec
32
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.2. Verb – Get Connection Select Control (Verb ID=F01h)
Table 34. Verb – Get Connection Select Control (Verb ID=F01h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for Analog Port-A/B/C/D/E/F/G/H
Bit
31:8
7:0
Description
0’s.
Connection Index Currently Set (Default value is 00h).
00h: Sum Widget NID=0Ch
01h: Sum Widget NID=0Dh
02h: Sum Widget NID=0Eh
03h: Sum Widget NID=0Fh
04h: Sum Widget NID=26h
Other: Reserved
Codec Response for Digital Pin S/PDIF-OUT
Bit
31:8
7:0
Description
0’s.
Connection Index Currently Set (Default value is 00h).
00h: Digital Converter (S/PDIF-OUT) NID=06h
Other: Reserved
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.3. Verb – Set Connection Select (Verb ID=701h)
Table 35. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=701h
Select Index [7:0]
0’s for all nodes
7.1+2 Channel High Definition Audio Codec
33
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.4. Verb – Get Connection List Entry (Verb ID=F02h)
Table 36. Verb – Get Connection List Entry (Verb ID=F02h)
Get Command Format
Codec Response Format
Response [31:0]
32-bit Response
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F02h
Offset Index - N[7:0]
Codec Response for NID=08h (LINE ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 23h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=09h (MIX ADC)
Bit
Description
15:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 22h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Ah (S/PDIF-IN Converter)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Bh (Mixer)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Bh (Pin Complex – LINE2) for N=0~3.
Returns 15h (Pin Complex-SURR) for N=4~7.
Returns 00h for N>7.
Returns 00h for N>7.
23:16
15:8
Connection List Entry (N+2).
Returns 1Ah (Pin Complex – LINE1) for N=0~3.
Returns 14h (Pin Complex – FRONT) for N=4~7.
Connection List Entry (N+1).
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7.
Returns 17h (Pin Complex – SIDESURR) for N=8~11. Returns 00h for N>11.
7:0
Connection List Entry (N).
Returns 18h (Pin Complex – MIC1) for N=0~3.
Returns 16h (Pin Complex – CEN/LFE) for N=8~11.
Returns 1Ch (Pin Complex – CD) for N=4~7.
Returns 00h for N>11.
7.1+2 Channel High Definition Audio Codec
34
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Codec Response for NID=0Ch (Front Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 02h (Front DAC) for N=0~3.
Codec Response for NID=0Dh (Surround Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 03h (Surround DAC) for N=0~3.
Codec Response for NID=0Eh (Cen/LFE Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 04h (Cen/LFE DAC) for N=0~3.
Codec Response for NID=0Fh (Side-Surr Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 05h (Front DAC) for N=0~3.
7.1+2 Channel High Definition Audio Codec
35
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Codec Response for NID=26h (Fout Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Connection List Entry (N).
Returns 25h (Fout1 DAC) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Codec Response for NID=14h~1Bh (Port-A to port-H)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 0Fh (Sum Widget NID=0Fh) for N=0~3.
Connection List Entry (N+2).
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3.
Connection List Entry (N+1).
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3.
Connection List Entry (N).
Returns 00h for n>3.
Returns 00h for N>3.
Returns 00h for N>3.
23:16
15:8
7:0
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3.
Returns 26h (Sum Widget NID=26h) for N=4~7.
Returns 00h for N>7.
Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT)
Bit
Description
31:16
Connection List Entry (N+3) and (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 00h.
Connection List Entry (N).
Returns 06h (S/PDIF-OUT converter) for N=0~3.
Returns 00h for N>3.
Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Bh (Pin Complex – LINE2) for N=0~3.
Returns 15h (Pin Complex-SURR) for N=4~7.
Connection List Entry (N+2).
Returns 1Ah (Pin Complex – LINE1) for N=0~3.
Returns 14h (Pin Complex – FRONT) for N=4~7.
Returns 0Bh (Sum Widget) for N=8~11.
Returns 00h for N>7.
Returns 00h for N>11.
23:16
7.1+2 Channel High Definition Audio Codec
36
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs)
Bit
Description
15:8
Connection List Entry (N+1).
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7.
Returns 17h (Pin Complex – SIDESURR) for N=8~11.
Returns 00h for N>11.
7:0
Connection List Entry (N).
Returns 18h (Pin Complex – MIC1) for N=0~3.
Returns 1Ch (Pin Complex – CD) for N=4~7.
Returns 16h (Pin Complex – CEN/LFE) for N=8~11.
Returns 00h for N>11.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.5. Verb – Get Processing State (Verb ID=F03h)
Table 37. Verb – Get Processing State (Verb ID=F03h)
Get Command Format
Codec Response Format
Response [31:0]
32-bit response
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F03h
0’s
Codec Response for All NID
Bit
Description
Not Supported (returns 00000000h).
31:0
8.6. Verb – Set Processing State (Verb ID=703h)
Table 38. Verb – Set Processing State (Verb ID=703h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=703h
Processing State [7:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
37
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.7. Verb – Get Coefficient Index (Verb ID=Dh)
Table 39. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format
Codec Response Format
Response [31:0]
Bit [15:0] are Coefficient Index
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Dh
0’s
Codec Response for NID=20h (Realtek Defined Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s.
Coefficient Index.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.8. Verb – Set Coefficient Index (Verb ID=5h)
Table 40. Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=5h
Coefficient Index [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
38
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.9. Verb – Get Processing Coefficient (Verb ID=Ch)
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch)
Get Command Format
Codec Response Format
Response [31:0]
Processing Coefficient [15:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ch
0’s
Codec Response for NID=20h (Realtek Define Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s.
Processing Coefficient.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.10. Verb – Set Processing Coefficient (Verb ID=4h)
Table 42. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=4h
Coefficient [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
39
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.11. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 43. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=Bh
‘Get’ payload [15:0]
Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output.
0: Input amplifier gain is requested
Reserved. Read as 0.
1: Output amplifier gain is requested
14
13
Get Left/Right.
0: Right amplifier gain is requested
Reserved. Read as 0’s.
Index[3:0] for Input Source.
1: Left amplifier gain is requested
12:4
3:0
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.
Codec Response for 08h (LINE ADC) and 09h (MIX ADC)
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –16.5B~+30dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).
6:0
Codec Response for NID=0Bh (MIXER Sum Widget)
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute (Default for all Index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).
6:0
7.1+2 Channel High Definition Audio Codec
40
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, Cen/LFE, SIDESURR Sum)
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –46.5dB~0dB in 1.5dB steps.
6:0
Codec Response for NID=14h~1Bh (Pin Complex: Front/Surr/CenLFE/SIDESURR/MIC1/MIC2/LINE1/LINE2)
Bit
31:8
7
Description
0’s.
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0.
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute.
0:Unmute
1:Mute (NID=14h~1Bh,Default=1)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0’s.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Codec Response to Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
7.1+2 Channel High Definition Audio Codec
41
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.12. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 44. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=3h
‘Set’ payload [7:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
Description
15
Set Output Amp.
1: Indicates output amplifier gain will be set.
Set Input Amp.
1: Indicates input amplifier gain will be set.
Set Left Amp.
14
13
1: Indicates left amplifier gain will be set.
Set Right Amp.
12
1: Indicates right amplifier gain will be set.
Index Offset (for input amplifiers on Sum widgets and Selector Widgets).
11:8
5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is
not set.
7
Mute.
0: Unmute
1: Mute (-∞gain)
6:0
Gain[6:0].
A 7-bit step value specifying the amplifier gain.
7.1+2 Channel High Definition Audio Codec
42
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.13. Verb – Get Converter Format (Verb ID=Ah)
Table 45. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format
Codec Response Format
Response [31:0]
Bit[15:0] are converter format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ah
0’s
Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC, S/PDIF-OUT).
Codec Response for NID=08h~0Ah (Input Converters: LINE, MIX DAC, and S/PDIF-IN)
Bit
31:16
15
Description
Reserved. Read as 0.
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: *1
011b: *4
001b: *2
100b~111b: Reserved
010b: *3
10:8
Sample Base Rate Divisor (DIV).
000b: /1
011b: /4
110b: /7
001b: /2
100b: /5
111b: /8
010b: /3
101b: /6
The ALC888 does not support Divisor. Always read as 000b.
Reserved. Read as 0.
7
6:4
Bits per Sample (BITS).
000b: 8 bits
011b: 24 bits
Number of Channels.
0: 1 channel
…..
001b: 16 bits
100b: 32 bits
010b: 20 bits
101b~111b: Reserved
3:0
1: 2 channels
2: 3 channels
15: 16 channels
Codec Response for other NID
Bit
Description
Not Supported (returns 00000000h).
31:0
7.1+2 Channel High Definition Audio Codec
43
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.14. Verb – Set Converter Format (Verb ID=2h)
Table 46. Verb – Set Converter Format (Verb ID=2h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=2h
Set format [15:0]
‘Set’ Payload in Command Bit[15:0]
Bit
31:16
15
Description
Reserved. Read as 0.
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: *1
011b: *4
001b: *2
100b~111b: Reserved
010b: *3
10:8
Sample Base Rate Divisor (DIV).
000b: /1
011b: /4
110b: /7
001b: /2
100b: /5
111b: /8
010b: /3
101b: /6
7
Reserved. Read as 0.
Bits per Sample (BITS).
000b: 8 bits
6:4
001b: 16 bits
100b: 32 bits
010b: 20 bits
101b~111b: Reserved
011b: 24 bits
Number of Channels.
0: 1 channel
3:0
1: 2 channels
2: 3 channels
…..…
15: 16 channels
7.1+2 Channel High Definition Audio Codec
44
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.15. Verb – Get Power State (Verb ID=F05h)
Table 47. Verb – Get Power State (Verb ID=F05h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h
Verb ID=Ah
0’s
Power State [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
01: Power state is D1
11: Power state is D3
10: Power state is D2
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set.
3:2
1:0
Reserved. Read as 0’s.
PS-Set. Set Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Set controls the current power setting of the referenced node.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.16. Verb – Set Power State (Verb ID=705h)
Table 48. Verb – Set Power State (Verb ID=705h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=705h
Power State [7:0]
0’s for all nodes
‘Power State’ in Command Bit[7:0]
Bit
7:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
01: Power state is D1
11: Power state is D3
10: Power state is D2
PS-Act indicates the actual power state of the referenced node.
3:2
1:0
Reserved. Read as 0’s.
PS-Set. Set Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
7.1+2 Channel High Definition Audio Codec
45
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.17. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC, S/PDIF-OUT)
Codec Response for NID=08h~0Ah (Input Converters: LINE ADC, MIX DAC, and S/PDIF-IN)
Bit
31:8
7:4
Description
Reserved. Read as 0’s.
Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Channel[3:0].
3:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for
its left and right channel.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.18. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=706h Stream & Channel [7:0]
0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
31:8
7:4
Description
Reserved. Read as 0’s.
Set Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Set Channel[3:0].
1:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for
its left and right channel.
Note: This verb assigns stream and channel for output converters (NID=02h~06h, 25h) and input converters
(NID=08h~0Ah). Other widgets will ignore this verb.
7.1+2 Channel High Definition Audio Codec
46
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.19. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 50. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Response [31:0]
Pin Control [7:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=F07h
0’s
Codec Response for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 1Fh
(Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT
and S/PDIF-IN)
Bit
31:1
7
Description
Reserved. Read as 0’s.
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O unit).
0: Disabled
Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit).
0: Disabled 1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).
1: Enabled
6
5
0: Disabled
Reserved.
1: Enabled
4:
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
011b: Reserved
001b: 50% of AVDD
100b: 80% of AVDD
010b: Ground 0V
101b: 100% of AVDD
110b~111b: Reserved
Codec Response for other NID
Bit
Description
Not Supported (returns 00000000h).
31:0
7.1+2 Channel High Definition Audio Codec
47
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.20. Verb – Set Pin Widget Control (Verb ID=707h)
Table 51. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=707h
Pin Control [7:0]
‘Pin Control’ in command [7:0] for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 1Fh.
(Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT
and S/PDIF-IN)
Bit
31:1
7
Description
Reserved. Read as 0’s.
H-Phn Enable.
0: Disabled
1: Enabled
1: Enabled
6
5
Out Enable.
0: Disabled
In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).
0: Disabled
Reserved.
1: Enabled
4:
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
011b: Reserved
001b: 50% of AVDD
100b: 80% of AVDD)
010b: Ground 0V
101b: 100% of AVDD
110b~111b: Reserved
7.1+2 Channel High Definition Audio Codec
48
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.21. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real-time event.
Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F08h
0’s
32-bit Response
Codec Response for NID=01h (GPIO), 14h~1Bh (Port A to H)
Bit
31:8
7
Description
Reserved. Read as 0’s.
Unsolicited Response is Enabled.
0: Disabled
1: Enabled
6:4
3:0
Reserved. Read as 0’s.
Assigned Tag for Unsolicited Response.
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.22. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enables a widget to generate an unsolicited response.
Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=708h
EnableUnsol [7:0]
0’s for all nodes
‘EnableUnsol’ in Command Bit[7:0] for NID=01h (GPIO), 14h~1Bh (Port A to H)
Bit
31:8
7
Description
Reserved. Read as 0’s.
Enable Unsolicited Response.
0: Disable
1: Enable
6:4
3:0
Reserved. Read as 0’s.
Tag for Unsolicited Response.
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses.
7.1+2 Channel High Definition Audio Codec
49
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.23. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 54. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Codec Response Format
Response [31:0]
32-bit Response
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID= F09h
0’s
Codec Response for NID = 14h~1Bh, 1Eh, 1Fh
Bit
Description
31
Presence Detect Status.
0: No device is attached to the pin
1: Device is attached to the pin
Measured Impedance.
30:0
The ALC888 does not support hardware impedance detection. This field is read as 0s.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.24. Verb – Execute Pin Sense (Verb ID=709h)
Table 55. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= 709h
Right Channel[0]
0’s for all nodes
‘Payload’ in Command Bit[7:0]
Bit
7:1
0
Description
Reserved. Read as 0’s.
Right (Ring) Channel Select.
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
The ALC888 does not support hardware impedance sensing and will ignore this control.
7.1+2 Channel High Definition Audio Codec
50
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.25. Verb – Get Configuration Default (Verb ID=F1Ch)
Reads the 32-bit sticky register for each Pin Widget configured by software.
Table 56. Verb – Get Configuration Default (Verb ID=F1Ch)
Get Command Format
Codec Response Format
Response [31:0]
32-bit Response
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID= F1Ch
0’s
Codec Response for NID=14h, 15h, 16h, 17h, 18h, 19h, 1Ah, 1Bh, 1Eh, and 1Fh
Bit
Description
31:0
32-bit configuration information for each pin widget.
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
8.26. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh such as placement and expected default device.
Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=71Ch,
Label [7:0]
0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~1Bh, 1Eh and 1Fh. Other widgets will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
51
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.27. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 58. Verb – Get BEEP Generator (Verb ID= F0Ah)
Get Command Format
Codec Response Format
Response [31:0]
Divider [7:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID= F1Bh
0’s
‘Response’ for NID=01h (Audio Function Group)
Bit
31:8
7:0
Description
Reserved
Frequency Divider, F[7:0]. The internal BEEP frequency is the result of dividing the 48kHz clock by 4
times the number specified in F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz.
The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.28. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=71Bh
Divider [7:0]
0’s for all nodes
‘Divider’ in Set Command
Bit
31:8
7:0
Description
Reserved.
Frequency Divider, F[7:0]. The internal BEEP frequency is the result of dividing the 48kHz clock by 4
times the number specified in F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz.
The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
52
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.29. Verb – Get GPIO Data (Verb ID=F15h)
Table 60. Verb – Get GPIO Data (Verb ID= F15h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F15h
0’s
32-bit Response
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:3] Data. Not supported in the ALC888.
GPIO[2:0] Data.
2:0
The value written (output) or sensed (input) on the corresponding pin if it is enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.30. Verb – Set GPIO Data (Verb ID=715h)
Table 61. Verb – Set GPIO Data (Verb ID= 715h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=715h
Data [7:0]
0’s for all nodes
‘Data’ in Set command for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:3] output Data. Not supported in the ALC888.
GPIO[2:0] Output Data.
2:0
The value written determines the value driven on a pin that is configured as an output pin.
Codec Response for All NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
53
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.31. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Table 62. Verb – Get GPIO Enable Mask (Verb ID= F16h)
Get Command Format
Codec Response Format
Response [31:0]
EnableMask [7:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=F16h
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
Reserved.
2:0
GPIO[2:0] Enable Mask.
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.32. Verb – Set GPIO Enable Mask (Verb ID=716h)
Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=716h
Enable Mask [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:3] Enable Mask. Not supported in the ALC888.
GPIO[2:0] Enable Mask.
2:0
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
54
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.33. Verb – Get GPIO Direction (Verb ID=F17h)
Table 64. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format
Codec Response Format
Response [31:0]
Direction [7:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=F17h
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:3] Direction Control. Not supported in the ALC888.
GPIO[2:0] Direction Control.
2:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.34. Verb – Set GPIO Direction (Verb ID=717h)
Table 65. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=717h
Direction [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:3] Direction Control. Not supported in the ALC888.
GPIO[2:0] Direction Control.
2:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
55
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.35. Verb – Get GPIO Unsolicited Response Enable Mask
(Verb ID=F19h)
Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Response [31:0]
UnsolEnable [7:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=F19h
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:3] Unsolicited Enable Mask. Not supported in the ALC888.
GPIO[2:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
2:0
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec
56
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.36. Verb – Set GPIO Unsolicited Response Enable Mask
(Verb ID=719h)
Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=719h
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:3] Unsolicited Enable Mask. Not supported in the ALC888.
GPIO[2:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
2:0
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’and Verb-‘Unsolicited
Response’for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.37. Verb – Function Reset (Verb ID=7FFh)
Table 68. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01H)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=7FFh
0’s
Codec Response
Bit
Description
31:0
Reserved. Read as 0’s.
Note: The Function Reset command causes all widgets in the ALC888 to return to their power on default state.
7.1+2 Channel High Definition Audio Codec
57
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.38. Verb – Get Digital Converter Control 1 & Control 2
(Verb ID= F0Dh, F0Eh)
Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F0Dh/F0Eh
0’s
Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0])
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit
31:16
15
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Read as 0’s.
Reserved. Read as 0’s.
14:8
7
CC[6:0] (Category Code).
LEVEL (Generation Level).
PRO (Professional or Consumer Format).
6
0: Consumer format
/AUDIO (Non-Audio Data Type).
0: PCM data
1: Professional format
1: AC3 or other digital non-audio data
5
4
3
COPY (Copyright).
0: Asserted
1: Not asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
0
VCFG for Validity Control (control V bit and data in Sub-Frame).
V for Validity Control (control V bit and data in Sub-Frame).
Digital Enable. DigEn.
0: OFF
1: ON
NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Dh)
NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Eh)
Bit
31:16
15
Description (part of S/PDIF-IN Channel Status)
Reserved. Read as 0’s.
Reserved. Read as 0’s.
14:8
7
CC[6:0] (Category Code).
LEVEL (Generation Level).
6
PRO (Professional or Consumer Format).
0: Consumer format
1: Professional format
5
4
3
2
/AUDIO (Non-Audio Data Type).
0: PCM data
1: AC3 or other digital non-audio data
1: Not asserted
COPY (Copyright).
0: Asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
Reserved.
7.1+2 Channel High Definition Audio Codec
58
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Dh)
NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Eh)
Bit
Description (part of S/PDIF-IN Channel Status)
1
In‘V’alid. V bit in sub-frame of S/PDIF-IN.
0: Data X and Y are valid, or S/PDIF-IN is not locked
1: At least one of data X and Y is invalid
0
Digital Enable. DigEn.
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.39. Verb – Set Digital Converter Control 1 & Control 2
(Verb ID=70Dh, 70Eh)
Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Xh, Set Control 1)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=70Dh
SIC [7:0]
0’s
Set Command Format (Verb ID=70Yh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=70Eh
SIC [15:8]
‘Payload’ in Set Control 1 for NID=06h (S/PDIF-OUT)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
LEVEL (Generation Level).
6
PRO (Professional or Consumer Format).
0: Consumer format
/AUDIO (Non-Audio Data Type).
0: PCM data
1: Professional format
1: AC3 or other digital non-audio data
5
4
3
COPY (Copyright).
0: Asserted
1: Not asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
0
VCFG for Validity Control (control V bit and data in Sub-Frame).
V for Validity Control (control V bit and data in Sub-Frame).
Digital Enable. DigEn.
0: OFF
1: ON
7.1+2 Channel High Definition Audio Codec
59
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s.
6:0
CC[6:0] (Category Code).
‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN)
Bit
7:1
0
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved.
Digital Enable. DigEn.
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN)
Bit
Description – SIC (S/PDIF IEC Control) Bit[7:0]
7:0
Reserved. Read as 0’s.
Note: Other widgets will ignore this verb.
8.40. Verb – Get Subsystem ID [31:0]
(Verb ID=F20h/F21h/D22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 71. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)
Get Command Format Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=01h
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Verb ID=F20h
0s
32-bit Response
Codec Response for NID=01h
Bit
31:16
15:8
7:0
Description
Subsystem ID[23:8]. (Default=10ECh)
Subsystem ID[7:0]. (Default=08h)
Assembly ID[7:0]. (Default=88h)
7.1+2 Channel High Definition Audio Codec
60
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
8.41. Verb – Set Subsystem ID [31:0] (Verb ID=723h for [31:24],
722h for [23:16], 721h for [15:8], 720h for [7:0])
Table 72. Verb – Set Subsystem ID [31:0]
(Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Node ID=01h Verb ID=723h, 722h, 721h, 720h
Label [7:0]
0s for all nodes
Codec Response for all NID
Bit
Description
31:0
0s.
8.42. Verb – Get/Set EAPD Enable (VID=70Ch/F0Ch) [31:0]
Table 73. Verb – Get/Set EAPD Enable (VID=70Ch/F0Ch) [31:0]
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Verb ID=F0Ch
0s
Bit[1] is EAPD Control
Codec Response in Get Command for NID=14h (LINE-OUT Pin Widget), 15h (HP-OUT Pin Widget)
Bit
31:3
2
Description
Reserved.
L-R Swap. The ALC888 does not support left and right channel swapping. Read as 0.
1
EAPD Enable.
0: EAPD pin state is not controlled by the power state of the corresponding pin widget
1: EAPD pin state is controlled by the power state of the corresponding pin widget
0
BTL Enable. The ALC888 does not support BTL output. Read as 0.
Codec Response in Get Command for other NID
Bit
Description
31:0
0s.
Set Command Format
Codec Response Format
Response [31:0]
0s
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd = X
Verb ID=70Ch Bit[1] is EAPD Control
Codec Response in Set Command for all Nodes
Bit
Description
31:0
0s.
7.1+2 Channel High Definition Audio Codec
61
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 74. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supply
Digital Power for Core
Digital Power for HDA Link
Analog
DVDD
DVDD-IO*
AVDD**
Ta
3.0
1.5
3.3
0
3.3
3.3
5.0
-
3.6
3.6
5.5
V
V
V
oC
oC
Ambient Operating Temperature
Storage Temperature
+70
+125
Ts
-
-
ESD (Electrostatic Discharge)
Susceptibility Voltage
Pass 3500V
All Pins
*: The digital link power DVDD-IO must be lower than the digital core power DVDD.
**: The standard testing condition before shipping is AVDD = 5.0V unless specified. Customer designing with a different
AVDD should contact Realtek technical support representatives for special testing support.
9.1.2.
Threshold Voltage
DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load.
Table 75. Threshold Voltage
Symbol Minimum
Vin -0.30
Parameter
Typical
Maximum
DVDD+0.30
0.30*DVDDIO
-
Units
V
Input Voltage Range
-
-
-
-
Low Level Input Voltage (HDA Link)
High Level Input Voltage (HDA Link)
Low Level Input Voltage
(S/PDIF-IN/OUT, GPIOs)
High Level Input Voltage
(S/PDIF-IN/OUT, GPIOs)
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
VIL
VIH
VIL
-
V
0.65*DVDDIO
-
V
0.44*DVDD
(1.45)
V
VIH
0.56*DVDD
(1.85)
-
-
V
VOH
0.9*DVDD
-
-
V
V
VOL
-
-10
-10
-
-
-
0.1*DVDD
-
-
-
-
10
10
-
µA
µA
mA
Ω
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance
-
5
-
50k
-
7.1+2 Channel High Definition Audio Codec
62
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
9.1.3.
Digital Filter Characteristics
Table 76. Digital Filter Characteristics
Filter
Description
Minimum
Typical
Maximum
Units
kHz
kHz
dB
ADC Lowpass Filter
Passband
0
-
-
0.45*Fs
Stopband
0.60*Fs
-
Stopband Rejection
Passband Frequency Response
Passband
-
-76.0
±0.02
-
-
-
-
dB
DAC Lowpass Filter
0
0.45*Fs
kHz
kHz
dB
Stopband
0.60*Fs
-
-
-
-
Stopband Rejection
Passband Frequency Response
-
-
-78.5
±0.020
dB
Note: Fs=Sample rate.
9.1.4.
S/PDIF Input/Output Characteristics
DVDD= 3.3V, Tambient=25°C, with 75Ω external load.
Table 77. S/PDIF Input/Output Characteristics
Parameter
Symbol
VOH
VOL
VIH
Minimum
Typical
Maximum
Units
V
S/PDIF-OUT High Level Output
S/PDIF-OUT Low Level Output
S/PDIF-IN High Level Input
S/PDIF-IN Low Level Input
S/PDIF-IN Bias Level
3.0
3.3
-
0.3
-
-
0
V
1.85
-
-
V
VIL
-
-
1.45
-
V
Vt
1.65
V
7.1+2 Channel High Definition Audio Codec
63
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
9.2. AC Characteristic
9.2.1.
Link Reset and Initialization Timing
Table 78. Link Reset and Initialization Timing
Parameter
Symbol
TRST
Minimum
Typical
Maximum
Units
µs
RESET# Active Low Pulse Width
RESET# Inactive to BCLK
1.0
20
-
-
-
-
TPLL
µs
Startup Delay for PLL Ready Time
SDI Initialization Request
TFRAME
-
-
1
Frame Time
Initialization
Sequence
>= 4 BCLK
4 BCLK
4 BCLK
BCLK
SYNC
Normal Frame
SYNC
SDO
SDI
Initialization
Request
RESET#
TRST
TPLL
TFRAME
Figure 15. Link Reset and Initialization Timing
7.1+2 Channel High Definition Audio Codec
64
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
9.2.2.
Link Timing Parameters at the Codec
Table 79. Link Timing Parameters at the Codec
Parameter
Symbol
Minimum
Typical
Maximum
Units
MHz
ns
BCLK Frequency
BCLK Period
-
-
24.0
-
-
-
Tcycle
41.67
BCLK Jitter
Tjitter
Thigh
Tlow
-
-
-
-
-
2.0
24.16
24.16
-
ns
BCLK High Pulse Width
BCLK Low Pulse Width
17.5
17.5
2.1
ns
ns
SDO Setup Time at Both Rising
and Falling Edge of BCLK
Tsetup
ns
SDO Hold Time at Both Rising and
Falling Edge of BCLK
Thold
Ttco
2.1
-
-
8.0
-
ns
ns
ns
SDI Valid Time After Rising Edge
of BCLK (1:50pF external Load)
-
-
7.5
2.0
SDI Flight Time
Tflight
T_cycle
T_high
V
IH
BCLK
SDO
V
V
T
IL
T_low
T_setup T_hold
T_tco
V
OH
SDI
V
OL
T_flight
Figure 16. Link Signals Timing
7.1+2 Channel High Definition Audio Codec
65
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
9.2.3.
S/PDIF Output and Input Timing
Table 80. S/PDIF Output and Input Timing
Parameter
Symbol
-
Minimum
Typical
3.072
Maximum
Units
MHz
ns
S/PDIF-OUT Frequency
S/PDIF-OUT Period1
-
-
Tcycle
Tjitter
THigh
TLow
Trise
-
325.6
-
S/PDIF-OUT Jitter
-
-
4
ns
S/PDIF-OUT High Level Width
S/PDIF-OUT Low Level Width
S/PDIF-OUT Rising Time
S/PDIF-OUT Falling Time
S/PDIF-IN Period2
156.2 (48%)
162.8 (50%)
162.8 (50%)
2.0
169.2 (52%)
ns (%)
ns (%)
ns
156.2 (48%)
169.2 (52%)
-
-
Tfall
-
2.0
-
ns
Tcycle
Tjitter
THigh
TLow
-
325.6
-
ns
S/PDIF-IN Jitter
-
-
10
ns
S/PDIF-IN High Level Width
S/PDIF-IN Low Level Width
146.4 (45%)
146.4 (45%)
162.8 (50%)
162.8 (50%)
179 (55%)
179 (55%)
ns (%)
ns (%)
Note 1: Bit parameters for 48kHz sample rate of S/PDIF-OUT.
Note 2: Bit parameters for 48kHz sample rate of S/PDIF-IN.
T
cycle
T
T
low
high
V
OH
V
IH
V
t
V
IL
V
OL
T
T
rise
fall
Figure 17. Output and Input Timing
9.2.4.
Test Mode
The ALC888 does not support codec test mode or Automatic Test Equipment (ATE) mode.
7.1+2 Channel High Definition Audio Codec
66
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
9.3. Analog Performance
• Tambient=25 oC, DVDD=3.3V ±5%, AVDD=5.0V±5%
Standard Test Conditions
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 81. Analog Performance
Parameter
Min
Typical
Max
Units
Full Scale Input Voltage
All Inputs (Gain=0dB)
ADC
-
-
1.6
1.1
-
-
Vrms
Vrms
Full Scale Output Voltage
DAC
-
-
1.2
1.0
-
-
Vrms
Vrms
Headphone Amplifier Output@32Ω Load
S/N (A Weighted)
ADC
DAC
-
-
-
90
96
95
-
-
-
dB FSA
dB FSA
dB FSA
Headphone Amplifier Output@32Ω Load
THD+N
ADC
DAC
-
-
-
-84
-90
-80
-
-
-
dB FS
dB FS
dB FS
Headphone Amplifier Output@32Ω Load
Frequency Response
ADC
10
0
-
-
-
0.45*Fs
0.45*Fs
Hz
Hz
dB
dB
dB
dB
KΩ
DAC
Power Supply Rejection
Total Out-of-Band Noise (28.8kHz~100kHz)
Amplifier Gain Step
Crosstalk Between Input Channels
Input Impedance (Gain=0dB)
Output Impedance
-40
-60
1.5
-80
47
-
-
-
-
-
-
-
-
-
Amplified Output
Non-amplified Output
-
-
1
100
-
-
Ω
Ω
Digital Power Supply Current (Normal Operation)
DVDD=3.3V
-
-
-
36
0.9
51
-
-
-
mA
mA
mA
Digital Power Supply Current (Power Down Mode)
DVDD=3.3V
Analog Power Supply Current (Normal Operation)
AVDD=5.0V
Analog Power Supply Current (Power Down Mode)
AVDD=5.0V
-
2.25
-
0.7
2.50
5
-
3.75
-
mA
V
VREFOUTx Output Voltage
VREFOUTx Output Current
Note: Fs=Sample Rate.
mA
7.1+2 Channel High Definition Audio Codec
67
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
10. Application Circuits
The ALC888-VC is a 48-pin IC and is pin-to-pin compatible with the previous ALC888 series and
ALC883. A board designed for the ALC888 series or ALC883 can use the ALC888-VC directly.
To get the best compatibility in hardware design and software driver, any modification should be
confirmed by Realtek. Realtek may update the latest application circuits onto our web site
(www.realtek.com.tw) without modifying this datasheet.
10.1. Filter Connection
Figure 18. Filter Connection (ALC888, ALC888-VC, LQFP-48)
7.1+2 Channel High Definition Audio Codec
68
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
10.2. Onboard Front Panel Header Connection
Option 1 in Figure 19 comes from by Intel’s front panel IO connectivity design guide. A drawback of this
option is that the ports connected to the front panel must use the same jack detection pin. According to the
HD Audio standard specification, ports A/B/C/D use ‘Sense A’ as the jack detect pin; ports E/F/G/H use
‘Sense B’ as the jack detect pin. This is not a good option when the system integrators want to use port-A
(pin 39/41) and port-F (pin 16/17) to be the front panel ports, as ‘Sense A’ and ‘Sense B’ cannot be tied
together.
Option 2 in Figure 19 shows an alternative front panel header design that is also compatible with standard
front panel I/O cable. The option 2 header design lets the two ports use an individual sense pin, and is
compatible with current HD Audio front panel cable.
Option 1: Follow Intel's HD Audio front panle header design
(Two ports must be in the same jack detect group)
MIC2-VREFO
D3
D4
HD Audio Front Panel I/O Cable
1N4148
1N4148
+3.3VD
J2
FIO-PORT1-L
1
3
5
7
9
2
4
6
8
10
R11
R12
FIO-PORT1-R
FIO-PORT2-R
FIO-SENSE
FIO-PRESENCE#
PORT1-SENSE-RETURN
KEY
PORT2-SENSE-RETURN
4.7K
4.7K
R14
FIO-PORT2-L
MIC2-L
MIC2-R
C35
C37
1u
1u
10K
CON10A
J3
1
3
5
7
9
2
4
6
8
10
PRESENCE#
System GPI
LINE2-R
LINE2-L
C38
C39
100u
100u
MIC2-JD
Key
FRONT-IO-JD
FIO-SENSE
LINE2-JD
R19
39.2K,1%
R18
JACK 7
CON10A
Onboard front
panel header
4
3
5
PORT2-SENSE-RETURN
20K,1%
FIO-PORT2-R
FIO-PORT2-L
L14
L15
FERB
FERB
2
1
C41
C42
FIO-PORT2 (Jack-E)
Option 2: A more flexible front panel header
100P
100P
(Each port can be in different jack detect group)
MIC2-VREFO
D5
D6
1N4148
1N4148
FIO-SENSE
+3.3VD
R20
R21
JACK 8
4
3
5
4.7K
4.7K
R23
PORT1-SENSE-RETURN
FIO-PORT1-R
FIO-PORT1-L
L16
L17
FERB
FERB
MIC2-L
MIC2-R
C44
C46
1u
1u
10K
2
1
PRESENCE#
J5
System GPI
1
3
5
7
9
2
4
6
8
10
R25
R26
C49
C50
20K,1%
LINE2-R
LINE2-L
C48
C51
100u
100u
MIC2-JD
LINE2-JD
FIO-PORT1 (Jack-F)
Sense B
Sense B
Key
100P
100P
CON10A
Onboard front
panel header
39.2K,1%
Figure 19. Onboard Front Panel Header Connection
7.1+2 Channel High Definition Audio Codec
69
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
10.3. Jack Connection on Rear Panel
MIC1-VREFO-L
MIC1-VREFO-R
R234
R235
JACK 30
4.7K
JACK 31
SURR-JD
FERB
FERB
4
3
5
4.7K
L70
MIC1-JD
4
3
5
SURR-R
SURR-L
C218 1u
C220 1u
L69
L72
MIC1-R
MIC1-L
C219 1u
C221 1u
FERB
FERB
2
1
L73
2
1
C222
C223
100P
C224
100P
C225
100P
MIC-IN (Port-B)
SURROUND (Port-A)
2.2~4.7uF for DA (LF)
frequence response
100P
JACK 32
JACK 33
CEN-JD
4
3
5
FRONT-JD
4
3
5
LFE
C228 1u
C232 1u
L74
L76
FERB
FERB
FRONT-R
FRONT-L
C231
C233
100u
100u
L75
L77
FERB
FERB
CEN
2
1
2
1
C234
C235
100P
C236
100P
C237
100P
CENTER/LFE (Port-G)
2.2~4.7uF for DA (LF)
frequence response
FRONT-OUT (Port-D)
100P
JACK 35
JACK 34
LINE1-JD
SIDESURR-JD
FERB
4
3
5
4
3
5
LINE1-R
LINE1-L
C239 1u
C241 1u
L78
L80
FERB
FERB
SIDE-R
SIDE-L
C240 1u
C242 1u
L79
L81
FERB
2
1
2
1
C245
100P
C246
100P
LINE-IN (Port-C)
C247
100P
C248
100P
SIDESURR (Port-H)
2.2~4.7uF for DA (LF)
frequence response
Figure 20. Jack Connection on Rear Panel
10.4. S/PDIF Input/Output Connection
S/PDIF module option 1: Optical S/PDIF option 2: RCA only
S/PDIF option 3: Optical & RCA
U23 TOTX178
U24 TOTX178
U25 TORX178S
Transmitter
S/PDIF-OUT
C261
Transmitter
Receiver
1
R258 100
S/PDIF-OUT
4
5
4
5
4
5
J26
0.01u
C262
100P
R259
220
RCA
R260 10
S/PDIF-OUT
+5VD
L86
C263
0.1u
C264
0.1u
47uH
C265
0.1u
+5VD
+5VD
+3.3VD
+3.3VD
U26 TORX178S
R261
12K@ALC882;NC@ALC888/883
Receiver
R262
12K@ALC882;NC@ALC888/883
S/PDIF-OUT
C266
S/PDIF-IN
S/PDIF-IN
1
R263 100
S/PDIF-OUT
R
4
5
C267
1
C269
100P
0.01u
R264 10
R266
S/PDIF-IN
C268
0.01u
S
0.01u
R270
R265 10
R268
S/PDIF-IN
R271
75
C270
J27
R267
220
J5A3
RCA
J28
RCA
C271
100P
R269 10 S/PDIF-IN
100P
RCA
10K@ALC882,NC@ALC883
10K@ALC882,NC@ALC888/8833
L87
47uH
C272
0.1u
J5A is RCA jack with switch
+5VD
Figure 21. S/PDIF Input/Output Connection
7.1+2 Channel High Definition Audio Codec
70
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
11. Mechanical Dimensions
L
L1
MILLIMETER
INCH
TYP MAX
SYMBOL
MIN TYP MAX MIN
A
A1
A2
c
-
-
-
1.60
0.15
-
-
-
0.063
0.006
0.05
0.002
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING, FOOTPRINT
2.0mm
1.35 1.40 1.45
0.053 0.055 0.057
0.09
-
0.20
0.004
-
0.008
D
9.00 BSC
7.00 BSC
5.50
0.354 BSC
0.276 BSC
0.217
LEADFRAME MATERIAL
D1
D2
E
APPROVE
CHECK
DOC. NO.
VERSION
DWG NO.
DATE
02
9.00 BSC
7.00BSC
5.50
0.354 BSC
0.276 BSC
0.217
PKGC-065
E1
E2
b
REALTEK SEMICONDUCTOR CORP.
0.17 0.20
0.50 BSC
3.5o
0.45 0.60
1.00
0.27 0.007 0.008
0.0196 BSC
3.5o
0.011
7o
e
TH
L
0o
7o
0o
0.75 0.018 0.0236 0.030
0.0393
L1
-
-
-
-
7.1+2 Channel High Definition Audio Codec
71
Track ID: JATR-1076-21 Rev. 1.4
ALC888
Datasheet
12. Ordering Information
Table 82. Ordering Information
Part Number
ALC888-GR
Description
Status
LQFP-48 with ‘Green’ Package
Production
Production
Production
Production
Production
ALC888DD-GR
ALC888H-GR
ALC888-GR + Dolby® Digital Live + DTS® CONNECT™ (software feature)
ALC888-GR + Dolby® Home Theater (software feature)
ALC888-VA2-GR ALC888 version A2, LQFP-48 with ‘Green’ package
ALC888-VC2-GR ALC888 version C2 meets future Window Logo Program (WLP) requirements,
LQFP-48 with ‘Green’ package
Note 1: See page 7 for ‘Green’package and version identification.
Note 2: Above parts are tested under AVDD =5.0V. Customers requesting lower AVDD support should contact Realtek
sales representatives or agents.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-5780211 Fax: 886-3-577-6047
www.realtek.com.tw
7.1+2 Channel High Definition Audio Codec
72
Track ID: JATR-1076-21 Rev. 1.4
相关型号：
©2020 ICPDF网 联系我们和版权申明