HYS72T64020HR-5-A [QIMONDA]
240-Pin Registered DDR2 SDRAM Modules; 240引脚注册DDR2 SDRAM模组型号: | HYS72T64020HR-5-A |
厂家: | QIMONDA AG |
描述: | 240-Pin Registered DDR2 SDRAM Modules |
文件: | 总67页 (文件大小:3847K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
March 2007
HYS72T32000HR–[2.5/3/3S/3.7/5]–A
HYS72T64001HR–[2.5/3/3S/3.7/5]–A
HYS72T64020HR–[2.5/3/3S/3.7/5]–A
240-Pin Registered DDR2 SDRAM Modules
DDR2 SDRAM
RDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.21
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
HYS72T32000HR–[2.5/3/3S/3.7/5]–A, HYS72T64001HR–[2.5/3/3S/3.7/5]–A, HYS72T64020HR–[2.5/3/3S/3.7/5]–A
Revision History: 2007-03, Rev. 1.21
Page
Subjects (major changes since last revision)
All
All
Qimonda update
Adapted internet edition
Previous Revision: 2005-09, Rev. 1.2
Chapter 4 SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product types
Chapter 5 Package Outlines updated
Previous Revision: 2005-06, Rev. 1.1
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
09152006-J5FK-C565
2
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
•
•
•
240-pin PC2-6400, PC2-5300, PC2-4200 and PC2-3200
DDR2 SDRAM memory modules for PC, Workstation and
Server main memory applications
One rank 32M x 72, 64M x 72 and two ranks 64M × 72
module organization and 32M × 8, 64M × 4 chip
organization
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
•
Programmable CAS Latencies (3, 4, 5 & 6), Burst Length
(4 & 8) and Burst Type
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
•
•
Serial Presence Detect with E2PROM
RDIMM Dimensions (nominal): 30 mm high, 133.35 mm
wide
•
•
All Speed Grades faster than DDR2–400 comply with
DDR2–400 timing specifications
Built with 256-Mbit DDR2 SDRAMs in P-TFBGA-60
chipsize packages.
•
•
Based on Standard reference layouts Raw Card “A-F”, “B-
G” & “C-H”
RoHS compliant products1)
TABLE 1
Performance for –2.5 & –3 (S)
Product Type Speed Code
–2.5
–3
–3S
Unit
Speed Grade
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
—
max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
fCK6
fCK5
fCK4
fCK3
tRCD
tRP
400
333
266
200
15
333
333
333
200
12
333
333
266
200
15
MHz
MHz
MHz
ns
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
15
12
15
ns
tRAS
tRC
45
45
45
ns
60
57
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.21, 2007-03
3
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 2
Performance for DDR2-533 and DDR2-400
Product Type Speed Code
–3.7
–5
Units
Speed Grade
PC2–4200 4–4–4
PC2–3200 3–3–3
—
Max. Clock Frequency
@CL5
@CL4
@CL3
fCK5
fCK4
fCK3
tRCD
tRP
266
266
200
15
200
200
200
15
MHz
MHz
MHz
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
15
15
ns
tRAS
tRC
45
40
ns
60
55
ns
Rev. 1.21, 2007-03
4
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1.2
Description
The QIMONDA HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
module family are Registered DIMM modules “RDIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as ECC modules in 32M x 72 (256 MByte) and
64M x 72 (512 MByte) organization and density, intended for
mounting into 240-pin connector sockets.
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E2PROM device using the 2-pin I2C
protocol. The first 128 bytes are programmed with
configuration data and are write-protected; the second
128 bytes are available to the customer.
The memory array is designed with 256-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
TABLE 3
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-6400
HYS72T32000HR–2.5–A
HYS72T64001HR–2.5–A
HYS72T64020HR–2.5–A
PC2-5300
256 MB 1R×8 PC2–6400R–666–12–F0
512 MB 1R×4 PC2–6400R–666–12–H0
512 MB 2R×8 PC2–6400R–666–12–G0
1 Rank, ECC
1 Rank, ECC
2 Rank, ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
HYS72T32000HR–3–A
HYS72T64001HR–3–A
HYS72T64020HR–3–A
HYS72T32000HR–3S–A
HYS72T64001HR–3S–A
HYS72T64020HR–3S–A
PC2–4200
256 MB 1R×8 PC2–5300R–444–12–F0
512 MB 1R×4 PC2–5300R–444–12–H0
512 MB 2R×8 PC2–5300R–444–12–G0
256 MB 1R×8 PC2–5300R–555–12–F0
512 MB 1R×4 PC2–5300R–555–12–H0
512 MB 2R×8 PC2–5300R–555–12–G0
1 Rank, ECC
1 Rank, ECC
2 Rank, ECC
1 Rank, ECC
1 Rank, ECC
2 Rank, ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
HYS72T32000HR–3.7–A
HYS72T64001HR–3.7–A
HYS72T64020HR–3.7–A
PC2-3200
256 MB 1R×8 PC2–4200R–444–11–F0
512 MB 1R×4 PC2–4200R–444–11–H0
512 MB 2R×8 PC2–4200R–444–11–G0
1 rank, ECC
1 rank, ECC
2 rank, ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
HYS72T32000HR–5–A
HYS72T64001HR–5–A
HYS72T64020HR–5–A
256 MB 1R×8 PC2–3200R–333–11–F0
512 MB 1R×4 PC2–3200R–333–11–H0
512 MB 2R×8 PC2–3200R–333–11–G0
1 Rank, ECC
1 Rank, ECC
2 Rank, ECC
256 Mbit (×8)
256 Mbit (×4)
256 Mbit (×8)
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T32000HR–5–A, indicating Rev. “A” dies are
used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–F0”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS) latency
= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced
on the Raw Card “F”
Rev. 1.21, 2007-03
5
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 4
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw Card
256 MB
512 MB
512 MB
32M ×72
64M ×72
64M ×72
1
1
2
ECC
ECC
ECC
9
13/2/10
13/2/11
13/2/10
A-F
C-H
B-G
18
18
TABLE 5
Components on Modules
DRAM Organization Note2)
Product Type1)
DRAM Components1)
DRAM Density
HYS72T32000HR
HYS72T64001HR
HYB18T256800AF
HYB18T256400AF
HYB18T256800AF
256 Mbit
256 Mbit
256 Mbit
32M × 8
64M × 4
32M × 8
—
—
—
HYS72T64020HR
1) Green Product
2) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet.
Rev. 1.21, 2007-03
6
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
2
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 6 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 7
and Table 8 respectively. The pin numbering is depicted in
Figure 1.
TABLE 6
Pin Configuration of RDIMM
Ball No.
Name
Pin
Buffer
Function
Type Type
Clock Signals
185
186
52
CK0
CK0
CKE0
CKE1
NC
I
SSTL
SSTL
SSTL
SSTL
—
Clock Signal CK0, Complementary Clock Signal CK0
I
I
Clock Enables 1:0
Note: 2-Ranks module
171
I
NC
Not Connected
Note: 1-Rank module
Control Signals
193
76
S0
S1
NC
I
SSTL
SSTL
—
Chip Select Rank 1:0
Note: 2-Ranks module
I
NC
Not Connected
Note: 1-Rank module
192
RAS
I
I
I
I
SSTL
SSTL
SSTL
CMOS
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
74
CAS
73
WE
18
RESET
Register Reset
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
190
54
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
I
SSTL
Not Connected
Less than 1Gb DDR2 SDRAMS
Rev. 1.21, 2007-03
7
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
188
183
63
A0
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Address Bus 12:0, Address Signal 10/AutoPrecharge
A1
I
A2
I
182
61
A3
I
A4
I
60
A5
I
180
58
A6
I
A7
I
179
177
70
A8
I
A9
I
A10
AP
A11
A12
A13
NC
I
I
57
I
176
196
I
I
Address Signal 13
NC
Not Connected
Note: Non CA parity modules based on 256 Mbit component
Address Signal 14
174
173
A14
NC
I
SSTL
—
Note: CA Parity module
NC
I
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
Address Signal 14
A15
NC
SSTL
—
Note: CA Parity module
NC
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
Rev. 1.21, 2007-03
8
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Data Signals
3
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input/Output pins
4
DQ1
9
DQ2
10
DQ3
122
123
128
129
12
DQ4
DQ5
DQ6
DQ7
DQ8
13
DQ9
21
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
Rev. 1.21, 2007-03
9
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
206
89
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
Check Bits
42
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Check Bits 7:0
Check Bit Input / Output pins
43
Note: NC on Non-ECC module
48
49
161
162
167
168
Rev. 1.21, 2007-03
10
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Data Strobe Bus
7
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DQS8
DQS8
DQS9
DQS9
DQS10
DQS10
DQS11
DQS11
DQS12
DQS12
DQS13
DQS13
DQS14
DQS14
DQS15
DQS15
DQS16
DQS16
DQS17
DQS17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobes 17:0
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
Rev. 1.21, 2007-03
11
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Data Mask
125
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Masks 8:0
Note: ×8 based module
134
146
155
202
211
223
232
164
EEPROM
120
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
Serial Bus Data
119
I/O
239
I
I
I
CMOS
CMOS
CMOS
Serial Address Select Bus 2:0
240
101
Parity
55
ERR_OUT
PAR_IN
O
I
CMOS
CMOS
Parity bits
Power Supplies
1
VREF
AI
—
—
—
I/O Reference Voltage
EEPROM Power Supply
I/O Driver Power Supply
238
VDDSPD
PWR
PWR
51, 56, 62, 72, 75, VDDQ
78, 170, 175, 181,
191, 194
53, 59, 64, 67, 69, VDD
172, 178, 184, 187,
189, 197
PWR
GND
—
—
Power Supply
Ground Plane
2, 5, 8, 11, 14, 17, VSS
20, 23, 26, 29, 32,
35, 38, 41, 44, 47,
50, 65, 66, 79, 82,
85, 88, 91, 94, 97,
100, 103, 106, 109,
112, 115, 118, 121,
124, 127, 130, 133,
136, 139, 142, 145,
148, 151, 154, 157,
160, 163, 166, 169,
198, 201, 204, 207,
210, 213, 216, 219,
222, 225, 228, 231,
234, 237
Rev. 1.21, 2007-03
12
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Other Pins
19, 55, 68, 102,
137, 138, 173, 220,
221
NC
NC
—
Not connected
195
77
ODT0
ODT1
NC
I
SSTL
SSTL
—
On-Die Termination Control 1:0
Note: 2-Ranks module
I
NC
Note: 1-Rank modules
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
CMOS
OD
Serial Stub Terminated Logic (SSTL_18)
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
TABLE 8
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Rev. 1.21, 2007-03
13
09152006-J5FK-C565
ꢃ
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration for RDIMM (240 pins)
95()
'4ꢀ
966
'46ꢀ
'4ꢈ
966
'4ꢇ
'46ꢁ
966
1&
'4ꢁꢀ
966
'4ꢁꢂ
'46ꢈ
966
'4ꢁꢇ
'4ꢈꢉ
966
'46ꢅ
'4ꢈꢊ
966
&%ꢁ
'46ꢋ
966
&%ꢅ
9''4
9''
1&
$ꢁꢁ
9''
$ꢉ
ꢃ 3LQꢄꢀꢀꢁ
ꢃ 3LQꢄꢀꢀꢅ
ꢃ 3LQꢄꢀꢀꢆ
ꢃ 3LQꢄꢀꢀꢂ
ꢃ 3LQꢄꢀꢀꢇ
ꢃ 3LQꢄꢀꢁꢁ
ꢃ 3LQꢄꢀꢁꢅ
ꢃ 3LQꢄꢀꢁꢆ
ꢃ 3LQꢄꢀꢁꢂ
ꢃ 3LQꢄꢀꢁꢇ
3LQꢄꢁꢈꢁ ꢃ 966
3LQꢄꢁꢈꢈ ꢃ '4ꢉ
966
'4ꢁ
'46ꢀ ꢃ 3LQꢄꢀꢀꢊ
966
'4ꢅ
'4ꢋ
966
'46ꢁ ꢃ 3LQꢄꢀꢁꢊ
5(6(7 ꢃ 3LQꢄꢀꢁꢋ
ꢃ 3LQꢄꢀꢀꢈ
ꢃ 3LQꢄꢀꢀꢉ
3LQꢄꢁꢈꢅ ꢃ '4ꢆ
3LQꢄꢁꢈꢉ ꢃ 966
3LQꢄꢁꢈꢆ ꢃ '0ꢀꢌ'46ꢇ
3LQꢄꢁꢈꢊ ꢃ 1&ꢌ'46ꢇ
3LQꢄꢁꢈꢂ ꢃ 966
ꢃ 3LQꢄꢀꢀꢋ
ꢃ 3LQꢄꢀꢁꢀ
ꢃ 3LQꢄꢀꢁꢈ
ꢃ 3LQꢄꢀꢁꢉ
3LQꢄꢁꢈꢋ ꢃ '4ꢊ
3LQꢄꢁꢈꢇ ꢃ '4ꢂ
3LQꢄꢁꢅꢀ ꢃ 966
3LQꢄꢁꢅꢁ ꢃ '4ꢁꢈ
3LQꢄꢁꢅꢈ ꢃ '4ꢁꢅ
3LQꢄꢁꢅꢅ ꢃ 966
3LQꢄꢁꢅꢉ ꢃ '0ꢁꢌ'46ꢁꢀ
3LQꢄꢁꢅꢆ ꢃ 1&ꢌ'46ꢁꢀ
3LQꢄꢁꢅꢊ ꢃ 966
3LQꢄꢁꢅꢂ ꢃ 1&
3LQꢄꢁꢅꢇ ꢃ 966
3LQꢄꢁꢉꢁ ꢃ '4ꢁꢆ
3LQꢄꢁꢉꢅ ꢃ '4ꢈꢀ
3LQꢄꢁꢉꢆ ꢃ 966
3ꢄLQꢄꢁꢉꢂ ꢃ 1&ꢌ'46ꢁꢁ
3LQꢄꢁꢉꢇ ꢃ '4ꢈꢈ
3LQꢄꢁꢆꢁ ꢃ 966
3LQꢄꢁꢆꢅ ꢃ '4ꢈꢇ
3LQꢄꢁꢆꢆ ꢃ '0ꢅꢌ'46ꢁꢈ
3LQꢄꢁꢆꢂ ꢃ 966
3LQꢄꢁꢆꢇ ꢃ '4ꢅꢁ
3LQꢄꢁꢊꢁ ꢃ &%ꢉ
3LQꢄꢁꢊꢅ ꢃ 966
3LQꢄꢁꢊꢆ ꢃ 1&ꢌ'46ꢁꢂ
3LQꢄꢁꢊꢂ ꢃ &%ꢊ
3LQꢄꢁꢊꢇ ꢃ 966
3LQꢄꢁꢂꢁ ꢃ 1&ꢌ&.(ꢁ
3LQꢄꢁꢂꢅ ꢃ 1&ꢄꢌꢄ$ꢁꢆ
3LQꢄꢁꢂꢆ ꢃ 9''4
3LQꢄꢁꢂꢂ ꢃ $ꢇ
3LQꢄꢁꢂꢇ ꢃ $ꢋ
3LQꢄꢁꢋꢁ ꢃ 9''4
3LQꢄꢁꢋꢅ ꢃ $ꢁ
3LQꢄꢁꢅꢋ ꢃ 1&
3LQꢄꢁꢉꢀ ꢃ '4ꢁꢉ
ꢃ
3LQꢄꢁꢉꢈ 966
966
ꢃ 3LQꢄꢀꢈꢀ
ꢃ
ꢃ
3LQꢄꢀꢈꢁ
3LQꢄꢀꢈꢅ
ꢃ
'4ꢁꢁ
'4ꢁꢊ
966
'46ꢈ
'4ꢁꢋ
966
'4ꢈꢆ
'46ꢅ
966
'4ꢈꢂ
&%ꢀ
966
'46ꢋ
&%ꢈ
966
&.(ꢀ
3LQꢄꢀꢈꢈ
ꢃ
ꢃ
3LQꢄꢀꢈꢉ
3LQꢄꢁꢉꢉ '4ꢈꢁ
ꢃ 3LQꢄꢀꢈꢆ
3ꢄLQꢄꢀꢈꢂ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢉꢊ '0ꢈꢌ'46ꢁꢁ
3LQꢄꢀꢈꢊ
3LQꢄꢀꢈꢋ
3LQꢄꢀꢅꢀ
3LQꢄꢀꢅꢈ
3LQꢄꢀꢅꢉ
3LQꢄꢀꢅꢊ
3LQꢄꢀꢅꢋ
3LQꢄꢀꢉꢀ
3LQꢄꢀꢉꢈ
3LQꢄꢀꢉꢉ
3LQꢄꢀꢉꢊ
3LQꢄꢀꢉꢋ
3LQꢄꢀꢆꢀ
3LQꢄꢀꢆꢈ
ꢃ
3LQꢄꢁꢉꢋ 966
ꢃ 3LQꢄꢀꢈꢇ
ꢃ 3LQꢄꢀꢅꢁ
ꢃ 3LQꢄꢀꢅꢅ
ꢃ 3LQꢄꢀꢅꢆ
ꢃ 3LQꢄꢀꢅꢂ
ꢃ 3LQꢄꢀꢅꢇ
ꢃ 3LQꢄꢀꢉꢁ
ꢃ 3LQꢄꢀꢉꢅ
ꢃ 3LQꢄꢀꢉꢆ
ꢃ 3LQꢄꢀꢉꢂ
ꢃ 3LQꢄꢀꢉꢇ
ꢃ 3LQꢄꢀꢆꢁ
ꢃ 3LQꢄꢀꢆꢅ
ꢃ 3LQꢄꢀꢆꢆ
ꢃ 3LQꢄꢀꢆꢂ
ꢃ 3LQꢄꢀꢆꢇ
ꢃ 3LQꢄꢀꢊꢁ
ꢃ 3LQꢄꢀꢊꢅ
ꢃ
3LQꢄꢁꢆꢀ '4ꢈꢅ
ꢃ
3LQꢄꢁꢆꢈ '4ꢈꢋ
ꢃ
3LQꢄꢁꢆꢉ 966
ꢃ
3LQꢄꢁꢆꢊ 1&ꢌ'46ꢁꢈ
ꢃ
3LQꢄꢁꢆꢋ '4ꢅꢀ
ꢃ
3LQꢄꢁꢊꢀ 966
ꢃ
3LQꢄꢁꢊꢈ &%ꢆ
ꢃ
3LQꢄꢁꢊꢉ '0ꢋꢌ'46ꢁꢂ
ꢃ
3LQꢄꢁꢊꢊ 966
ꢃ
3LQꢄꢁꢊꢋ &%ꢂ
ꢃ
3LQꢄꢁꢂꢀ 9''4
ꢃ
3LQꢄꢁꢂꢈ 9''
ꢃ
ꢃ
1&ꢌ%$ꢈ 3LQꢄꢀꢆꢉ
9''4
$ꢂ
$ꢆ
9''4
9''
3LQꢄꢁꢂꢉ 1&ꢌ$ꢁꢉ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢂꢊ $ꢁꢈ
3LQꢄꢀꢆꢊ
3LQꢄꢀꢆꢋ
3LQꢄꢀꢊꢀ
3LQꢄꢀꢊꢈ
3LQꢄꢀꢊꢉ
ꢃ
3LQꢄꢁꢂꢋ 9''
ꢃ
3LQꢄꢁꢋꢀ $ꢊ
ꢃ
3LQꢄꢁꢋꢈ $ꢅ
$ꢈ
ꢃ
3LQꢄꢁꢋꢉ 9''
966
ꢃ 3LQꢄꢀꢊꢆ
ꢃ 3LQꢄꢀꢊꢂ
ꢃ 3LQꢄꢀꢊꢇ
ꢃ 3LQꢄꢀꢂꢁ
ꢃ 3LQꢄꢀꢂꢅ
ꢃ 3LQꢄꢀꢂꢆ
3LQꢄꢁꢋꢆ ꢃ &.ꢀ
3LQꢄꢁꢋꢂ ꢃ 9''
3LQꢄꢁꢋꢇ ꢃ 9''
3LQꢄꢁꢇꢁ ꢃ 9''4
3LQꢄꢁꢇꢅ ꢃ 6ꢀ
3LQꢄꢁꢇꢆ ꢃ 2'7ꢀ
3LQꢄꢁꢇꢂ ꢃ 9''
3LQꢄꢁꢇꢇ ꢃ '4ꢅꢊ
3LQꢄꢈꢀꢁ ꢃ 966
3LQꢄꢈꢀꢅ ꢃ 1&ꢌ'46ꢁꢅ
3LQꢄꢈꢀꢆ ꢃ '4ꢅꢋ
3LQꢄꢈꢀꢂ ꢃ 966
3LQꢄꢈꢀꢇ ꢃ '4ꢉꢆ
3LQꢄꢈꢁꢁ ꢃ '0ꢆꢌ'46ꢁꢉ
3LQꢄꢈꢁꢅ ꢃ 966
3LQꢄꢈꢁꢆ ꢃ '4ꢉꢂ
3LQꢄꢈꢁꢂ ꢃ '4ꢆꢈ
3LQꢄꢈꢁꢇ ꢃ 966
3LQꢄꢈꢈꢁ ꢃ 1&
3LQꢄꢈꢈꢅ ꢃ '0ꢊꢌ'46ꢁꢆ
3LQꢄꢈꢈꢆ ꢃ 966
3LQꢄꢈꢈꢂ ꢃ '4ꢆꢆ
3LQꢄꢈꢈꢇ ꢃ '4ꢊꢀ
3LQꢄꢈꢅꢁ ꢃ 966
3LQꢄꢈꢅꢅ ꢃ 1&ꢌ'46ꢁꢊ
3LQꢄꢈꢅꢆ ꢃ '4ꢊꢈ
3LQꢄꢈꢅꢂ 966
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢋꢊ &.ꢀ
966
1&
3LQꢄꢀꢊꢊ
3LQꢄꢀꢊꢋ
9''
9''
%$ꢀ
:(
9''4
ꢃ
3LQꢄꢁꢋꢋ $ꢀ
ꢃ
ꢃ
$ꢁꢀꢌ$3 3LQꢄꢀꢂꢀ
3LQꢄꢁꢇꢀ %$ꢁ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢇꢈ 5$6
9''4
&$6
1&ꢌ6ꢁ
9''4
'4ꢅꢈ
966
'46ꢉ
'4ꢅꢉ
966
'4ꢉꢁ
'46ꢆ
966
'4ꢉꢅ
'4ꢉꢋ
966
1&
'46ꢊ
966
'4ꢆꢁ
'4ꢆꢊ
966
'46ꢂ
'4ꢆꢋ
966
3LQꢄꢀꢂꢈ
3LQꢄꢀꢂꢉ
3LQꢄꢀꢂꢊ
3LQꢄꢀꢂꢋ
3LQꢄꢀꢋꢀ
3LQꢄꢀꢋꢈ
3LQꢄꢀꢋꢉ
3LQꢄꢀꢋꢊ
3LQꢄꢀꢋꢋ
3LQꢄꢀꢇꢀ
3LQꢄꢀꢇꢈ
3LQꢄꢀꢇꢉ
3LQꢄꢀꢇꢊ
3LQꢄꢀꢇꢋ
3LQꢄꢁꢀꢀ
3LQꢄꢁꢀꢈ
3LQꢄꢁꢀꢉ
3LQꢄꢁꢀꢊ
3LQꢄꢁꢀꢋ
3LQꢄꢁꢁꢀ
3LQꢄꢁꢁꢈ
3LQꢄꢁꢁꢉ
3LQꢄꢁꢁꢊ
3LQꢄꢁꢁꢋ
3LQꢄꢁꢈꢀ
ꢃ
3LQꢄꢁꢇꢉ 9''4
ꢃ
3LQꢄꢁꢇꢊ 1&ꢌ$ꢁꢅ
1&ꢌ2'7ꢁ ꢃ 3LQꢄꢀꢂꢂ
966
ꢃ
3LQꢄꢁꢇꢋ 966
ꢃ 3LQꢄꢀꢂꢇ
ꢃ 3LQꢄꢀꢋꢁ
ꢃ 3LQꢄꢀꢋꢅ
ꢃ 3LQꢄꢀꢋꢆ
ꢃ 3LQꢄꢀꢋꢂ
ꢃ 3LQꢄꢀꢋꢇ
ꢃ 3LQꢄꢀꢇꢁ
ꢃ 3LQꢄꢀꢇꢅ
ꢃ 3LQꢄꢀꢇꢆ
ꢃ 3LQꢄꢀꢇꢂ
ꢃ 3LQꢄꢀꢇꢇ
ꢃ 3LQꢄꢁꢀꢁ
ꢃ 3LQꢄꢁꢀꢅ
ꢃ 3LQꢄꢁꢀꢆ
ꢃ 3LQꢄꢁꢀꢂ
ꢃ 3LQꢄꢁꢀꢇ
ꢃ 3LQꢄꢁꢁꢁ
ꢃ 3LQꢄꢁꢁꢅ
ꢃ 3LQꢄꢁꢁꢆ
ꢃ 3LQꢄꢁꢁꢂ
ꢃ 3LQꢄꢁꢁꢇ
ꢃ
3LQꢄꢈꢀꢀ '4ꢅꢂ
'4ꢅꢅ
'46ꢉ
966
'4ꢅꢆ
'4ꢉꢀ
966
'46ꢆ
'4ꢉꢈ
966
'4ꢉꢇ
6$ꢈ
ꢃ
3LQꢄꢈꢀꢈ '0ꢉꢌ'46ꢁꢅ
ꢃ
3LQꢄꢈꢀꢉ 966
ꢃ
3LQꢄꢈꢀꢊ '4ꢅꢇ
ꢃ
3LQꢄꢈꢀꢋ '4ꢉꢉ
ꢃ
3LQꢄꢈꢁꢀ 966
ꢃ
3LQꢄꢈꢁꢈ 1&ꢌ'46ꢁꢉ
ꢃ
3LQꢄꢈꢁꢉ '4ꢉꢊ
ꢃ
3LQꢄꢈꢁꢊ 966
ꢃ
3LQꢄꢈꢁꢋ '4ꢆꢅ
ꢃ
3LQꢄꢈꢈꢀ 1&
ꢃ
3LQꢄꢈꢈꢈ 966
966
ꢃ
3LQꢄꢈꢈꢉ 1&ꢌ'46ꢁꢆ
'46ꢊ
'4ꢆꢀ
966
'4ꢆꢂ
'46ꢂ
966
ꢃ
3LQꢄꢈꢈꢊ '4ꢆꢉ
ꢃ
3LQꢄꢈꢈꢋ 966
ꢃ
3LQꢄꢈꢅꢀ '4ꢊꢁ
ꢃ
3LQꢄꢈꢅꢈ '0ꢂꢌ'46ꢁꢊ
ꢃ
3LQꢄꢈꢅꢉ 966
ꢃ
3LQꢄꢈꢅꢊ '4ꢊꢅ
'4ꢆꢇ
6'$
3LQꢄꢈꢅꢋ 9''63'
3LQꢄꢈꢉꢀ 6$ꢁ
3LQꢄꢈꢅꢇ 6$ꢀ
0337ꢀꢁꢂꢀ
6&/
Rev. 1.21, 2007-03
14
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 9 at any time.
TABLE 9
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
–1.0
–0.5
–0.5
–0.5
–55
+2.3
+2.3
+2.3
+2.3
+100
V
1)2)
1)2)
1)
VDDQ
VDDL
V
V
VIN, VOUT
TSTG
V
1)2)
°C
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 10
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
1)2)3)4)
TOPER
Operating Temperature
0
95
°C
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %
Rev. 1.21, 2007-03
15
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.2
DC Operating Conditions
This chapter contains the DC operating conditions tables.
TABLE 11
Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Max.
Operating temperature (ambient)
DRAM Case Temperature
TOPR
TCASE
TSTG
PBar
0
+65
+95
+100
+105
90
°C
°C
°C
kPa
%
—
1)2)3)4)
0
Storage Temperature
– 50
+69
10
—
5)
Barometric Pressure (operating & storage)
Operating Humidity (relative)
HOPR
—
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %.
5) Up to 3000 m.
TABLE 12
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Typ.
Max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
VDD
1.7
1.8
1.9
V
—
1)
VDDQ
VREF
1.7
1.8
1.9
V
2)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
VDDSPD
VIH(DC)
VIL (DC
IL
1.7
—
—
—
—
3.6
V
—
—
DC Input Logic High
V
REF + 0.125
V
V
5
DDQ + 0.3
V
DC Input Logic Low
)
– 0.30
– 5
REF – 0.125
V
—
3)
In / Output Leakage Current
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
.
Rev. 1.21, 2007-03
16
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3
AC Characteristics
This chapter describes the AC characteristics.
3.3.1
Speed Grades Definitions
This chapter contains the Speed Grades Definitions tables.
TABLE 13
Speed Grade Definition Speed Bins for DDR2–800E
Speed Grade
DDR2–800E
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–2.5
6–6–6
tCK
Parameter
Symbol
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
3
8
tCK
8
tCK
2.5
45
60
15
15
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
Rev. 1.21, 2007-03
17
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 14
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667C
DDR2–667D
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–3
–3S
4–4–4
5–5–5
tCK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3
8
3.75
3
8
tCK
3
8
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
57
12
12
70000
—
45
60
15
15
70000
—
—
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
TABLE 15
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
Speed Grade
DDR2–533C
DDR2–400B
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–3.7
–5
4–4–4
3–3–3
tCK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
3.75
45
8
5
8
tCK
8
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
40
55
15
15
70000
—
60
15
—
—
15
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
Rev. 1.21, 2007-03
18
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.2
AC Timing Parameters
This chapter contains the AC Timing Parameters.
TABLE 16
Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
9)
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
tAC
–400
–350
0.48
+400
+350
0.52
0.52
8000
—
ps
9)
tDQSCK
tCH.AVG
tCL.AVG
tCK.AVG
tDS.BASE
tDH.BASE
ps
10)11)
10)11)
10)11)
12)13)14)
12)13)15)
tCK.AVG
tCK.AVG
ps
0.48
2500
50
DQ and DM input setup time
DQ and DM input hold time
ps
125
—
ps
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG
tCK.AVG
ps
—
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
tDIPW
tHZ
tLZ.DQS
tLZ.DQ
0.35
—
—
9)16)
—
tAC.MAX
tAC.MAX
tAC.MAX
200
9)16)
9)16)
17)
tAC.MIN
2 x tAC.MIN
—
ps
ps
DQS-DQ skew for DQS & associated DQ signals tDQSQ
ps
18)
CK half pulse width
tHP
Min (tCH.ABS
,
__
ps
tCL.ABS
)
19)
20)
DQ hold skew factor
tQHS
tQH
—
300
—
ps
DQ/DQS output hold time from DQS
t
HP – tQHS
ps
Write command to DQS associated clock edges WL
RL – 1
– 0.25
nCK
tCK.AVG
—
21)
DQS latching rising transition to associated clock tDQSS
+ 0.25
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
—
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
ps
—
—
—
21)
—
21)
tDSH
0.2
—
tWPST
tWPRE
tLS.BASE
tLH.BASE
tRPRE
tRPST
tRAS
0.4
0.6
—
—
Write preamble
0.35
175
250
0.9
—
22)23)
Address and control input setup time
Address and control input hold time
Read preamble
—
23)24)
25)26)
25)27)
28)
—
ps
1.1
0.6
70000
—
tCK.AVG
tCK.AVG
ns
Read postamble
0.4
Active to precharge command
45
28)
Active to active command period for 1KB page
size products
tRRD
7.5
ns
28)
Active to active command period for 2KB page
size products
tRRD
10
—
ns
Rev. 1.21, 2007-03
19
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–800
Min.
Unit
Note1)2)3)4)5)6)7)
8)
Max.
28)
28)
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
35
—
—
—
—
—
—
—
—
—
—
ns
45
ns
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
nCK
ns
—
28)
15
29)30)
28)31)
28)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
7.5
nCK
ns
Internal write to read command delay
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
ns
28)
t
RFC +10
ns
200
2
nCK
nCK
—
—
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
tXARD
2
—
—
nCK
nCK
—
—
Exit active power-down mode to read command tXARDS
8 – AL
(slow exit, lower power)
32)
CKE minimum pulse width ( high and low pulse tCKE
width)
3
—
2
nCK
ODT turn-on delay
tAOND
tAON
2
nCK
ns
—
9)33)
ODT turn-on
tAC.MIN
t
AC.MAX + 0.7
2 x tCK.AVG
AC.MAX + 1
2.5
AC.MAX + 0.6
2.5 x tCK.AVG
AC.MAX + 1
ODT turn-on (Power down mode)
tAONPD
t
AC.MIN + 2
+
ns
—
t
ODT turn-off delay
tAOFD
tAOF
2.5
nCK
ns
—
34)35)
ODT turn-off
tAC.MIN
t
ODT turn-off (Power down mode)
tAOFPD
t
AC.MIN + 2
+
ns
—
t
ODT to power down entry latency
ODT to power down exit latency
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
tANPD
tAXPD
tMRD
tMOD
tOIT
3
8
2
0
0
––
nCK
nCK
nCK
ns
—
—
—
12
12
––
—
28)
28)
ns
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
t
LS + tCK .AVG
+
ns
—
tLH
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
Rev. 1.21, 2007-03
20
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 2.
13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 2.
16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 3.
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 3.
25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 1 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
Rev. 1.21, 2007-03
21
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND
34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD
.
.
35) When the device is operated with input clock jitter, this parameter needs to be derated by {–tJIT.DUTY.MAX – tERR(6-10PER).MAX} and {–tJIT.DUTY.MIN
– tERR(6-10PER).MIN } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter
into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps, tERR(6- 10PER).MAX = + 293 ps, tJIT.DUTY.MIN = – 106 ps and tJIT.DUTY.MAX = + 94 ps,
then tAOF.MIN(DERATED) = tAOF.MIN + {– tJIT.DUTY.MAX – tERR(6-10PER).MAX} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and tAOF.MAX(DERATED) = tAOF.MAX
+ {– tJIT.DUTY.MIN – tERR(6-10PER).MIN} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)
TABLE 17
Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
9)
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
tAC
–450
–400
0.48
+450
+400
0.52
0.52
8000
—
ps
9)
tDQSCK
tCH.AVG
tCL.AVG
tCK.AVG
tDS.BASE
tDH.BASE
ps
10)11)
10)11)
tCK.AVG
tCK.AVG
ps
0.48
3000
100
—
12)13)14)
DQ and DM input setup time
DQ and DM input hold time
ps
13)14)15)
175
—
ps
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG
tCK.AVG
ps
—
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
tDIPW
tHZ
tLZ.DQS
tLZ.DQ
0.35
—
—
9)16)
—
tAC.MAX
tAC.MAX
tAC.MAX
240
9)16)
9)16)
17)
tAC.MIN
2 x tAC.MIN
—
ps
ps
DQS-DQ skew for DQS & associated DQ signals tDQSQ
ps
18)
CK half pulse width
tHP
Min (tCH.ABS
,
__
ps
tCL.ABS
)
19)
20)
DQ hold skew factor
tQHS
tQH
—
340
—
ps
DQ/DQS output hold time from DQS
t
HP – tQHS
ps
Write command to DQS associated clock edges WL
RL–1
nCK
—
Rev. 1.21, 2007-03
22
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
21)
DQS latching rising transition to associated clock tDQSS
– 0.25
+ 0.25
tCK.AVG
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
—
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
ps
—
—
—
21)
—
21)
tDSH
0.2
—
tWPST
tWPRE
tLS.BASE
tLH.BASE
tRPRE
tRPST
tRAS
0.4
0.6
—
—
Write preamble
0.35
200
275
0.9
—
22)23)
Address and control input setup time
Address and control input hold time
Read preamble
—
23)24)
25)26)
25)27)
28)
—
ps
1.1
0.6
70000
—
tCK.AVG
tCK.AVG
ns
Read postamble
0.4
Active to precharge command
45
28)
Active to active command period for 1KB page
size products
tRRD
7.5
ns
28)
Active to active command period for 2KB page
size products
tRRD
10
—
ns
28)
28)
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
37.5
—
—
—
—
—
—
—
—
—
—
ns
50
ns
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
nCK
ns
—
28)
15
29)30)
28)31)
28)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
7.5
nCK
ns
Internal write to read command delay
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
ns
28)
t
RFC +10
ns
200
2
nCK
nCK
—
—
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
tXARD
2
—
—
nCK
nCK
—
—
Exit active power-down mode to read command tXARDS
7 – AL
(slow exit, lower power)
32)
CKE minimum pulse width ( high and low pulse tCKE
width)
3
—
2
nCK
ODT turn-on delay
tAOND
tAON
2
nCK
ns
—
9)33)
ODT turn-on
tAC.MIN
t
AC.MAX + 0.7
2 x tCK.AVG
AC.MAX + 1
2.5
AC.MAX + 0.6
2.5 x tCK.AVG
AC.MAX + 1
ODT turn-on (Power down mode)
tAONPD
t
AC.MIN + 2
+
ns
—
t
ODT turn-off delay
tAOFD
tAOF
2.5
nCK
ns
—
34)35)
ODT turn-off
tAC.MIN
t
ODT turn-off (Power down mode)
tAOFPD
t
AC.MIN + 2
+
ns
—
t
Rev. 1.21, 2007-03
23
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Min.
Unit
Note1)2)3)4)5)6)7)
8)
Max.
ODT to power down entry latency
ODT to power down exit latency
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
tANPD
tAXPD
tMRD
tMOD
tOIT
3
8
2
0
0
––
nCK
nCK
nCK
ns
—
—
—
12
12
––
—
28)
28)
ns
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
t
LS + tCK .AVG
+
ns
—
tLH
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 2.
13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 2.
16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
Rev. 1.21, 2007-03
24
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 3.
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 3.
25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 1 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND
34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD
.
.
35) When the device is operated with input clock jitter, this parameter needs to be derated by {–tJIT.DUTY.MAX – tERR(6-10PER).MAX} and {–tJIT.DUTY.MIN
– tERR(6-10PER).MIN } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter
into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps, tERR(6- 10PER).MAX = + 293 ps, tJIT.DUTY.MIN = – 106 ps and tJIT.DUTY.MAX = + 94 ps,
then tAOF.MIN(DERATED) = tAOF.MIN + {– tJIT.DUTY.MAX – tERR(6-10PER).MAX} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and tAOF.MAX(DERATED) = tAOF.MAX
+ {– tJIT.DUTY.MIN – tERR(6-10PER).MIN} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)
Rev. 1.21, 2007-03
25
09152006-J5FK-C565
5(ꢄꢄEHJLꢄQꢄSRLQWꢄ
7
ꢄ
Hꢄ
ꢄSRLꢄQW
ꢄ
92/
ꢄꢍꢄꢈ[ꢄP9
ꢄꢍꢄ[ꢄP9
ꢄ
977ꢄꢃꢄ[ꢄP
9ꢄ
92/
ꢄ
977ꢄꢃꢄꢈ[ꢄP9ꢄ
7ꢁꢄ 7ꢈꢄ
W+=ꢎW536
7ꢄꢄHQG
ꢄSRLQ
Wꢄꢄ
ꢄꢈꢏ
7ꢁꢃ7ꢈꢄ
W/=ꢎW
535(ꢄEꢄ
Wꢄꢄ
ꢄꢈꢏ7
ꢁꢃ7ꢈꢄ
ꢄ
W'+ꢄ
W'6ꢄ
ꢄ
9,ꢄ+ꢐDFꢑꢄꢄPLQ
9,ꢄ+ꢐGFꢑꢄꢄPLQ
95ꢄ ()ꢐGFꢑꢄ
ꢄ
ꢄ
9,ꢄ/ꢐGFꢑꢄꢄPD[
9,ꢄ/ꢐDFꢑꢄꢄPD[
96ꢄ 6ꢄ
ꢄ
ꢄ
W,+ꢄ
W,+
ꢄ
W,6ꢄ
W,6ꢄ
ꢄ
ꢑꢄ
ꢑꢄ
9,ꢄ/ꢐGF ꢄPD[
ꢄ
ꢄ
ꢑꢄ
9,ꢄ/ꢐDF ꢄPD[
ꢑꢄ
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 2
Method for calculating transitions and endpoint
92+
ꢄꢃꢄ[ꢄP9
ꢄ
977ꢄꢍꢄꢈ[ꢄP9ꢄ
977ꢄꢍꢄ[ꢄP9ꢄ
92+
ꢄꢃꢄꢈ[ꢄP9ꢄ
W/=ꢄ
W53
W+=ꢄ
W536 QG
7ꢁꢄ 7ꢈꢄ
HJLQꢄSRLQ
FIGURE 3
Differential input waveform timing - tDS and tDS
'46ꢄ
'46
W'+ꢄ
W'6ꢄ
9'ꢄ '4
FIGURE 4
Differential input waveform timing - tlS and tlH
&.ꢄ
&.ꢄ
9'ꢄ '4
9,ꢄ+ꢐDF ꢄPLQꢄ
9,ꢄ+ꢐGF ꢄPLQꢄ
95ꢄ ()ꢐGFꢑꢄ
96ꢄ 6ꢄ
Rev. 1.21, 2007-03
26
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 18
Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–500
2
+500
—
ps
—
—
—
—
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
—
8)18)
Auto-Precharge write recovery + precharge
time
tDAL
9)
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
—
—
—
ns
ps
ps
10)
11)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
DQ and DM input hold time (single ended data
strobe)
DH1(base)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–450
0.35
—
—
tCK
ps
tCK
ps
—
—
tDQSCK
+450
—
DQS input low (high) pulse width (write cycle) tDQSL,H
—
11)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
300
Write command to 1st DQS latching transition tDQSS
– 0.25
100
+ 0.25
—
tCK
—
11)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
11)
DQ and DM input setup time (single ended data tDS1(base)
strobe)
–25
0.2
—
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
tCK
—
—
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
—
—
tCK
ns
ns
Four Activate Window period
tFAW
37.5
—
13)
50
12)
13)
11)
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
375
0.6
Address and control input pulse width
(each input)
—
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
250
—
ps
ps
ps
tCK
ns
—
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
—
—
—
tOIT
12
Data output hold time from DQS
tQH
t
HP –tQHS
—
Rev. 1.21, 2007-03
27
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Min.
Unit
Note1)2)3)4)5)
6)7)
Max.
Data hold skew factor
tQHS
tREFI
—
—
—
75
400
7.8
3.9
—
ps
µs
µs
ns
—
14)15)
Average periodic refresh Interval
16)18)
17)
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1tCK
—
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
ns
—
tRP
15 + 1tCK
0.9
—
—
14)
tRPRE
tRPST
tRRD
1.1
0.60
—
14)
Read postamble
0.40
7.5
14)18)
16)20)
Active bank A to Active bank B command
period
10
—
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
—
tWPRE
tWPST
tWR
0.25 x tCK
0.40
15
—
—
19)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
—
20)
Write recovery time for write with Auto-
Precharge
WR
t
WR/tCK
tCK
21)
22)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
22)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
—
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
—
—
200
tCK
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
Rev. 1.21, 2007-03
28
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 3 “Ordering Information for RoHS
Compliant Products” on Page 5.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
TABLE 19
Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–600
2
+600
—
ps
—
—
—
—
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
—
8)22)
Auto-Precharge write recovery + precharge
time
tDAL
9)
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
275
––
––
—
ns
ps
ps
10)
11)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
DQ and DM input hold time (single ended data
strobe)
DH1(base)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–500
0.35
—
—
tCK
ps
tCK
ps
—
—
tDQSCK
+500
—
DQS input low (high) pulse width (write cycle) tDQSL,H
—
11)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
350
Write command to 1st DQS latching transition tDQSS
– 0.25
150
+ 0.25
—
tCK
—
11)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
11)
DQ and DM input setup time (single ended
data strobe)
t
DS1(base)
–25
—
ps
Rev. 1.21, 2007-03
29
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
—
—
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
—
—
tCK
ns
ns
Four Activate Window period
tFAW
37.5
—
13)
50
12)
13)
11)
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
475
0.6
Address and control input pulse width
(each input)
—
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
350
—
ps
ps
ps
tCK
ns
—
ps
µs
µs
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
—
—
—
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
—
450
7.8
—
14)15)
Average periodic refresh Interval
tREFI
16)18)
17)
—
3.9
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
75
—
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1tCK
—
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
ns
—
tRP
15 + 1tCK
0.9
—
—
14)
tRPRE
tRPST
tRRD
1.1
0.60
—
14)
Read postamble
0.40
7.5
14)18)
16)20)
Active bank A to Active bank B command
period
10
—
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
—
tWPRE
tWPST
tWR
0.25 x tCK
0.40
15
—
—
19)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
—
20)
Write recovery time for write with Auto-
Precharge
WR
t
WR/tCK
tCK
21)
22)
Internal Write to Read command delay
tWTR
10
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
22)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
—
Rev. 1.21, 2007-03
30
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–400
Min.
Unit
Note1)2)3)4)5)
6)7)
Max.
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
—
—
200
tCK
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 3 “Ordering Information for RoHS
Compliant Products” on Page 5.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
Rev. 1.21, 2007-03
31
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.3
ODT AC Electrical Characteristics
This chapter contains the ODT AC electrical characteristics tables.
TABLE 20
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
—
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK +
t
AC.MAX + 1 ns
—
2.5
2.5
—
2)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK +
tAC.MAX + 1 ns
—
—
—
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD
.
.
TABLE 21
ODT AC Characteristics and Operating Conditions for DDR2-533/DDR2-400
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
—
1)
ODT turn-on
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK +
t
AC.MAX + 1 ns
—
2.5
2.5
—
2)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK +
tAC.MAX + 1 ns
—
—
—
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
.
Both are measured from tAOFD
.
Rev. 1.21, 2007-03
32
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.4
IDD Specifications and Conditions
This chapter describes the IDD Specifications and Conditions.
TABLE 22
DD Measurement Conditions
I
Parameter
Symbol Note1)2)
3)4)5)6)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH
between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN
,
t
RCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2Q
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
IDD5D
t
CK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Rev. 1.21, 2007-03
33
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol Note1)2)
3)4)5)6)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are guaranteed up to TCASE of
85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA.
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) Definitions for IDD see Table 23
3) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
4) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh)
5) All current measurements includes Register and PLL current consumption
6) For details and notes see the relevant QIMONDA component data sheet
TABLE 23
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are VREF = VDDQ /2
STABLE
FLOATING
SWITCHING
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Rev. 1.21, 2007-03
34
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 24
DD Specification HYS72T[32000/64001/64020]HR–2.5–A
I
Product Type
Unit
Note1)
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank
–2.5
1 Rank
–2.5
2 Ranks
–2.5
Symbol
Max.
Max.
Max.
2)
IDD0
1110
1200
880
1780
1960
1330
520
1150
1240
1330
520
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
480
3)
IDD2Q
750
1060
1330
830
1060
1330
830
3)
IDD3N
880
3)
IDD3P(MRS= 0)
IDD3P(MRS= 1)
IDD4R
630
3)
480
520
520
2)
1560
1650
1290
480
2680
2860
2140
540
1600
1690
1330
540
2)
IDD4W
IDD5B
2)
3)4)
3)4)
2)
IDD5D
IDD6
35
70
70
IDD7
1830
3220
1870
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD mode
4) Values for 0 °C < TCASE ≤ 85 °C
Rev. 1.21, 2007-03
35
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 25
DD Specification HYS72T[32000/64001/64020]HR–3–A
I
Product Type
Organization
HYS72T32000HR–3–A
HYS72T64001HR–3–A
HYS72T64020HR–3–A
Unit Note1)
256MB
×72
512MB
×72
512MB
×72
1 Rank
–3
1 Rank
–3
2 Ranks
–3
Symbol
Max.
Max.
Max.
2)
IDD0
970
1060
790
430
660
790
560
430
1380
1420
1240
440
35
1770
1950
1410
680
1010
1100
1200
470
mA
2)
IDD1
mA
3)
IDD2N
mA
3)
IDD2P
mA
3)
IDD2Q
1140
1410
940
930
mA
3)
IDD3N
1200
730
mA
3)
IDD3P(MRS= 0)
IDD3P(MRS= 1)
IDD4R
mA
3)
690
480
mA
2)
2580
2670
2310
700
1420
1460
1280
490
mA
2)
IDD4W
IDD5B
mA
2)
mA
3)4)
IDD5D
mA
3)4)
IDD6
70
70
mA
2)
IDD7
1690
3210
1730
mA
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD mode
4) Values for 0 °C ≤ TCASE ≤ 85 °C
Rev. 1.21, 2007-03
36
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 26
DD Specification HYS72T[32000/64001/64020]HR–3S–A
I
Product Type
Organization
HYS72T32000HR–3S–A
HYS72T64001HR–3S–A
HYS72T64020HR–3S–A
Unit Note1)
256MB
×72
512MB
×72
512MB
×72
1 Rank
–3S
1 Rank
–3S
2 Ranks
–3S
Symbol
Max.
Max.
Max.
2)
IDD0
940
1020
790
430
660
790
560
430
1380
1420
1240
440
35
1710
1870
1410
680
980
mA
2)
IDD1
1060
1200
470
mA
3)
IDD2N
mA
3)
IDD2P
mA
3)
IDD2Q
1140
1410
940
930
mA
3)
IDD3N
1200
730
mA
3)
IDD3P(MRS= 0)
IDD3P(MRS= 1)
IDD4R
mA
3)
690
480
mA
2)
2580
2670
2310
700
1420
1460
1280
490
mA
2)
IDD4W
IDD5B
mA
2)
mA
3)4)
IDD5D
mA
3)4)
IDD6
70
70
mA
2)
IDD7
1630
3080
1670
mA
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD mode
4) Values for 0 °C ≤ TCASE ≤ 85 °C
Rev. 1.21, 2007-03
37
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 27
I
DD Specification for HYS72T[32000/64001/64020]HR–3.7–A
Product Type HYS72T32000HR–3.7–A
HYS72T64001HR–3.7–A
HYS72T64020HR–3.7–A
Unit Note1)
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank
–3.7
1 Rank
–3.7
2 Ranks
–3.7
Symbol
Max.
Max.
Max.
2)
IDD0
830
870
650
370
560
650
470
370
1140
1190
1140
380
35
1490
1580
1130
570
860
910
960
400
780
960
620
400
1180
1220
1180
440
70
mA
2)
IDD1
mA
3)
IDD2N
mA
3)
IDD2P
mA
3)
IDD2Q
950
mA
3)
IDD3N
1130
790
mA
3)
IDD3P(MRS= 0)
IDD3P(MRS= 1)
IDD4R
mA
3)
570
mA
2)
2120
2210
2120
610
mA
2)
IDD4W
IDD5B
mA
2)
mA
3)4)
IDD5D
mA
3)4)
IDD6
70
mA
2)
IDD7
1550
2930
1580
mA
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD mode
4) Values for 0 °C ≤ TCASE ≤ 85 °C
Rev. 1.21, 2007-03
38
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 28
DD Specification for HYS72T[32000/64001/64020]HR-5-A
I
Product Type
Organization
HYS72T32000HR–5–A
HYS72T64001HR–5–A
HYS72T64020HR–5–A
Unit Note1)
256MB
×72
512MB
×72
512MB
×72
1 Rank
–5
1 Rank
–5
2 Ranks
–5
Symbol
Max.
Max.
Max.
2)
IDD0
730
770
530
310
460
550
390
310
910
950
1040
330
35
1310
1400
910
760
810
780
350
640
820
510
350
940
990
1080
380
70
mA
2)
IDD1
mA
3)
IDD2N
mA
3)
IDD2P
480
mA
3)
IDD2Q
770
mA
3)
IDD3N
950
mA
3)
IDD3P(MRS= 0)
IDD3P(MRS= 1)
IDD4R
640
mA
3)
480
mA
2)
1670
1760
1940
510
mA
2)
IDD4W
IDD5B
mA
2)
mA
3)4)
IDD5D
mA
3)4)
IDD6
70
mA
2)
IDD7
1400
2660
1440
mA
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD mode
4) Values for 0 °C ≤ TCASE ≤ 85 °C
Rev. 1.21, 2007-03
39
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
Table 29 “SPD Codes for PC2–6400R–666” on Page 40
Table 30 “SPD Codes for PC2–5300R–444” on Page 45
Table 31 “SPD Codes for PC2–5300R–555” on Page 49
Table 32 “SPD Codes for PC2–4200R–444” on Page 53
Table 33 “SPD Codes for PC2–3200R–333” on Page 57
TABLE 29
SPD Codes for PC2–6400R–666
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–6400R–666 PC2–6400R–666 PC2–6400R–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
48
00
05
25
40
02
80
08
08
0D
0B
60
48
00
05
25
40
02
80
08
08
0D
0A
61
48
00
05
25
40
02
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Rev. 1.21, 2007-03
40
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–6400R–666 PC2–6400R–666 PC2–6400R–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
82
08
08
00
0C
04
70
01
01
04
03
30
45
3D
50
3C
1E
3C
2D
40
17
25
05
12
3C
1E
1E
82
04
04
00
0C
04
70
01
01
05
03
30
45
3D
50
3C
1E
3C
2D
80
17
25
05
12
3C
1E
1E
82
08
08
00
0C
04
70
01
01
05
03
30
45
3D
50
3C
1E
3C
2D
40
17
25
05
12
3C
1E
1E
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Rev. 1.21, 2007-03
41
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–6400R–666 PC2–6400R–666 PC2–6400R–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Analysis Characteristics
00
00
3C
4B
80
14
1E
0F
53
82
5B
2B
29
29
36
19
4E
17
26
C4
8C
70
B0
12
F7
7F
7F
00
00
3C
4B
80
14
1E
0F
53
82
5B
2B
29
29
36
19
4E
17
26
C4
8C
70
B0
12
31
7F
7F
00
00
3C
4B
80
14
1E
0F
53
82
5B
2B
29
29
36
19
4E
17
26
C4
8C
70
B0
12
F9
7F
7F
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Rev. 1.21, 2007-03
42
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–6400R–666 PC2–6400R–666 PC2–6400R–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
37
32
54
33
32
30
30
30
48
52
32
2E
35
41
20
20
20
20
3x
xx
37
32
54
36
34
30
30
31
48
52
32
2E
35
41
20
20
20
20
3x
xx
37
32
54
36
34
30
32
30
48
52
32
2E
35
41
20
20
20
20
3x
xx
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Rev. 1.21, 2007-03
43
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–6400R–666 PC2–6400R–666 PC2–6400R–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
93
94
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
00
FF
xx
xx
xx
00
FF
xx
xx
xx
00
FF
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.21, 2007-03
44
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 30
SPD Codes for PC2–5300R–444
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–5300R–444 PC2–5300R–444 PC2–5300R–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
48
00
05
30
45
02
82
08
08
00
0C
04
38
01
01
04
03
30
45
80
08
08
0D
0B
60
48
00
05
30
45
02
82
04
04
00
0C
04
38
01
01
05
03
30
45
80
08
08
0D
0A
61
48
00
05
30
45
02
82
08
08
00
0C
04
38
01
01
05
03
30
45
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
Rev. 1.21, 2007-03
45
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–5300R–444 PC2–5300R–444 PC2–5300R–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
t
t
t
t
t
t
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
50
60
30
1E
30
2D
40
20
27
10
17
3C
1E
1E
00
00
39
4B
80
18
22
0F
52
82
47
25
29
50
60
30
1E
30
2D
80
20
27
10
17
3C
1E
1E
00
00
39
4B
80
18
22
0F
52
82
47
25
29
50
60
30
1E
30
2D
40
20
27
10
17
3C
1E
1E
00
00
39
4B
80
18
22
0F
52
82
47
25
29
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
Rev. 1.21, 2007-03
46
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–5300R–444 PC2–5300R–444 PC2–5300R–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
∆T3N (DT3N)
25
2F
19
44
17
24
C4
8C
68
94
12
A4
7F
7F
7F
7F
7F
51
00
00
xx
25
2F
19
44
17
24
C4
8C
68
94
12
DE
7F
7F
7F
7F
7F
51
00
00
xx
25
2F
19
44
17
24
C4
8C
68
94
12
A6
7F
7F
7F
7F
7F
51
00
00
xx
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
37
32
54
33
32
30
37
32
54
36
34
30
37
32
54
36
34
30
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Rev. 1.21, 2007-03
47
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–5300R–444 PC2–5300R–444 PC2–5300R–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 7
30
30
48
52
33
41
20
20
20
20
20
20
6x
xx
xx
xx
xx
00
FF
30
31
48
52
33
41
20
20
20
20
20
20
6x
xx
xx
xx
xx
00
FF
32
30
48
52
33
41
20
20
20
20
20
20
6x
xx
xx
xx
xx
00
FF
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.21, 2007-03
48
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 31
SPD Codes for PC2–5300R–555
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–5300R–555 PC2–5300R–555 PC2–5300R–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
48
00
05
30
45
02
82
08
08
00
0C
04
38
01
01
04
03
3D
80
08
08
0D
0B
60
48
00
05
30
45
02
82
04
04
00
0C
04
38
01
01
05
03
3D
80
08
08
0D
0A
61
48
00
05
30
45
02
82
08
08
00
0C
04
38
01
01
05
03
3D
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
CK @ CLMAX -1 (Byte 18) [ns]
Rev. 1.21, 2007-03
49
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–5300R–555 PC2–5300R–555 PC2–5300R–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
t
t
t
t
t
t
t
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
50
50
60
3C
1E
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
4B
80
18
22
0F
52
82
43
25
50
50
60
3C
1E
3C
2D
80
20
27
10
17
3C
1E
1E
00
00
3C
4B
80
18
22
0F
52
82
43
25
50
50
60
3C
1E
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
4B
80
18
22
0F
52
82
43
25
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
Rev. 1.21, 2007-03
50
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–5300R–555 PC2–5300R–555 PC2–5300R–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
∆T2P (DT2P)
29
25
2F
19
44
17
22
C4
8C
68
94
12
D1
7F
7F
7F
7F
7F
51
00
00
xx
29
25
2F
19
44
17
22
C4
8C
68
94
12
0B
7F
7F
7F
7F
7F
51
00
00
xx
29
25
2F
19
44
17
22
C4
8C
68
94
12
D3
7F
7F
7F
7F
7F
51
00
00
xx
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
37
32
54
33
32
37
32
54
36
34
37
32
54
36
34
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Rev. 1.21, 2007-03
51
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–5300R–555 PC2–5300R–555 PC2–5300R–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 6
30
30
30
48
52
33
53
41
20
20
20
20
20
3x
xx
xx
xx
xx
00
FF
30
30
31
48
52
33
53
41
20
20
20
20
20
3x
xx
xx
xx
xx
00
FF
30
32
30
48
52
33
53
41
20
20
20
20
20
3x
xx
xx
xx
xx
00
FF
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.21, 2007-03
52
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 32
SPD Codes for PC2–4200R–444
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–4200R–444 PC2–4200R–444 PC2–4200R–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
48
00
05
3D
50
02
82
08
08
00
0C
04
38
00
01
04
01
3D
80
08
08
0D
0B
60
48
00
05
3D
50
02
82
04
04
00
0C
04
38
00
01
05
01
3D
80
08
08
0D
0A
61
48
00
05
3D
50
02
82
08
08
00
0C
04
38
00
01
05
01
3D
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
CK @ CLMAX -1 (Byte 18) [ns]
Rev. 1.21, 2007-03
53
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–4200R–444 PC2–4200R–444 PC2–4200R–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
t
t
t
t
t
t
t
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
50
50
60
3C
1E
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
4B
80
1E
28
0F
55
82
37
1F
50
50
60
3C
1E
3C
2D
80
25
37
10
22
3C
1E
1E
00
00
3C
4B
80
1E
28
0F
55
82
37
1F
50
50
60
3C
1E
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
4B
80
1E
28
0F
55
82
37
1F
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
Rev. 1.21, 2007-03
54
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–4200R–444 PC2–4200R–444 PC2–4200R–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
∆T2P (DT2P)
21
1D
28
14
2C
15
21
C4
8C
61
78
11
A8
7F
7F
7F
7F
7F
51
00
00
xx
21
1D
28
14
2C
15
21
C4
8C
61
78
11
E2
7F
7F
7F
7F
7F
51
00
00
xx
21
1D
28
14
2C
15
21
C4
8C
61
78
11
AA
7F
7F
7F
7F
7F
51
00
00
xx
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
37
32
54
33
32
37
32
54
36
34
37
32
54
36
34
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Rev. 1.21, 2007-03
55
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–4200R–444 PC2–4200R–444 PC2–4200R–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 6
30
30
30
48
52
33
2E
37
41
20
20
20
20
4x
xx
xx
xx
xx
00
FF
30
30
31
48
52
33
2E
37
41
20
20
20
20
4x
xx
xx
xx
xx
00
FF
30
32
30
48
52
33
2E
37
41
20
20
20
20
4x
xx
xx
xx
xx
00
FF
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.21, 2007-03
56
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 33
SPD Codes for PC2–3200R–333
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–3200R–333 PC2–3200R–333 PC2–3200R–333
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
48
00
05
50
60
02
82
08
08
00
0C
04
38
00
01
04
01
50
60
80
08
08
0D
0B
60
48
00
05
50
60
02
82
04
04
00
0C
04
38
00
01
05
01
50
60
80
08
08
0D
0A
61
48
00
05
50
60
02
82
08
08
00
0C
04
38
00
01
05
01
50
60
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
Rev. 1.21, 2007-03
57
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–3200R–333 PC2–3200R–333 PC2–3200R–333
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
t
t
t
t
t
t
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
50
60
3C
1E
3C
28
40
35
47
15
27
3C
28
1E
00
00
37
4B
80
23
2D
0F
53
82
2F
19
21
50
60
3C
1E
3C
28
80
35
47
15
27
3C
28
1E
00
00
37
4B
80
23
2D
0F
53
82
2F
19
21
50
60
3C
1E
3C
28
40
35
47
15
27
3C
28
1E
00
00
37
4B
80
23
2D
0F
53
82
2F
19
21
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
Rev. 1.21, 2007-03
58
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–3200R–333 PC2–3200R–333 PC2–3200R–333
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
∆T3N (DT3N)
19
20
14
26
14
1F
C4
8C
59
5C
11
D9
7F
7F
7F
7F
7F
51
00
00
xx
19
20
14
26
14
1F
C4
8C
59
5C
11
13
7F
7F
7F
7F
7F
51
00
00
xx
19
20
14
26
14
1F
C4
8C
59
5C
11
DB
7F
7F
7F
7F
7F
51
00
00
xx
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
37
32
54
33
32
30
37
32
54
36
34
30
37
32
54
36
34
30
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Rev. 1.21, 2007-03
59
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
256MB
×72
512MB
×72
512MB
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC2–3200R–333 PC2–3200R–333 PC2–3200R–333
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 7
30
30
48
52
35
41
20
20
20
20
20
20
4x
xx
xx
xx
xx
00
FF
30
31
48
52
35
41
20
20
20
20
20
20
4x
xx
xx
xx
xx
00
FF
32
30
48
52
35
41
20
20
20
20
20
20
4x
xx
xx
xx
xx
00
FF
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.21, 2007-03
60
09152006-J5FK-C565
ꢁꢄ
ꢁꢈꢀꢄ
ꢀꢒꢁꢄ
ꢂꢄ
ꢁꢒꢈ
ꢊ
ꢆꢆꢄ
ꢅꢄ
ꢁꢒꢆꢄ
ꢀꢒꢁꢄ
ꢁ
ꢈꢉꢀꢄ
ꢈ
ꢁꢄ
ꢐꢅꢑꢄ
'
H
R
WD
L
OꢄR
IꢄF
Q
WD
FWVꢄ
ꢀꢒꢋꢄ
ꢀꢒ
ꢀꢆꢄ
ꢀꢒꢁꢄ$ꢄ %ꢄ &ꢄ
%
ꢄ
PD
ꢀꢒꢉ
ꢄ
D
*
ꢊꢆꢆ
XUU
[ꢒꢄ
OORZHGꢄ
/'ꢀꢇ
ꢄ
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 5
Package Outline Raw Card A L-DIM-240-11
ꢁ
ꢁ
ꢅ
ꢈ
ꢅꢒꢅ
ꢋꢒꢇ
ꢆꢄ
ꢆꢄ
ꢈꢒꢂ
ꢄ
0$;ꢒꢄ
ꢉꢄ
ꢈꢒꢆꢄ
&ꢄ
ꢆꢄ
$ꢄ
%ꢄ
ꢁꢄ
Rev. 1.21, 2007-03
09152006-J5FK-C565
61
ꢁꢄ
ꢁ
ꢈꢀꢄ
ꢀꢒꢁꢄ
ꢂꢄ
ꢁꢒꢈ
ꢊ
ꢆꢆꢄ
ꢅꢄ
ꢁꢒꢆꢄ
ꢀꢒꢁꢄ
ꢁ
ꢈꢉꢀꢄ
ꢈ
ꢁꢄ
ꢐꢅꢑꢄ
'
H
R
FR
ꢁꢄ
WD
L
Oꢄ
Iꢄ
Q
WD
FWVꢄ
ꢀꢒꢋꢄ
ꢀꢒꢀꢆꢄ
ꢀꢒꢁꢄ$ꢄ %ꢄ &ꢄ
%
ꢄ
PD
ꢒꢄ
ꢀꢒꢉ
ꢄ
D
*
ꢊꢆꢊ
XUU
[
OORZHGꢄ
/'ꢀꢇ
ꢄ
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 6
Package Outline Raw Card B-G L-DIM-240-12
ꢁ
ꢁ
ꢅ
ꢈ
ꢅꢒꢅ
ꢋꢒꢇ
ꢆꢄ
ꢆꢄ
ꢉꢄ
0$;ꢒꢄ
ꢉꢄ
ꢈꢒꢆꢄ
&ꢄ
ꢆꢄ
$ꢄ
%ꢄ
Rev. 1.21, 2007-03
09152006-J5FK-C565
62
ꢁꢄ
ꢁꢈꢀꢄ
ꢂꢄ
ꢀꢒꢁꢄ
ꢁꢒ
ꢈ
ꢊ
ꢆꢆꢄ
ꢅꢄ
ꢀꢒꢁꢄ
ꢁꢒꢆꢄ
ꢁ
ꢈꢉꢀꢄ
ꢈ
ꢁꢄ
ꢐꢅꢑꢄ
'H
D
R
W
L
OꢄR
IꢄF
Q
WDFWVꢄ
ꢀꢒꢋꢄ
ꢀꢒ
ꢀꢆꢄ
ꢀꢒꢁꢄ$ꢄ %ꢄ &ꢄ
%
ꢄP
D
ꢒ
ꢉꢄDOORZHG
ꢄ
*
'ꢀꢇꢊꢆ
XUU
[ꢒꢄꢀ
/
ꢂꢄ
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 7
Package Outline Raw Card C L-DIM-240-13
ꢁ
ꢁ
ꢅꢅ
ꢈꢋ
ꢒ
ꢒ
ꢅ
ꢇ
ꢆꢄ
ꢆꢄ
ꢉꢄ0$;ꢒꢄ
ꢉꢄ
ꢈꢒꢆꢄ
&ꢄ
ꢆꢄ
$ꢄ
%ꢄ
ꢁꢄ
Rev. 1.21, 2007-03
09152006-J5FK-C565
63
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some propriatory coding. Table 34 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 35 and for components in Table 36.
TABLE 34
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64
0
2
0
0
K
A
M
C
–5
–5
–A
512
16
—
TABLE 35
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
QIMONDA
HYS
Constant
Modul Prefix
2
Module Data Width [bit]
64
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
2 GByte
4 GByte
5
6
7
8
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
Package,
Lead-Free Status
9
Module Type
D
M
R
U
F
SO-DIMM
Micro-DIMM
Registered
Unbuffered
Fully Buffered
Rev. 1.21, 2007-03
64
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–2.5
–3
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
–3S
–3.7
–5
11
Die Revision
–A
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 36
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
QIMONDA
HYB
Constant
Component Prefix
2
3
4
Interface Voltage [V]
DRAM Technology
18
T
SSTL_18
DDR2
256 Mbit
512 Mbit
1 Gbit
2 Gbit
×4
Component Density [Mbit]
256
512
1G
2G
40
80
16
0 .. 9
A
5+6
Number of I/Os
×8
×16
7
8
Product Variations
Die Revision
Look up table
First
B
Second
9
Package,
C
FBGA,
Lead-Free Status
lead-containing
F
FBGA, lead-free
DDR2-800 6-6-6
DDR2-667 4-4-4
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
10
Speed Grade
–2.5
–3
–3S
–3.7
–5
Rev. 1.21, 2007-03
65
09152006-J5FK-C565
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Rev. 1.21, 2007-03
66
09152006-J5FK-C565
Internet Data Sheet
Edition 2007-03
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com
相关型号:
©2020 ICPDF网 联系我们和版权申明