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HYB18T256161BF-28 [QIMONDA]

256-Mbit x16 DDR2 SDRAM; 256 - Mbit的X16 DDR2 SDRAM
HYB18T256161BF-28
型号： HYB18T256161BF-28
厂家： QIMONDA AG    QIMONDA AG
描述：

256-Mbit x16 DDR2 SDRAM
256 - Mbit的X16 DDR2 SDRAM

存储 内存集成电路 动态存储器 双倍数据速率 时钟
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中文：  中文翻译
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June 2007  
HYB18T256161BF–20/25/28  
256-Mbit x16 DDR2 SDRAM  
DDR2 SDRAM  
RoHS compliant  
Internet Data Sheet  
Rev. 1.20  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
HYB18T256161BF–20/25/28  
Revision History: 2007-06, Rev. 1.20  
Page  
Subjects (major changes since last revision)  
Typos corrected  
All  
Previous Revision: Rev. 1.0, 2006-09  
All Final Data Sheet  
Previous Revision: Rev. 0.60, 2006-09  
94-101  
added chapter 7 explaining AC timing measurement condition (reference load ; slew rate ; set up & hold timing  
references ; derating values for input /command ,data )  
82-86  
All  
setup & hold timings are changed with reference to Industrial standard definition  
removed all the occurances of RDQS as it in not used in graphics (x16)  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
techdoc@qimonda.com  
qag_techdoc_rev400 / 3.2 QAG / 2006-08-01  
11232006-QP6X-6EM0  
2
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
1
Overview  
This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family for graphics applications and  
describes its main characteristics.  
1.1  
Features  
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:  
•
•
•
•
1.8 V ± 0.1V VDD for [–20/–25/–28]  
1.8 V ± 0.1V VDDQ for [–20/–25/–28]  
DRAM organizations with 16 data in/outputs  
Double Data Rate architecture:  
•
•
Data masks (DM) for write data  
Posted CAS by programmable additive latency for better  
command and data bus efficiency  
Off-Chip-Driver impedance adjustment (OCD) and On-  
Die-Termination (ODT) for better signal quality.  
Auto-Precharge operation for read and write bursts  
Auto-Refresh, Self-Refresh and power saving Power-  
Down modes  
Average Refresh Period 7.8 μs at a TCASE lower than 85°C,  
3.9 μs between 85°C and 95°C  
Full Strength and reduced Strength (60%) Data-Output  
•
– two data transfers per clock cycle  
– four internal banks for concurrent operation  
Programmable CAS Latency: 3, 4, 5, 6, 7  
Programmable Burst Length: 4 and 8  
•
•
•
•
•
•
Differential clock inputs (CK and CK)  
•
•
Bi-directional, differential data strobes (DQS and DQS) are  
transmitted / received with data. Edge aligned with read  
data and center-aligned with write data.  
DLL aligns DQ and DQS transitions with clock  
DQS can be disabled for single-ended data strobe  
operation  
Drivers  
1K page size  
•
•
•
•
•
Package: P-TFBGA-84  
RoHS Compliant Products1)  
•
Commands entered on each positive clock edge, data and  
data mask are referenced to both edges of DQS  
TABLE 1  
Ordering Information for RoHS compliant products  
Product Number  
Org.  
Clock (MHz)  
Package  
HYB18T256161BF–20/25/28  
×16  
500/400/350  
P-TFBGA-84  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 1.20, 2007-06  
3
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
1.2  
Description  
The 256-Mb DDR2 DRAM is a high-speed Double-Data-Rate-Two CMOS Synchronous DRAM device containing 268,435,456  
bits and internally configured as a quad bank DRAM. The 256-Mb device is organized as 4 Mbit × 16 I/O × 4 banks chip. These  
synchronous devices achieve high speed transfer rates starting at 700 Mb/sec/pin for general applications.  
The device is designed to comply with all DDR2 DRAM key features:  
1. posted CAS with additive latency,  
2. write latency = read latency - 1,  
3. normal and weak strength data-output driver,  
4. Off-Chip Driver (OCD) impedance adjustment  
5. On-Die Termination (ODT) function.  
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched  
at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or  
differential DQS-DQS pair in a source synchronous fashion.  
A 15-bit address bus is used to convey row, column and bank address information in a RAS-CAS multiplexing style.  
An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.  
The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.  
The DDR2 SDRAM is available in P-TFBGA package.  
Rev. 1.20, 2007-06  
4
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
2
Configuration  
2.1  
Chip Configuration  
The chip configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Ball# and Buffer Type  
columns are explained in Table 3 and Table 4 respectively. The ball numbering for the FBGA package is depicted in Figure 1.  
TABLE 2  
Chip Configuration of DDR2 SDRAM  
Ball#  
Name  
Ball Type Buffer Type Function  
Clock Signals  
J8  
CK  
CK  
I
I
SSTL  
SSTL  
Clock Signal CK, Complementary Clock Signal CK  
Note: CK and CK are differential system clock inputs. All  
address and control inputs are sampled on the  
crossing of the positive edge of CK and negative  
edge of CK. Output (read) data is referenced to  
the crossing of CK and CK (both direction of  
crossing)  
K8  
K2  
CKE  
I
SSTL  
Clock Enable  
Note: CKE HIGH activates and CKE LOW deactivates  
internal clock signals and device input buffers and  
output drivers. Taking CKE LOW provides  
Precharge Power-Down and Self-Refresh  
operation (all banks idle), or Active Power-Down  
(row Active in any bank). CKE is synchronous for  
power down entry and exit and for self-refresh  
entry. Input buffers excluding CKE are disabled  
during self-refresh. CKE is used asynchronously  
to detect self-refresh exit condition. Self-refresh  
termination itself is synchronous. After VREF has  
become stable during power-on and initialisation  
sequence, it must be maintained for proper  
operation of the CKE receiver. For proper self-  
refresh entry and exit, VREF must be maintained to  
this input. CKE must be maintained HIGH  
throughout read and write accesses. Input  
buffers, excluding CK, CK, ODT and CKE are  
disabled during power-down  
Control Signals  
K7  
L7  
K3  
L8  
RAS  
CAS  
WE  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe  
(CAS), Write Enable (WE)  
CS  
Chip Select  
Rev. 1.20, 2007-06  
5
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
Ball#  
Name  
Ball Type Buffer Type Function  
Address Signals  
L2  
BA0  
BA1  
NC  
A0  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Bank Address Bus 1:0  
L3  
L1  
M8  
M3  
M7  
N2  
N8  
N3  
N7  
P2  
P8  
P3  
M2  
Address Signal 12:0, Address Signal  
10/Autoprecharge  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
AP  
A11  
A12  
P7  
R2  
Data Signals  
G8  
DQ0  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Signal 15:0  
Note: Bi-directional data bus. DQ[15:0]  
G2  
DQ1  
H7  
DQ2  
H3  
DQ3  
H1  
DQ4  
H9  
DQ5  
F1  
DQ6  
F9  
DQ7  
C8  
DQ8  
C2  
DQ9  
D7  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
D3  
D1  
D9  
B1  
B9  
Data Strobe  
B7  
UDQS  
UDQS  
LDQS  
LDQS  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
Data Strobe Upper Byte  
Note: UDQS corresponds to the data on DQ[15:8]  
A8  
F7  
Data Strobe Lower Byte  
Note: LDQS corresponds to the data on DQ[7:0]  
E8  
Data Mask  
Rev. 1.20, 2007-06  
6
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
Ball#  
Name  
Ball Type Buffer Type Function  
B3  
F3  
UDM  
LDM  
I
I
SSTL  
SSTL  
Data Mask Upper/Lower Byte  
Note: LDM and UDM are the input mask signals and  
control the lower or upper bytes.  
Power Supplies  
A9,C1,C3,C7,C9  
A1  
VDDQ  
VDD  
PWR  
PWR  
PWR  
PWR  
–
–
–
–
I/O Driver Power Supply  
Power Supply  
A7,B2,B8,D2,D8  
A3,E3  
VSSQ  
VSS  
I/O Driver Power Supply  
Power Supply  
Power Supplies  
J2  
VREF  
VDDQ  
VDDL  
VDD  
AI  
–
–
–
–
–
–
–
I/O Reference Voltage  
I/O Driver Power Supply  
Power Supply  
E9, G1, G3, G7, G9  
J1  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
E1, J9, M9, R1  
E7, F2, F8, H2, H8  
J7  
Power Supply  
VSSQ  
VSSDL  
VSS  
I/O Driver Power Supply  
Power Supply  
A3, E3,J3,N1,P9  
Not Connected  
Power Supply  
A2, E2, R3, R7, R8, L1 NC  
NC  
I
–
Not Connected  
Other Balls  
K9  
ODT  
SSTL  
On-Die Termination Control  
Note: ODT is applied to each DQ, UDQS, UDQS,  
LDQS, LDQS, UDM and LDM signal. An EMRS(1)  
control bit enables or disables the ODT  
functionality.  
TABLE 3  
Abbreviations for Ball Type  
Abbreviation  
Description  
I
Standard input-only ball. Digital levels.  
Output. Digital levels.  
O
I/O  
AI  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
Power  
PWR  
GND  
NC  
Ground  
Not Connected  
Rev. 1.20, 2007-06  
7
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
TABLE 4  
Abbreviations for Buffer Type  
Abbreviation  
Description  
SSTL  
Serial Stub Terminated Logic (SSTL_18)  
Low Voltage CMOS  
LV-CMOS  
CMOS  
OD  
CMOS Levels  
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and  
allows multiple devices to share as a wire-OR.  
FIGURE 1  
Chip Configuration, PG-TFBGA-84 (top view)  
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Notes  
2. LDM is the data mask signal for DQ[7:0], UDM is the data  
mask signal for DQ[15:8]  
3. VDDL and VSSDL are power and ground for the DLL. VDDL is  
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is  
data strobe for DQ[7:0]  
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS  
and VSSQ are isolated on the device.  
,
Rev. 1.20, 2007-06  
8
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
2.2  
256 Mbit DDR2 Addressing  
TABLE 5  
DDR2 Addressing  
Configuration  
16Mb x 16  
Note  
Bank Address  
BA[1:0]  
4
Number of Banks  
Auto-Precharge  
A10 / AP  
A[12:0]  
A[8:0]  
10  
Row Address  
Column Address  
Number of Column Address Bits  
Number of I/Os  
1)  
2)  
3)  
16  
Page Size [Bytes]  
1024 (1K)  
1) Refered to as ’colbits’  
2) Refered to as ’org’  
3) PageSize = 2colbits × org/8 [Bytes]  
Rev. 1.20, 2007-06  
9
11232006-QP6X-6EM0  
                     
                     
                      
                      
                           
                           
                             
                             
                                   
                                    
                                     
                                     
                                       
                                        
                                        
                                         
                                         
                                          
                                             
                                             
                                              
                                              
                                                  
                                                  
                                                   
                                                   
                                                       
                                                       
                                                       
                                                        
                                                           
                                                            
                                                            
                                                             
                                                                
                                                                 
                                                                 
                                                                  
                                                                     
                                                                      
                                                                      
                                                                       
                                                                          
                                                                          
                                                                           
                                                                           
                                                                               
                                                                               
                                                                                
                                                                                
                                                                                    
                                                                                    
                                                                                     
                                                                                     
                                                                                         
                                                                                         
                                                                                          
                                                                                          
                    
                    
                           
                            
                            
                            
                             
                             
                                             
                                              
                                                        
                                                        
                                                         
                                                         
                                                            
                                                             
                                                             
                                                              
                                                              
                                                                        
                                                                         
                                                                                   
                                                                                   
                                                                                              
                                                                                              
              
              
               
               
                
                 
                 
                  
                  
                   
                   
                                                       
                                                       
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
3
Functional Description  
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TABLE 6  
Mode Register Definition (BA[1:0] = 00B)  
Field  
Bits  
Type1)  
Description  
Bank Address [1]  
0B BA1 Bank Address  
Bank Address [0]  
BA1  
14  
reg. addr.  
BA0  
PD  
13  
12  
0B  
BA0 Bank Address  
w
w
Active Power-Down Mode Select  
0B  
1B  
PD Fast exit  
PD Slow exit  
WR  
[11:9]  
Write Recovery2)  
Note: All other bit combinations are illegal.  
001B WR 2  
010B WR 3  
011B WR 4  
100B WR 5  
101B WR 6  
DLL  
TM  
CL  
8
w
w
w
DLL Reset  
0B  
1B  
DLL No  
DLL Yes  
7
Test Mode  
0B  
1B  
TM Normal Mode  
TM Vendor specific test mode  
[6:4]  
CAS Latency  
Note: All other bit combinations are illegal.  
011B CL 3  
100B CL 4  
101B CL 5  
110B CL 6  
111B CL 7  
Rev. 1.20, 2007-06  
10  
11232006-QP6X-6EM0  
            
             
              
              
                    
                    
                     
                     
                      
                      
                          
                           
                           
                           
                            
                            
                            
                             
                             
                                  
                                  
                                        
                                         
                                         
                                          
                                             
                                             
                                              
                                              
                                                  
                                                  
                                                  
                                                   
                                                      
                                                       
                                                       
                                                        
                                                           
                                                            
                                                            
                                                             
                                                                
                                                                 
                                                                 
                                                                  
                                                                     
                                                                     
                                                                      
                                                                      
                                                                          
                                                                          
                                                                           
                                                                           
                                                                               
                                                                               
                                                                                
                                                                                
                                                                                    
                                                                                    
                                                                                     
                                                                                     
                                                                                         
                                                                                         
                                                                                         
                                                                                          
                                   
                                   
                                    
                                       
                                       
                                        
                                        
                                                    
                                                    
                                                     
                                                     
                                                      
                                                      
                                                       
                                                       
                                                       
                                                       
                                                        
                                                        
                                                         
                                                         
                                                          
                                                          
                                                           
                                                           
                                                            
                                                            
                                                             
                                                                  
                                                                  
                                                                   
                    
                    
                                            
                                             
                                             
                                              
                                              
                                                   
                                                   
                                                                            
                                                                             
                                                                             
                                                                              
                                                                                       
                                                                                        
                                                                                            
                                                                                             
                                                                                             
                                                                                              
                                                                                              
                                                                                                 
                                                                                                  
                                                                                                  
                                                                                                  
                                                                                                   
                                                                                                   
                                                                                                   
                                                                                                    
                                                                                                    
                                           
                                           
                                                                                                     
                                                                                                                                     
              
              
              
               
                
                 
                 
                  
                  
                   
                   
                                                  
                                                  
                                                            
                                                            
                                                                     
                                                                      
                                                                               
                                                                                
                                                                                    
                                                                                    
                                                                                    
                                                                                     
                                                                                     
                                                                                         
                                                                                          
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
Field  
Bits  
Type1)  
Description  
Burst Type  
BT  
3
w
0B  
1B  
BT Sequential  
BT Interleaved  
BL  
[2:0]  
w
Burst Length  
Note: All other bit combinations are illegal.  
010B BL 4  
011B BL 8  
1) w = write only register bits  
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and  
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement  
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN  
.
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TABLE 7  
Extended Mode Register Definition (BA[1:0] = 01B)  
Field  
Bits  
Type1)  
Description  
Bank Address [1]  
0B BA1 Bank Address  
Bank Address [0]  
BA1  
14  
reg. addr.  
BA0  
Qoff  
13  
12  
1B  
BA0 Bank Address  
w
Output Disable  
0B  
1B  
QOff Output buffers enabled  
QOff Output buffers disabled  
A11  
11  
10  
w
w
Address Bus [11]  
0B A11 Address bit 11  
Complement Data Strobe (DQS Output)  
DQS  
0B  
1B  
DQS Enable  
DQS Disable  
Rev. 1.20, 2007-06  
11  
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
Field  
Bits  
Type1)  
Description  
OCD  
[9:7]  
w
Off-Chip Driver Calibration Program  
Program  
000B OCD OCD calibration mode exit, maintain setting  
001B OCD Drive (1)  
010B OCD Drive (0)  
100B OCD Adjust mode  
111B OCD OCD calibration default  
AL  
[5:3]  
w
Additive Latency  
Note: All other bit combinations are illegal.  
000B AL 0  
001B AL 1  
010B AL 2  
011B AL 3  
100B AL 4  
101B AL 5  
110B AL 6  
RTT  
6,2  
w
Nominal Termination Resistance of ODT  
Note: See Table 18 “ODT DC Electrical Characteristics” on Page 20  
00B RTT ∞ (ODT disabled)  
01B RTT 75 Ohm  
10B RTT 150 Ohm  
11B RTT 50 Ohm  
DIC  
DLL  
1
0
w
w
Off-chip Driver Impedance Control  
0B  
1B  
DIC Full (Driver Size = 100%)  
DIC Reduced  
DLL Enable  
0B  
1B  
DLL Enable  
DLL Disable  
1) w = write only register bits  
Rev. 1.20, 2007-06  
12  
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
Rev. 1.20, 2007-06  
13  
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
$ꢁꢁ  
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TABLE 8  
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B)  
Description  
reg. addr., Bank Address [1]  
Field Bits  
Type1)  
BA1  
BA0  
A
14  
1B  
BA1 Bank Address  
13  
Bank Address [0]  
0B  
BA0 Bank Address  
[12:8]  
7
w
w
Address Bus  
00000B  
A Address bits  
SRF  
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C  
0B  
1B  
A7 disable  
A7 enable 2)  
A
[6:3]  
w
Address Bus  
0000B A Address bits  
Partial Self Refresh for 4 banks  
PASR [2:0]  
w
Address Bus, Partial Array Self Refresh for 4 Banks3)  
000B PASR0 Full Array  
001B PASR1 Half Array (BA[1:0]=00, 01)  
010B PASR2 Quarter Array (BA[1:0]=00)  
011B PASR3 Not defined  
100B PASR4 3/4 array (BA[1:0]=01, 10, 11)  
101B PASR5 Half array (BA[1:0]=10, 11)  
110B PASR6 Quarter array (BA[1:0]=11)  
111B PASR7 Not defined  
1) w = write only  
2) When DRAM is operated at 85°C ≤ TCase £ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self  
refresh mode can be entered.  
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh  
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued  
Rev. 1.20, 2007-06  
14  
11232006-QP6X-6EM0  
                                                
                                                
                                                 
                                                 
                                                   
                                                   
                                                   
                                                    
                                                    
                                                     
                                                     
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
%
             
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TABLE 9  
EMR(3) Programming Extended Mode Register Definition( BA[1:0]=11B)  
Field  
Bits  
Type1)  
reg.addr  
Description  
BA1  
14  
Bank Adress  
1B  
BA1 Bank Address  
BA0  
A
13  
Bank Adress  
1B  
BA0 Bank Address  
[12:0]  
w
Address Bus  
0000000000000B Address bits  
1) w = write only  
TABLE 10  
ODT Truth Table  
Input Pin  
EMRS(1) Address Bit A10  
EMRS(1) Address Bit A11  
DQ[7:0]  
DQ[15:8]  
LDQS  
LDQS  
UDQS  
UDQS  
LDM  
X
X
X
0
X
X
X
0
X
X
UDM  
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high  
Rev. 1.20, 2007-06  
15  
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
TABLE 11  
Burst Length and Sequence  
Burst Length  
Starting Address  
(A2 A1 A0)  
Sequential Addressing  
(decimal)  
Interleave Addressing  
(decimal)  
4
× 0 0  
× 0 1  
×1 0  
0, 1, 2, 3  
0, 1, 2, 3  
1, 2, 3, 0  
1, 0, 3, 2  
2, 3, 0, 1  
2, 3, 0, 1  
×1 1  
3, 0, 1, 2  
3, 2, 1, 0  
8
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
0, 1, 2, 3, 4, 5, 6, 7  
1, 2, 3, 0, 5, 6, 7, 4  
2, 3, 0, 1, 6, 7, 4, 5  
3, 0, 1, 2, 7, 4, 5, 6  
4, 5, 6, 7, 0, 1, 2, 3  
5, 6, 7, 4, 1, 2, 3, 0  
6, 7, 4, 5, 2, 3, 0, 1  
7, 4, 5, 6, 3, 0, 1, 2  
0, 1, 2, 3, 4, 5, 6, 7  
1, 0, 3, 2, 5, 4, 7, 6  
2, 3, 0, 1, 6, 7, 4, 5  
3, 2, 1, 0, 7, 6, 5, 4  
4, 5, 6, 7, 0, 1, 2, 3  
5, 4, 7, 6, 1, 0, 3, 2  
6, 7, 4, 5, 2, 3, 0, 1  
7, 6, 5, 4, 3, 2, 1, 0  
Notes  
2. Order of burst access for sequential addressing is “nibble-  
based” and therefore different from SDR or DDR  
components  
1. Page Size and Length is a function of I/O  
organization:Page size for all 256 Mbit components is 1  
KByte  
Rev. 1.20, 2007-06  
16  
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
4
Truth Tables  
TABLE 12  
Command Truth Table  
Function  
CKE  
CS RAS CAS WE BA0 A[12:11] A10 A[9:0]  
Note1)2)3)  
BA1  
Previous Current  
Cycle  
Cycle  
4)5)  
4)  
(Extended) Mode Register Set H  
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
BA  
X
OP Code  
Auto-Refresh  
H
H
L
L
L
H
H
X
H
L
X
X
X
X
X
X
X
X
X
4)6)  
4)6)7)  
Self-Refresh Entry  
Self-Refresh Exit  
L
L
X
H
X
H
L
X
H
H
H
H
L
X
4)5)  
4)  
Single Bank Precharge  
Precharge all Banks  
Bank Activate  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
BA  
X
X
X
L
X
X
L
L
H
4)5)  
4)5)8)  
4)5)8)  
4)5)8)  
4)5)8)  
4)  
L
H
L
BA  
BA  
BA  
BA  
BA  
X
Row Address  
Write  
H
H
H
H
H
X
X
H
X
H
Column  
Column  
Column  
Column  
X
L
Column  
Column  
Column  
Column  
X
Write with Auto-Precharge  
Read  
L
L
H
L
L
H
H
H
X
X
H
X
H
Read with Auto-Precharge  
No Operation  
L
H
X
X
X
H
X
X
H
X
H
4)  
Device Deselect  
Power Down Entry  
X
X
X
4)9)  
X
X
X
4)9)  
Power Down Exit  
L
H
X
X
X
X
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.  
2) “X” means “H or L (but a defined logic level)”.  
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down  
and then restarted through the specified initialization sequence before normal operation can continue.  
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.  
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.  
6)  
VREF must be maintained during Self Refresh operation.  
7) Self Refresh Exit is asynchronous.  
8) Burst reads or writes at BL = 4 cannot be terminated.  
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh  
requirements.  
Rev. 1.20, 2007-06  
17  
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
TABLE 13  
Clock Enable (CKE) Truth Table for Synchronous Transitions  
Current State1) CKE  
Command (N)2)3)RAS, Action (N)2)  
CAS, WE, CS  
Note4)5)  
Previous Cycle6) Current Cycle6)  
(N-1)  
(N)  
7)8)11)  
Power-Down  
Self Refresh  
L
L
X
Maintain Power-Down  
7)9)10)11)  
8)11)12)  
L
H
L
DESELECT or NOP  
X
Power-Down Exit  
L
Maintain Self Refresh  
Self Refresh Exit  
9)12)13)14)  
7)9)10)11)15)  
9)10)11)15)  
7)11)14)16)  
17)  
L
H
L
DESELECT or NOP  
DESELECT or NOP  
DESELECT or NOP  
AUTOREFRESH  
Bank(s)Active  
All Banks Idle  
H
H
H
H
Active Power-Down Entry  
Precharge Power-Down Entry  
Self Refresh Entry  
L
L
Any State other  
than listed above  
H
Refer to the Command Truth Table  
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.  
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)  
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.  
4) CKE must be maintained HIGH while the device is in OCD calibration mode.  
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down  
and then restarted through the specified initialization sequence before normal operation can continue.  
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.  
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh  
requirements  
8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in  
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).  
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.  
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.  
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the  
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during  
the time period of tIS + 2×tCKE + tIH.  
12) VREF must be maintained during Self Refresh operation.  
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read  
commands may be issued only after tXSRD (200 clocks) is satisfied.  
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.  
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or  
Refresh operations are in progress.  
16) Self Refresh mode can only be entered from the All Banks Idle state.  
17) Must be a legal command as defined in the Command Truth Table.  
TABLE 14  
Data Mask (DM) Truth Table  
Name (Function)  
DM  
DQs  
Note  
1)  
Write Enable  
L
Valid  
X
1)  
Write Inhibit  
H
1) Used to mask write data; provided coincident with the corresponding data.  
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5
Electrical Characteristics  
5.1  
Absolute Maximum Ratings  
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 18 at any time.  
TABLE 15  
Absolute Maximum Ratings  
Symbol  
Parameter  
Rating  
Min.  
Unit  
Note  
Max.  
1)  
VDD  
Voltage on VDD pin relative to VSS  
Voltage on VDDQ pin relative to VSS  
Voltage on VDDL pin relative to VSS  
Voltage on any pin relative to VSS  
Junction Temperature  
–1.0  
–0.5  
–0.5  
–0.5  
–
+2.3  
+2.3  
+2.3  
+2.3  
+125  
+150  
V
1)2)  
1)2)  
1)  
VDDQ  
VDDL  
VIN, VOUT  
TJ  
V
V
V
1)  
°C  
°C  
1)2)  
TSTG  
Storage Temperature  
–55  
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.  
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.  
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only and functional operation of the device at these or any other  
conditions above those indicated in the operational sections of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended periods may affect reliability.  
TABLE 16  
DRAM Component Operating Temperature Range  
Symbol  
Parameter  
Rating  
Unit  
Note  
Min.  
Max.  
1)2)3)4)  
TCASE  
Operating Temperature  
0
95  
°C  
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.  
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case  
temperature must be maintained between 0 - 95 °C under all other specification parameters.  
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 μs  
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%  
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5.2  
DC Characteristics  
TABLE 17  
Recommended DC Operating Conditions (SSTL_18)  
Symbol  
Parameter  
Rating  
Min.  
Unit  
Notes  
Typ.  
Max.  
1)2)  
1)2)  
1)2)  
3)4)  
5)  
VDD  
Supply Voltage  
1.7  
1.8  
1.9  
V
V
V
V
V
VDDDL  
VDDQ  
VREF  
VTT  
Supply Voltage for DLL  
Supply Voltage for Output  
Input Reference Voltage  
Termination Voltage  
1.7  
1.8  
1.9  
1.7  
1.8  
1.9  
0.49 × VDDQ  
0.5 × VDDQ  
VREF  
0.51 × VDDQ  
V
REF – 0.04  
VREF + 0.04  
1) HYB18T256161BF–20/25/28  
2) DDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.  
3) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to  
V
be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ  
.
4) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)  
5)  
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and  
must track variations in die dc level of VREF  
.
TABLE 18  
ODT DC Electrical Characteristics  
Parameter / Condition  
Symbol  
Min.  
Nom.  
Max.  
Unit  
Note  
1)  
Termination resistor impedance value for  
EMRS(1)[A6,A2] = [0,1]; 75 Ohm  
Rtt1(eff)  
60  
75  
90  
Ω
1)  
Termination resistor impedance value for  
EMRS(1)[A6,A2] =[1,0]; 150 Ohm  
Rtt2(eff)  
120  
150  
180  
Ω
2)  
Deviation of VM with respect to VDDQ / 2  
delta VM  
–6.00  
—
+ 6.00  
%
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively.  
Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).  
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) –  
1) x 100%  
TABLE 19  
Input and Output Leakage Currents  
Symbol  
Parameter / Condition  
Min.  
Max.  
Unit  
Notes  
1)  
IIL  
Input Leakage Current; any input 0 V < VIN < VDD  
Output Leakage Current; 0 V < VOUT < VDDQ  
–2  
–5  
+2  
+5  
μA  
μA  
2)  
IOL  
1) all other pins not under test = 0 V  
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS are disabled and ODT is turned off  
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5.3  
DC & AC Characteristics  
DDR2 SDRAM pin timing are specified for either single ended  
or differential mode depending on the setting of the EMRS(1)  
“Enable DQS” mode bit; timing advantages of differential  
mode are realized in system design. The method by which the  
DDR2 SDRAM pin timing are measured is mode dependent.  
In single ended mode, timing relationships are measured  
In differential mode, these timing relationships are measured  
relative to the crosspoint of DQS and its complement, DQS.  
This distinction in timing methods is verified by design and  
characterization but not subject to production test. In single  
ended mode, the DQS signals are internally disabled and  
don’t care.  
relative to the rising or falling edges of DQS crossing at VREF  
.
TABLE 20  
DC & AC Logic Input Levels  
Symbol  
Parameter  
Min.  
Max.  
Units  
VIH(dc)  
VIL(dc)  
VIH(ac)  
VIL(ac)  
DC input logic high  
DC input low  
V
REF + 0.125  
V
DDQ + 0.3  
REF – 0.125  
V
V
V
V
–0.3  
V
AC input logic high  
AC input low  
V
REF + 0.250  
—
—
VREF – 0.250  
TABLE 21  
Single-ended AC Input Test Conditions  
Symbol  
Condition  
Value  
Unit  
Notes  
1)  
VREF  
Input reference voltage  
0.5 x VDDQ  
1.0  
V
1)  
VSWING.MAX  
SLEW  
Input signal maximum peak to peak swing  
Input signal minimum Slew Rate  
V
2)3)  
1.0  
V / ns  
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.  
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to  
IL(ac).MAX for falling edges as shown in Figure 2  
V
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative  
transitions.  
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FIGURE 2  
Single-ended AC Input Test Conditions Diagram  
6
$$1  
6
MIN  
)(ꢋACꢌ  
6
MIN  
)(ꢋDCꢌ  
6
37).'ꢋ-!8ꢌ  
6
6
6
6
2%&  
),ꢋDCꢌ  
),ꢋACꢌ  
33  
MAX  
MAX  
DELTA 4&  
DELTA 42  
2ISING 3LEW ꢍ  
6),ꢋACꢌ MAX  
6)(ꢋACꢌ MIN ꢎ  
62%&  
62%& ꢎ  
&ALLING 3LEW ꢍ  
DELTA 42  
DELTA 4&  
TABLE 22  
Differential DC and AC Input and Output Logic Levels  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Notes  
1)  
2)  
3)  
4)  
5)  
VIN(dc)  
VID(dc)  
VID(ac)  
VIX(ac)  
VOX(ac)  
DC input signal voltage  
–0.3  
V
V
V
DDQ + 0.3  
—
—
V
DC differential input voltage  
AC differential input voltage  
0.25  
DDQ + 0.6  
DDQ + 0.6  
0.5  
AC differential cross point input voltage  
0.5 × VDDQ – 0.175  
0.5 × VDDQ + 0.175  
0.5 × VDDQ + 0.125  
V
AC differential cross point output voltage 0.5 × VDDQ – 0.125  
V
1)  
2)  
3)  
V
V
V
IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.  
ID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc)  
ID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac)  
.
.
4) The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)  
indicates the voltage at which differential input signals must cross.  
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)  
indicates the voltage at which differential input signals must cross.  
FIGURE 3  
Differential DC and AC Input and Output Logic Levels Diagram  
6$$1  
642  
#ROSSING 0OINT  
6)$  
6)8 OR 6/8  
6#0  
6331  
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5.4  
Output Buffer Characteristics  
TABLE 23  
Full Strength Calibrated Pull-up Driver Characteristics  
Voltage (V)  
Calibrated Pull-up Driver Current [mA]  
Nominal Minimum1) Nominal  
Nominal(18  
Nominal  
High2)(17.25  
Ohms)  
Nominal  
(21 Ohms)  
Low2)(18.75 Ohms) ohms)3)  
Maximum4) (15  
Ohms)  
0.2  
0.3  
0.4  
–9.5  
–10.7  
–16.0  
–21.0  
–11.4  
–16.5  
–21.2  
–11.8  
–17.4  
–23.0  
–13.3  
–20.0  
–27.0  
–14.3  
–18.3  
1) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process  
2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8 V, any process  
3) The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process  
4) The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process  
TABLE 24  
Full Strength Calibrated Pull-down Driver Characteristics  
Calibrated Pull-down Driver Current [mA]  
Voltage (V)  
Nominal Minimum1)  
(21 Ohms)  
Nominal  
Low2)(18.75  
Ohms)  
Nominal3)(18  
ohms)  
Nominal  
High2)(17.25  
Ohms)  
Nominal  
Maximum4) (15  
Ohms)  
0.2  
0.3  
0.4  
9.5  
10.7  
16.0  
21.0  
11.5  
16.6  
21.6  
11.8  
17.4  
23.0  
13.3  
20.0  
27.0  
14.3  
18.7  
1) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process  
2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8V, any process  
3) The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process  
4) The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process  
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5.5  
Input / Output Capacitance  
TABLE 25  
Input / Output Capacitance  
Symbol  
Parameter  
Min.  
Max.  
Unit  
CCK  
CDCK  
CI  
Input capacitance, CK and CK  
1.0  
—
2.0  
pF  
pF  
pF  
pF  
pF  
Input capacitance delta, CK and CK  
Input capacitance, all other input-only pins  
Input capacitance delta, all other input-only pins  
0.25  
1.75  
0.25  
3.5  
1.0  
—
CDI  
CIO  
Input/output capacitance,  
DQ, DM, DQS, DQS  
2.5  
CDIO  
Input/output capacitance delta,  
DQ, DM, DQS, DQS  
—
0.5  
pF  
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5.6  
Overshoot and Undershoot Specification  
TABLE 26  
AC Overshoot / Undershoot Specification for Address and Control Pins  
Parameter  
–20  
–25  
–28  
Unit  
Maximum peak amplitude allowed for overshoot area  
Maximum peak amplitude allowed for undershoot area  
Maximum overshoot area above VDD  
0.5  
0.5  
0.5  
V
0.5  
0.5  
0.5  
V
0.80  
0.80  
0.80  
0.80  
0.80  
0.80  
V.ns  
V.ns  
Maximum undershoot area below VSS  
FIGURE 4  
AC Overshoot / Undershoot Diagram for Address and Control Pins  
-AXIMUM !MPLITUDE  
/VERSHOOT !REA  
6$$  
633  
5NDERSHOOT !REA  
-AXIMUM !MPLITUDE  
4IME ꢋNSꢌ  
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TABLE 27  
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins  
Parameter  
–20  
–25  
–28  
Unit  
Maximum peak amplitude allowed for overshoot area  
Maximum peak amplitude allowed for undershoot area  
Maximum overshoot area above VDDQ  
0.9  
0.9  
0.9  
V
0.9  
0.9  
0.9  
V
0.23  
0.23  
0.23  
0.23  
0.23  
0.23  
V.ns  
V.ns  
Maximum undershoot area below VSSQ  
FIGURE 5  
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins  
-AXIMUM !MPLITUDE  
/VERSHOOT !REA  
6$$1  
6331  
5NDERSHOOT !REA  
-AXIMUM !MPLITUDE  
4IME ꢋNSꢌ  
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5.7  
AC Characteristics  
5.7.1  
Speed Grade Definitions  
TABLE 28  
Speed Grade Definition  
Speed Grade  
Parameter  
Symbol  
–20  
–25  
–28  
Unit  
Note  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock  
Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
@ CL = 6  
@ CL = 7  
tCK  
tCK  
tCK  
tCK  
tCK  
tRAS  
tRC  
tRCD  
tRP  
5
8
5
8
5
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3.75  
3
8
3.75  
3
8
3.75  
3
8
8
8
8
2.5  
2.0  
45  
60  
15  
15  
8
2.5  
—
45  
60  
15  
15  
8
2.8  
—
45  
60  
15  
15  
8
8
—
70k  
—
—
—
—
70k  
—
—
—
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
70k  
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8Timings  
are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements” according  
to Chapter 7.1 only.  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference  
level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS is defined in  
Chapter 7.3.  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
4) The output timing reference voltage level is VTT. See Chapter 7.1 for the reference load for timing measurements.  
5)  
tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.  
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5.7.2  
AC Timing Parameters  
List of Timing Parameters  
TABLE 29  
Timing Parameter by Speed Grade  
Parameter  
–20  
–25  
–28  
Notes1)  
2)3)4)5)6)  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
DQ output access time from CK tAC  
–450  
+450  
–500  
+500  
–550  
+550  
ps  
/ CK  
CAS A to CAS B command  
period  
tCCD  
2
—
2
—
2
—
tCK  
CK, CK high-level width  
tCH  
0.45  
3
0.55  
—
0.45  
3
0.55  
—
0.45  
3
0.55  
—
tCK  
tCK  
CKE minimum high and low  
pulse width  
tCKE  
CK, CK low-level width  
tCL  
0.45  
0.55  
—
0.45  
0.55  
—
0.45  
0.55  
—
tCK  
tCK  
7)18)  
8)  
Auto-Precharge write recovery tDAL  
WR + tRP  
WR + tRP  
WR + tRP  
+ precharge time  
Minimum time clocks remain  
ON after CKE asynchronously  
drops LOW  
tDELAY tIS + tCK  
+
––  
tIS + tCK  
tIH  
+
––  
tIS + tCK  
tIH  
+
––  
ns  
tIH  
9)  
9)  
DQ and DM input hold time  
(differential data strobe)  
tDH  
145  
-105  
0.35  
––  
250  
0
––  
275  
25  
––  
ps  
ps  
tCK  
ps  
tCK  
ps  
tCK  
ps  
ps  
tCK  
tCK  
DQ and DM input hold time  
(single ended data strobe)  
tDH1  
––  
––  
––  
DQ and DM input pulse width tDIPW  
(each input)  
—
0.35  
–500  
0.35  
—
—
0.35  
–550  
0.35  
—
—
9)  
DQS output access time from tDQSCK –450  
CK / CK  
+450  
—
+500  
—
+550  
—
DQS input low (high) pulse  
width (write cycle)  
tDQSL,H 0.35  
tDQSQ  
10)  
DQS-DQ skew (for DQS &  
associated DQ signals)  
—
450  
450  
450  
Write command to 1st DQS  
latching transition  
tDQSS WL –  
WL +  
0.25  
WL –  
0.25  
WL +  
0.25  
WL –  
0.25  
WL +  
0.25  
0.25  
9)  
9)  
DQ and DM input setup time  
(differential data strobe)  
tDS  
20  
125  
––  
––  
—
—
150  
––  
––  
—
—
DQ and DM input setup time  
(single ended data strobe)  
tDS1  
tDSH  
-105  
0.2  
0.2  
0
25  
DQS falling edge hold time  
from CK (write cycle)  
—
—
0.2  
0.2  
0.2  
0.2  
DQS falling edge to CK setup tDSS  
time (write cycle)  
11)  
Clock half period  
tHP  
MIN. (tCL,  
tCH  
MIN. (tCL,  
tCH  
MIN. (tCL,  
tCH  
)
)
)
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Parameter  
–20  
–25  
–28  
Notes1)  
2)3)4)5)6)  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
12)  
Data-out high-impedance time tHZ  
from CK / CK  
—
tAC.MAX  
—
tAC.MAX  
—
tAC.MAX  
ps  
ps  
tCK  
Address and control input hold tIH  
time  
525  
0.6  
575  
0.6  
—
—
625  
0.6  
—
—
Address and control input pulse tIPW  
—
width  
(each input)  
Address and control input setup tIS  
time  
400  
450  
—
500  
—
ps  
ps  
ps  
tCK  
ns  
12)  
12)  
DQ low-impedance time from tLZ(DQ) 2 × tAC.MIN tAC.MAX  
CK / CK  
2 × tAC.MIN tAC.MAX  
2 × tAC.MIN tAC.MAX  
DQS low-impedance from CK / tLZ(DQS) tAC.MIN  
CK  
tAC.MAX  
tAC.MIN  
tAC.MAX  
tAC.MIN  
tAC.MAX  
Mode register set command  
cycle time  
tMRD  
2
—
2
—
2
—
OCD drive mode output delay tOIT  
0
12  
—
0
12  
—
0
12  
—
Data output hold time from  
DQS  
tQH  
tHP–tQHS  
t
HP–tQHS  
tHP–tQHS  
Data hold skew factor  
tQHS  
tREFI  
—
—
—
75  
600  
7.8  
3.9  
—
—
—
—
75  
600  
7.8  
3.9  
—
—
—
—
75  
600  
7.8  
3.9  
—
ps  
μs  
μs  
ns  
13)14)  
13)15)  
16)  
Average periodic refresh  
Interval  
Auto-Refresh to Active/Auto-  
Refresh command period  
tRFC  
12)  
Read preamble  
Read postamble  
tRPRE  
tRPST  
0.9  
1.1  
0.60  
—
0.9  
1.1  
0.60  
—
0.9  
1.1  
0.60  
—
tCK  
tCK  
ns  
12)  
0.40  
7.5  
0.40  
7.5  
0.40  
7.5  
14)17)  
Active bank A to Active bank B tRRD  
command period  
Internal Read to Precharge  
command delay  
tRTP  
7.5  
—
7.5  
—
7.5  
—
ns  
Write preamble  
Write postamble  
tWPRE 0.35 x tCK  
tWPST 0.40  
—
0.35 x tCK  
0.40  
—
0.35 x tCK  
0.40  
—
tCK  
tCK  
ns  
17)  
0.60  
—
0.60  
—
0.60  
—
Write recovery time for write  
without Auto-Precharge  
tWR  
13  
15  
15  
18)  
19)  
20)  
Write recovery time for write  
with Auto-Precharge  
WR  
tWTR  
tXARD  
t
WR/tCK  
t
WR/tCK  
t
WR/tCK  
tCK  
ns  
Internal Write to Read  
command delay  
7.5  
2
—
—
7.5  
2
—
—
7.5  
2
—
—
Exit power down to any valid  
command  
tCK  
(other than NOP or Deselect)  
20)  
Exit active power-down mode tXARDS 10 – AL  
to Read command (slow exit,  
lower power)  
—
8 – AL  
—
7 – AL  
—
tCK  
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Parameter  
–20  
–25  
–28  
Notes1)  
2)3)4)5)6)  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Exit precharge power-down to tXP  
any valid command (other than  
NOP or Deselect)  
2
—
2
—
2
—
tCK  
Exit Self-Refresh to non-Read tXSNR  
command  
t
RFC +10  
—
—
t
RFC +10  
—
—
t
RFC +10  
—
—
ns  
Exit Self-Refresh to Read  
command  
tXSRD  
200  
200  
200  
tCK  
1) VDDQ, VDD refer to Chapter 1.  
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down  
and then restarted through the specified initialization sequence before normal operation can continue.  
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this  
data sheet.  
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS, input reference  
level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in  
Chapter 5.3 of this data sheet.  
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
6) The output timing reference voltage level is VTT. See Chapter 5 for the reference load for timing measurements.  
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to  
the WR parameter stored in the MR.  
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change  
during power-down, a specific procedure is required.  
9) Timing is referenced to Industrial standard definition  
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate  
mis-match between DQS / DQS and associated DQ in any given cycle.  
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can  
be greater than the minimum specification limits for tCL and tCH).  
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving  
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These  
parameters are verified by design and characterization, but not subject to production test.  
13) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85 °C  
and 95 °C.  
14) 0 °C ≤ TCASE ≤ 85 °C  
15) 85 °C < TCASE ≤ 95 °C  
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.  
17) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system  
performance (bus turnaround) degrades accordingly.  
18) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded  
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK  
refers to the application clock period. WR refers to the WR parameter stored in the MRS.  
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.  
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-  
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow  
power-down exit timing tXARDS has to be satisfied.  
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5.7.3  
ODT AC Electrical Characteristics  
TABLE 30  
ODT AC Characteristics and Operating Conditions for all bins  
Symbol  
Parameter / Condition  
Values  
Unit  
Note  
Min.  
Max.  
1)  
tAOND  
tAON  
ODT turn-on delay  
2
2
nCK  
ns  
1)2)  
1)  
ODT turn-on  
tAC.MIN  
tAC.MAX + 0.7 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns  
2 tCK +  
t
AC.MAX + 1 ns  
ns  
1)  
2.5  
2.5  
nCK  
ns  
1)3)  
1)  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
ODT to Power Down Mode Entry Latency  
ODT Power Down Exit Latency  
t
AC.MIN + 2 ns  
2.5 tCK +  
t
AC.MAX + 1 ns  
ns  
1)  
3
8
—
—
nCK  
nCK  
1)  
1) Unit “tCK.AVG” represents the actual tCK.AVG of the input clock under operation. Unit “nCK” represents one clock cycle of the input clock,  
counting the actual clock edges. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be  
registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)  
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the  
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. tAOND is 2 clock cycles after the  
clock edge that registered a first ODT HIGH counting the actual input clock edges.  
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.  
Both are measured from tAOFD, which is interpreted differently per speed bin. If tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after  
the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.  
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6
Specifications and Conditions  
TABLE 31  
DD Measurement Conditions  
I
Parameter  
Symbol Note  
1)2)3)4)5)6)  
Operating Current - One bank Active - Precharge  
IDD0  
t
CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands.  
Address and control inputs are switching; Databus inputs are switching.  
1)2)3)4)5)6)  
Operating Current - One bank Active - Read - Precharge  
IDD1  
I
OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL =  
CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are  
switching; Databus inputs are switching.  
1)2)3)4)5)6)  
1)2)3)4)5)6)  
1)2)3)4)5)6)  
1)2)3)4)5)6)  
1)2)3)4)5)6)  
1)2)3)4)5)6)  
1)2)3)4)5)6)  
Precharge Power-Down Current  
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs  
are floating.  
IDD2P  
Precharge Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching,  
Data bus inputs are switching.  
IDD2N  
Precharge Quiet Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable,  
Data bus inputs are floating.  
IDD2Q  
IDD3P(0)  
IDD3P(1)  
IDD3N  
Active Power-Down Current  
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus  
inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).  
Active Power-Down Current  
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus  
inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);  
Active Standby Current  
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid  
commands. Address inputs are switching; Data Bus inputs are switching;  
Operating Current  
IDD4R  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS  
= tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
switching; Data Bus inputs are switching; IOUT = 0 mA.  
1)2)3)4)5)6)  
Operating Current  
IDD4W  
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS  
= tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
switching; Data Bus inputs are switching;  
1)2)3)4)5)6)  
1)2)3)4)5)6)  
Burst Refresh Current  
IDD5B  
t
CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid  
commands, Other control and address inputs are switching, Data bus inputs are switching.  
Distributed Refresh Current  
IDD5D  
t
CK = tCK(IDD), Refresh command every tREFI = 7.8 μs interval, CKE is LOW and CS is HIGH between  
valid commands, Other control and address inputs are switching, Data bus inputs are switching.  
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Parameter  
Symbol Note  
1)2)3)4)5)6)  
Self-Refresh Current  
IDD6  
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data  
bus inputs are floating.  
1)2)3)4)5)6)7)  
Operating Bank Interleave Read Current  
IDD7  
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK  
CK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address  
bus inputs are stable during deselects; Data bus is switching.  
=
t
1)  
2)  
3)  
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
I
I
DD specifications are tested after the device is properly initialized.  
DD parameter are specified with ODT disabled.  
4) Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS.  
5) Definitions for IDD: see Table 32  
6) Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7..  
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT  
TABLE 32  
Definition for IDD  
Parameter  
Description  
LOW  
defined as VIN ≤ VIL(ac).MAX  
HIGH  
defined as VIN ≥ VIH(ac).MIN  
STABLE  
FLOATING  
SWITCHING  
defined as inputs are stable at a HIGH or LOW level  
defined as inputs are VREF = VDDQ / 2  
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address  
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ  
signals not including mask or strobes  
TABLE 33  
DD Specification  
I
Speed Grade  
Symbol  
–20  
typ.  
–25  
typ.  
-28  
Unit  
Note  
typ.  
IDD0  
92  
99  
4
81  
89  
4
77  
85  
4
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD1  
IDD2P  
IDD2N  
IDD2Q  
IDD3P(0)  
IDD3P(1)  
IDD3N  
IDD4R  
IDD4W  
IDD5B  
IDD5D  
46  
40  
30  
5
41  
38  
28  
5
38  
35  
27  
5
1)  
2)  
52  
166  
189  
127  
5
47  
153  
163  
119  
5
43  
145  
149  
115  
5
3)  
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256-Mbit Double-Data-Rate-Two SDRAM  
Speed Grade  
Symbol  
–20  
typ.  
–25  
typ.  
-28  
Unit  
Note  
typ.  
3)  
IDD6  
IDD7  
4
4
4
mA  
mA  
204  
193  
193  
1) MRS(12)=0  
2) MRS(12)=1  
3) 0 ≤ TCASE ≤ 85°C  
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7
Package  
7.1  
Package Dimension  
FIGURE 6  
Package Outline P-TFBGA-84  
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Notes  
1. Drawing according to ISO 8015  
2. Dimensions in mm  
3. General tolerances +/- 0.15  
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7.2  
Package Thermal Characteristics  
TABLE 34  
Package thermal characteristics  
JESD51  
Theta_jA1)  
Theta_jC2)  
JEDEC Board  
Air Flow  
1s0p  
0 m/s  
69  
2s0p  
0 m/s  
41  
1 m/s  
53  
3 m/s  
47  
1 m/s  
35  
3 m/s  
33  
Rth[K/W]  
5
1) Junction to Ambient thermal resistance. The value has been obtained by simulation using the conditions stated in the Industrial standard.  
2) Junction to Case thermal resistance. The value has been obtained by simulation.  
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List of Figures  
Figure 1  
Figure 2  
Figure 3  
Figure 4  
Figure 5  
Figure 6  
Chip Configuration, PG-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Package Outline P-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
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256-Mbit Double-Data-Rate-Two SDRAM  
List of Tables  
Table 1  
Table 2  
Table 3  
Table 4  
Table 5  
Table 6  
Table 7  
Table 8  
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Chip Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Extended Mode Register Definition (BA[1:0] = 01B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B). . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
EMR(3) Programming Extended Mode Register Definition( BA[1:0]=11B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
ODT Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Full Strength Calibrated Pull-up Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Full Strength Calibrated Pull-down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 26  
Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Timing Parameter by Speed Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
ODT AC Characteristics and Operating Conditions for all bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Table 9  
Table 10  
Table 11  
Table 12  
Table 13  
Table 14  
Table 15  
Table 16  
Table 17  
Table 18  
Table 19  
Table 20  
Table 21  
Table 22  
Table 23  
Table 24  
Table 25  
Table 26  
Table 27  
Table 28  
Table 29  
Table 30  
Table 31  
Table 32  
Table 33  
Table 34  
I
DD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
DD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
I
Rev. 1.20, 2007-06  
38  
11232006-QP6X-6EM0  
Internet Data Sheet  
HYB18T256161BF–20/25/28  
256-Mbit Double-Data-Rate-Two SDRAM  
Table of Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
2
2.1  
2.2  
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
256 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3
4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
5
5.1  
5.2  
5.3  
5.4  
5.5  
5.6  
5.7  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
5.7.1  
5.7.2  
5.7.3  
6
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
7
7.1  
7.2  
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Rev. 1.20, 2007-06  
39  
11232006-QP6X-6EM0  
Internet Data Sheet  
Edition 2007-06  
Published by Qimonda AG  
Gustav-Heinemann-Ring 212  
D-81739 München, Germany  
© Qimonda AG 2007.  
All Rights Reserved.  
Legal Disclaimer  
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics  
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any  
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,  
including without limitation warranties of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in question please  
contact your nearest Qimonda Office.  
Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in  
1. Any applications that are intended for military usage (including but not limited to weaponry), or  
2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining  
or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if  
a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly -  
(i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or  
(ii) Cause the failure of such Critical Systems; or  
b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly -  
(i) Endanger the health or the life of the user of such Critical Systems or any other person; or  
(ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to  
property, whether tangible or intangible).  
www.qimonda.com  

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