PT6332 [PTC]
VFD Driver/Controller IC; VFD驱动器/控制器IC
| 型号： | PT6332 |
| 厂家： | 
PRINCETON TECHNOLOGY CORP |
| 描述： | VFD Driver/Controller IC |
| 文件： | 总37页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
DESCRIPTION
PT6332 is a VFD driver IC driven on 1/2 to 1/3 duty factor. It can drive up to 168 segments. 56 segment
output lines, 3 grid output lines, 4 general purpose output lines, control circuit, key scan circuit are all
incorporated into a single chip to build a highly reliable peripheral device for a single chip micro
controller. Pin configuration and application circuit are optimized for easy PCB layout and cost saving
advantages.
FEATURES
• CMOS technology
• Up to 168 segment outputs (3 Grid & 56 Segment drivers) or
Up to 114 segment outputs (2 Grid & 57 Segment drivers)
• Up to 25 key inputs
• Up to 4 general purpose outputs
• Sleep and dimmer mode
• One-Pin oscillation circuit
• Hard ware duty cycle selection 1/2 or 1/3
• Available in 80 pins, LQFP
APPLICATION
• Electronic equipment with VFD display
PT6332 V1.0
- 1 -
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
BLOCK DIAGRAM
Grid
D rive r
Segment Driver
57
/BLK
VFL
MPX
17 1
VDD
La tch
VSS1
VSS2
D im me r
Timin g
Ge nerato r
Con tro l
R egiste r
16
57
Shift Reg ister
Tim in g
Ge nerato r
Key Buffer
Divider
C om ma nd
Inte rfa ce
Key Sca n
Clo ck
OSCI
Ge nerato r
PT6332 V1.0
- 2 -
February, 2006
Tel: 886-2-66296288
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
INPUT/OUTPUT PINS EQUIVALENT CIRCUIT
•
•
•
DI, CE, CL, /BLK, DT
•
•
•
OSCI
KSn
KIn
V
DD
V
DD
VDD
DO
V
DD
VDD
V
DD
GRn, SGn
V
FL
PT6332 V1.0
- 3 -
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
PIN CONFIGURATION
VSS1
KS1
61
62
63
40
39
38
SG21
SG22
SG23
KS2
KS3
KS4
64
65
66
67
37
36
SG24
SG25
KS5
KI1
KI2
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SG26
SG27
68
69
70
71
72
73
74
75
76
77
78
79
80
SG28
SG29
KI3
KI4
SG30
PT6332
KI5
DT
SG31
SG32
/BLK
DO
SG33
SG34
CE
SG35
CL
SG36
SG37
SG38
DI
VDD
OSCI
VSS2
SG39
SG40
PT6332 V1.0
- 4 -
February, 2006
Tel: 886-2-66296288
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
PIN DESCRIPTION
Pin Name
GR1 ~ GR2
GR3/SG57
VFL
I/O
O
O
-
Description
Pin No.
1 ~ 2
Grid driver output pin
Grid/Segment driver output pin
Driver power supply
3
4
SG56/P1 ~ SG53/P4
SG52 ~ SG1
VSS1
O
O
-
Segment driver/General purpose output pin
Segment output pin
Ground pin
5 ~ 8
9~ 60
61
KS1 ~ KS5
KI1 ~ KI5
O
I
Key scan output pin
Key scan input pin
62 ~ 66
67 ~ 71
Duty cycle selection pin
DT
I
(DT=0, 1/3 duty)
72
(DT=1, 1/2 duty)
Blank input pin (Reset pin)
When this pin is set to “Low” level, the display is turned off
and key scan is disabled. All key data are reset to low.
When this pin is set to “High”, the display is turned on and
the key scan is enabled. (see note)
Data output pin (open ~ drain)
Chip enable input pin
Clock input pin
Data input pin
Power supply
Oscillation input pin
/BLK
I
73
DO
CE
CL
O
I
I
I
-
I
74
75
76
77
78
79
80
DI
VDD
OSCI
VSS2
-
Ground pin
PT6332 V1.0
- 5 -
February, 2006
Tel: 886-2-66296288
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
FUNCTION DESCRIPTION
SERIAL DATA INPUT
1/3 DUTY
When stopped with CL at the low level.
CE
CL
0
1
1
1
0
0
0
1
D1
D2
D56
D112
D 168
0
0
0
C0
0
0
0
0
0
0
0
0
0
0
0
0
P1
P2
P3
P4
S0
S1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DM9
0
0
1
0
1
0
DI
B0
B1
B2
B3
A0
A1
A2
A3
Display D at a
Address
Control Data
DD
DD
DD
CE
0
1
1
1
0
0
0
1
D57
D58
0
0
0
0
0
C1
C2
0
0
0
0
0
0
0
0
0
0
B0
B1
B2
B3
A0
A1
A2
A3
Display D at a
Address
0
1
1
1
0
0
0
1
D 11 3 D 11 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0
B1
B2
B3
A0
A1
A2
A3
Display D at a
Address
Figure 1
Note: DD=Direction Data
PT6332 V1.0
- 6 -
February, 2006
Tel: 886-2-66296288
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
When stopped with CL at the high level.
CE
CL
0
1
1
1
0
0
0
1
D1
D2
D56
0
0
0
C0
0
0
0
0
0
0
0
0
0
0
0
0
P1
P2
P3
P4
S0
S1
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DM9
0
0
1
0
1
0
DI
B0
B1
B2
B3
A0
A1
A2
A3
Display Dat a
Address
Control Data
DD
DD
DD
CE
0
1
1
1
0
0
0
1
D57 D58
D112
0
0
0
0
0
C1
C2
0
0
0
0
0
0
0
0
0
0
B0
B1
B2
B3
A0
A1
A2
A3
Display Dat a
Address
0
1
1
1
0
0
0
1
D113 D114
D168
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0
B1
B2
B3
A0
A1
A2
A3
Display Data
Addres s
Figure 2
Notes:
1. DD
2. Address
: Direction Data
: Applications must send the value (8EH) as shown in figure 1 & 2
3. D1 to D56
: Segment display data for the GR1 digit output pin (when P1 ~ P4=0)
Dn (n=1 to 56)=1: Segment on
Dn (n=1 to 56)=0: Segment off
4. D57 to D112
5. D113 to D168
6. D53 to D56
7. C0 to C2
: Segment display data for the GR2 digit output pin
Dn (n=57 to 112)=1: Segment on
Dn (n=57 to 112)=0: Segment off
: Segment display data for the GR3 digit output pin
Dn (n=113 to 168)=1: Segment on
Dn (n=113 to 168)=0: Segment off
: General purpose output pin (when P1~P4=1)
Dn (n=53 to 56)=1: General purpose on (High level)
Dn (n=53 to 56)=0: General purpose off (Low level)
: Sleep Mode Current Setup
Cn (n=0 to 2)=0: IDD1
Cn (n=0 to 2)=1: IDD1
≤
≤
100
µA (Normal mode)
5µ
A (Test mode)
PT6332 V1.0
- 7 -
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
1/2 DUTY
When stopped with CL at the low level.
CE
CL
0
1
1
1
0
0
0
1
D1
D2
D56 D57 C0
0
0
0
0
P1
P2
P3
P4
S0
S1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DM9
0
0
DI
B0
B1
B2
B3
A0
A1
A2
A3
Display D ata
Address
Control Data
DD
CE
0
1
1
1
0
0
0
1
D 58
D 59
D 11 3 D 11 4
0
0
0
0
0
0
0
0
0
C1
C2
0
0
0
0
0
0
0
0
0
0
0
1
B0
B1
B2
B3
A0
A1
A2
A3
Display D ata
Address
DD
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
56 bits
Address
DD
Figure 3
Note: DD=Direction Data
PT6332 V1.0
- 8 -
February, 2006
Tel: 886-2-66296288
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
When stopped with CL at the high level.
CE
CL
0
1
1
1
0
0
0
1
D1
D2
D56 D57 C0
0
0
0
0
P1
P2
P3
P4
S0
S1
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DM9
0
0
DI
B0
B1
B2
B3
A0
A1
A2
A3
Display D ata
Address
Control Data
DD
CE
0
1
1
1
0
0
0
1
D 58 D 59
D 11 3 D 11 4
0
0
0
0
0
0
0
0
0
C1
C2
0
0
0
0
0
0
0
0
0
0
0
1
B0
B1
B2
B3
A0
A1
A2
A3
Display D at a
Address
DD
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
56 bits
Addres s
DD
Figure 4
Notes:
1. DD
2. Address
: Direction Data
: Applications must send the value (8EH) as shown in figure 3 & 4
3. D1 to D57
4. D58 to D114
5. D53 to D56
6. C0 to C2
: Segment display data for the GR1 digit output pin (when P1 ~ P4 = 0)
Dn (n=1 to 57) = 1: Segment on
Dn (n=1 to 57) = 0: Segment off
: Segment display data for the GR2 digit output pin
Dn (n=58 to 114) = 1: Segment on
Dn (n=58 to 114) = 0: Segment off
: General purpose output pin (when P1 ~ P4=1)
Dn (n=53 to 56) = 1: General purpose on (High level)
Dn (n=53 to 56) = 0: General purpose off (Low level)
: Sleep Mode Current Setup
Cn (n=0 to 2)=0: IDD1
Cn (n=0 to 2)=1: IDD1
≤
≤
100
µA (Normal mode)
5µ
A (Test mode)
PT6332 V1.0
- 9 -
February, 2006
Tel: 886-2-66296288
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
CONTROL DATA
P1 TO P4: SEGMENT DRIVER/GENERAL PURPOSE OUTPUT CONTROL DATA
This control data controls switching SG56/P1~SG53/P4 between segment driver and general purpose
output. When SG56/P1~SG53/P4 is used as general purpose output which will be not affected by
dimming and segment control.
Control Bit
Data
H/L
H/L
H/L
H/L
Output Pin Mode
P1/SG56
P1
P2
P3
P4
P2/SG55
P3/SG54
P4/SG53
When SG56/P1~SG53/P4 is used as general purpose output. The table lists the relationship between
the output pin and control bit as below.
Output Pin Mode
SG56/P1
Control Bit
D56
SG55/P2
D55
SG54/P3
D54
SG53/P4
D53
S0, S1: SLEEP CONTROL DATA
This control data controls switching between sleep mode and normal mode, and also sets the states of
the KS1 to KS5 key scan output pins in key scan standby mode.
Control Data
Clock Generator
(oscillator circuit)
Normal Oscillator operating
Segment Outputs
Output Pin states during key scan standby
Mode
Digit Output
Operating
S0
0
S1
0
KS1
H
KS2
H
KS3
H
KS4
H
KS5
H
0
1
1
1
0
1
Sleep
Sleep
Sleep
Stopped
Stopped
Stopped
L
L
L
L
L
H
L
L
H
L
L
H
L
H
H
H
H
H
CT0 TO CT3: SLEEP CURRENT CONTROL DATA
Control Bit
Current
Mode
CT0
0
1
CT1
0
CT2
0
Normal mode
Test mode
IDD1≤100µA
1
1
IDD1≤5µA
PT6332 V1.0
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February, 2006
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
DM0 TO DM9: DIMMER DATA
This data controls the duty of the SG1 to SG56 segment output pins. This data forms a 10-bit binary
value in which D0 is the LSB. The brightness of the display can be controlled by adjusting the duty of
the SG1 to SG56 segment output pins. The table lists the relationship between the dimmer data and
the dimmer value.
DM9
DM8
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
Dimmer Value (t4/t3)
0/1024
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1/1024
2/1024
to
to
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1020/1024
1021/1024
1022/1024
1022/1024
t3 and t4: see figure 7
PT6332 V1.0
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February, 2006
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VFD Driver/Controller IC
PT6332
RELATIONSHIP BETWEEN THE DISPLAY DAT (D1 TO D168 AND THE
SEGMENT OUTPUT PINS)
1/3 DUTY
Segment
Output Pin
SG1
Segment
Output Pin
SG20
SG21
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SG32
SG33
SG34
SG35
SG36
SG37
SG38
Segment
Output Pin
SG39
SG40
SG41
SG42
SG43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
SG51
SG52
SG53
SG54
SG55
SG56
GR1 GR2
GR3
GR1 GR2
GR3
GR1
GR2
GR3
D1
D2
D3
D4
D5
D6
D7
D8
D9
D57
D58
D59
D60
D61
D62
D63
D64
D65
D113
D114
D115
D116
D117
D118
D119
D120
D121
D122
D123
D124
D125
D126
D127
D128
D129
D130
D131
D20 D76 D132
D21 D77 D133
D22 D78 D134
D23 D79 D135
D24 D80 D136
D25 D81 D137
D26 D82 D138
D27 D83 D139
D28 D84 D140
D29 D85 D141
D30 D86 D142
D31 D87 D143
D32 D88 D144
D33 D89 D145
D34 D90 D146
D35 D91 D147
D36 D92 D148
D37 D93 D149
D38 D94 D150
D39
D40
D41
D42
D43
D95
D96
D97
D98
D99
D151
D152
D153
D154
D155
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
D44 D100 D156
D45 D101 D157
D46 D102 D158
D47 D103 D159
D48 D104 D160
D49 D105 D161
D50 D106 D162
D51 D107 D163
D52 D108 D164
D53 D109 D165
D54 D110 D166
D55 D111 D167
D56 D112 D168
D10 D66
D11 D67
D12 D68
D13 D69
D14 D70
D15 D71
D16 D72
D17 D73
D18 D74
D19 D75
As an example, the table below lists the operation of the SG11 segment output pin.
Display Data
Segment Output Pin (SG11) State
D11
0
D67
0
D123
0
1
0
1
0
1
0
1
The segments corresponding to the GR1 to GR3 digit output pins are off
The segment corresponding to the GR3 digit output pin is on
The segment corresponding to the GR2 digit output pin is on
The segments corresponding to the GR2 to GR3 digit output pins are on
The segment corresponding to the GR1 digit output pin is on
The segments corresponding to the GR1 and GR3 digit output pins are on
The segments corresponding to the GR1 and GR2 digit output pins are on
The segments corresponding to the GR1 to GR3 digit output pins are on
0
0
0
1
1
1
1
0
1
1
0
0
1
1
PT6332 V1.0
- 12 -
February, 2006
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
RELATIONSHIP BETWEEN THE DISPLAY DAT (D1 TO D114 AND THE
SEGMENT OUTPUT PINS)
1/2 DUTY
Segment
Output Pin
SG1
Segment
Output Pin
SG20
SG21
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SG32
SG33
SG34
SG35
SG36
SG37
SG38
Segment
Output Pin
SG39
SG40
SG41
SG42
SG43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
SG51
SG52
SG53
SG54
SG55
SG56
SG57
GR1
GR2
GR1
GR2
GR1
GR2
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D96
D97
D98
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
D111
D112
D113
D114
As an example, the table below lists the operation of the SG11 segment output pin.
Display Data
Segment Output Pin (SG11) State
D11
0
D68
0
The segments corresponding to the GR1 to GR2 digit output pins are off
The segment corresponding to the GR2 digit output pin is on
The segment corresponding to the GR1 digit output pin is on
The segments corresponding to the GR1 to GR2 digit output pins are on
0
1
1
0
1
1
PT6332 V1.0
- 13 -
February, 2006
Tel: 886-2-66296288
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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
SERIAL DATA OUTPUT
When stopped with CL at the low level
CE
CL
1
1
1
1
0
0
0
1
DI
B0
B1
B2
B3
A0
A1
A2
A3
Address
DO
∗
∗
∗
∗
∗
∗
KD1 KD2
KD24 KD25 SA
Output Data
When stopped with CL at the high level
CE
CL
1
1
1
1
0
0
0
1
DI
B0
B1
B2
B3
A0
A1
A2
A3
Address
DO
∗
∗
∗
∗
∗
∗
∗
KD1 KD2 KD3
KD24 KD25 SA
Output Data
Figure 5
Note:
*
: Don’t Care
Address
KD1 to KD25
SA
: Applications must send the value (8FH) as shown in figure 5
: Key Data
: Sleep Acknowledge Data
The key data (KD1 to KD25) and the sleep acknowledge data (SA) will be invalid if the key data is
read when DO is high.
PT6332 V1.0
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VFD Driver/Controller IC
PT6332
OUTPUT DATA
KD1 TO KD25: KEY DATA
These bits represent the key output states when a key matrix with up to 25 keys is formed using the
KS1 to KS5 key scan output pins and the KI1 to KI5 key scan input pins. When a key is pressed, the bit
corresponding to that key will be set to 1. The correspondence is listed in the following table.
Item
KS1
KS2
KS3
KS4
KS5
KI1
KD1
KD6
KD11
KD16
KD21
KI2
KD2
KD7
KD12
KD17
KD22
KI3
KD3
KD8
KD13
KD18
KD23
KI4
KD4
KD9
KD14
KD19
KD24
KI5
KD5
KD10
KD15
KD20
KD25
SA: SLEEP ACKNOWLEDGE DATA
This output data is set to the state when the key was pressed. In that case DO will go to the low level.
If serial data is input during this period and the mode is set (normal mode or sleep mode), the IC will be
set to that mode. SA is set to 1 in the sleep mode and to 0 in the normal mode.
SLEEP MODE
The IC is set to sleep mode by setting either S0 or S1 in the control data to 1. The segment outputs and
the digit outputs are all set low, and the clock generator (oscillator circuit) is stopped (although it is
restarted when a key is pressed), and thus power dissipation is reduced. This mode is cleared by
setting S0 and S1 in the control data to 0.
In sleep mode, the status of segment/general purpose output port will not be changed.
PT6332 V1.0
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VFD Driver/Controller IC
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KEY SCAN OPERATION
KEY SCAN TIMING
The scan period is 18000T [s]. A key scan is performed twice to reliably recognize the key on/off state
by verifying that the key data for the two scans agrees. If the data agrees, the IC recognizes a key
press and 38400T [s] after the start of key scan execution issues a key scan data read request by
outputting a low level from DO. If the key data does not agree and a key was pressed at the later scan,
the IC executes another key scan operation. Note that this means that this IC cannot recognize a key
press shorter than 38400T [s].
KS1
KS2
KS3
KS4
∗
∗
∗
∗
1
1
2
2
∗
∗
∗
∗
3
3
4
4
KS5
5
5
36000T [s]
Key on
1
fosc
T=
[s]
Note:
*: The high-level and low-level state in sleep mode are set according to the control data S0 and S1.
Key scan output signals are not output from pins set to the “L” state.
IN NORMAL MODE
•
•
The pins KS1 to KS5 are set high.
A key scan is started when any of the keys is pressed, and the keys are kept scanning until all keys
are released. The controller can recognize simultaneous multiple key presses by checking the key
data for multiple bits being set.
•
•
If a key is pressed for over 38400T [s] (where T=1/fosc), the IC outputs a key data read request to
the controller by setting DO low. The controller acknowledges this state and reads the key data.
However, note that DO will go high when CE is set high during the serial data transfer.
After the controller key data readout completes, the key data read request will be cleared (DO will
be set high), and the IC performs another key scan. Note that since DO is an open-drain output, a
pull-up resistor (between 1 and 10KΩ) is required.
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VFD Driver/Controller IC
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Key Input 1
Key Input 2
Key scan
38400T[s]
38400T[s]
38400T[s]
CE
Serial data transfer
Serial data transfer
Key address
Key address (8FH)
Serial data transfer
Key address
DI
DO
Key data r ead
Key data read
Key data r ead request
Key data read
1
fosc
Key data r ead request
Key data r ead request
T =
[s]
IN SLEEP MODE
•
The pins KS1 to KS5 are set to high or low according to the values of S0 and S1 in the control data.
(see the description of the control data elsewhere in this document)
•
If a key connected to one of the KS1 to KS5 lines that was set high is pressed, the clock generator
(oscillator circuit) is started and a key scan is performed, and the keys are kept scanning until all
keys are released. The controller can recognize simultaneous multiple key presses by checking
the key data for multiple bits being set.
•
•
•
If a key is pressed for over 38400T [s] (where T=1/fosc), the IC outputs a key data read request to
the controller by setting DO low. The controller acknowledges this state and reads the key data.
However, note that DO will go high when CE is set high during the serial data transfer.
After the controller key data readout completes, the key data read request will be cleared (DO will
be set high), and the IC performs another key scan. However, sleep mode will not be cleared. Note
that since DO is an open-drain output, a pull-up resistor (between 1 and 10KΩ) is required.
Example of a key scan operation in sleep mode.
Example: Sleep mode with S1=0, S1=1 (only KS5 is set high)
(L) KS 1
If any one of these keys is pressed,
the os cillator on the OSC pin is start ed
and the keys are s cann ed.
(L) KS 2
(L) KS 3
(L) KS 4
(H ) KS5
∗
KI 1
KI2
KI3
KI 4
KI 5
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Note:
*: These diodes are required to reliably recognize multiple key presses on the KS5 line when the IC is
set to sleep mode with only KS5 set to high as in the example above. That is, they prevent incorrect
recognition of key pressed due to sneak currents arising from simultaneous presses of keys on the
KS1 through KS4 lines.
Key Input
(KS6 line)
Key scan
615T[s]
615T[s]
CE
Key address (43H)
Key address
Serial data transfer
Serial data transfer
Serial data transfer
DI
DO
Key data read
Key data read
1
fosc
Key data read request
Key data read request
T=
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VFD Driver/Controller IC
PT6332
MULTIPLE KEY PRESSES
The PT6332, even without diodes in the key scan lines, can scan for any combination of dual key
presses, any combination of triple key presses on any of the KI1 to KI5 key scan input pin lines, or any
combination of multiple key presses on any of the KS1 to KS5 key scan output lines. However, keys
that are not pressed may be seen as having been pressed for any other multiple key press combination.
Accordingly, applications must insert diodes at each key. Also, to reject any triple and higher multiple
key presses, if three or more data readout are 1 ignore the data by the software or in other ways.
NOTES ON THE /BLK PIN AND DISPLAY CONTROL
Since the states of the IC internal data (D1 to D168, and the control data) are undefined when power is
first applied, applications should turn off the display (i.e. set SG1 to SG56 and GR1 to GR3 low) by
setting the /BLK pin low at the same time as power is applied. Applications should transfer all 264 bits
of the serial data while /BLK is held low, and only then set /BLK high. This will prevent random
meaningless display at power on. (see figure 6)
toff1
toff2
ton
V
DD
VFL
/BLK
CE
V
IL
tc
V
IL
Display and control data transfer
Undefined
Internal d ata
D1 to D5 6
C ontrol data
Defined
Defined
Defined
Undefined
Undefined
Undefined
Internal d ata
D5 7 to D 112
Undefined
Undefined
Internal d ata
D 113 to D1 68
ton > 0
toff1 > 0
toff2 > 0 (toff1 > toff2)
tc⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅1 0µ s min.
Figure 6
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VFD Driver/Controller IC
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NOTE ON THE POWER ON SEQUENCE
Applications must observe the following sequence when turning the power on or off.
•
•
At power on: First turn on the logic system power (VDD), and then turn on the driver power (VFL).
At power off: First turn off the driver power (VFL), and then turn off the logic system power (VDD).
V
2V
t
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OUTPUT WAVEFOORMS (SG1 TO SG56)
1/3 DUTY
VFL
GR1
V
SS
VFL
GR2
GR3
V
SS
VFL
V
SS
VFL
SG1 to SG56 w aveform wh en the seg men t
corre spo nding to GR1 is on
V
SS
VFL
SG1 to SG56 w aveform wh en the seg men t
corre spo nding to GR2 is on
V
SS
VFL
SG1 to SG56 w aveform wh en the seg men t
corre spo nding to GR3 is on
V
SS
VFL
SG1 to SG56 w aveform wh en the seg men ts
corre spo nding to GR1 an d GR2 are on
V
SS
VFL
SG1 to SG56 w aveform wh en the seg men ts
corre spo nding to GR1 an d GR3 are on
V
SS
VFL
SG1 to SG56 w aveform wh en the seg men ts
corre spo nding to GR2 an d GR3 are on
V
SS
SG1 to SG56 w aveform wh en the seg men ts
corre spo nding to GR1 , GR2 a nd GR3 are on
VFL
V
SS
VFL
SG1 to SG56 w aveform wh en the seg men ts
corre spo nding to GR1 , GR2 a nd GR3 are off
V
SS
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VFD Driver/Controller IC
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OUTPUT WAVEFOORMS (SG1 TO SG57)
1/2 DUTY
VFL
GR1
V
SS
VFL
GR2
V
SS
VFL
SG1 to SG57 w aveform wh en the seg men t
corre spo nding to GR1 is on
V
SS
VFL
SG1 to SG57 w aveform wh en the seg men t
corre spo nding to GR2 is on
V
SS
SG1 to SG57 w aveform wh en the seg men ts
corre spo nding to GR1 , GR2 a re o n
VFL
V
SS
VFL
SG1 to SG57 w aveform wh en the seg men ts
corre spo nding to GR1 , GR2 a re o ff
V
SS
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PT6332
RELATIONSHIP BETWEEN THE SEGMENT AND DIGIT OUTPUTS
VFL
GR1
GR2
t3
t3
V
SS
VFL
t3
t3
V
SS
VFL
GR3
SG1 to SG7 2
SG1 to SG7 2
t3
t1
t1
t1
t3
t1
t1
t1
V
SS
VFL
t2
t4
t2
t4
Exa mple 1
Exa mple 2
V
SS
VFL
t2
t2
t4
t2
t2
t4
t4
V
SS
t4
VFL
Exa mple 3
SG1 to SG7 2
V
SS
Figure 7
•
Figure 7 shows the case where the display data is set up so that the segment outputs SG1 to SG56
output the VSS level with the same timing as the GR1 and GR3 digit outputs, and output the VFL
level with the same timing as the GR2 digit output. Here, the segments corresponding to GR2 will
be turned on. The relationship between t3 and the oscillator frequency fosc in this case is
t3=2048/fosc.
•
•
The SG1 to SG56 segment output waveforms in example 1 correspond to a dimmer data (DM0 to
DM9) set to 3FEH. The relationship between t1 and the oscillator frequency fosc is t1=2/fosc. Note
that t1 and t2 in example 1 are identical times.
The SG1 to SG56 segment output waveforms in example 2 correspond to a dimmer data (DM0 to
DM9) set to a smaller value. Although t1 does not change, t2 becomes longer. Here, if the dimmer
data (DM0 to DM9) is set to 1FFH and the oscillator frequency fosc is 2.4MHz, then t2 can be
calculated as follows.
t2 = t3 − t1×
(
1FFH +1
)
1024
=
fosc
[
= 0.43 ms
]
•
If the dimmer data (DM0 to DM9) is set to an even smaller value, t2 will become even longer as
shown in example 3. Note that t1 does not change in this case as well.
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VFD Driver/Controller IC
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BLOCK STATES DURING THE RESET PERIOD
(when /BLK is low)
•
•
•
•
•
•
Divider and timing generator
These circuits are reset and their base clock is stopped.
Dimmer timing generator
The circuit is reset and its operation is stopped.
Digit and segment dividers
These circuits are reset and the display is turned off (SG1 to SG56 and GR1 to GR3 are set low).
Key scan
The circuit is reset, its internal circuits are set to the initial state, and key scanning is disabled.
Key buffer
The circuit is reset and all data is set to 0.
Clock generator
The state (normal or sleep mode) of this block (the clock oscillator circuit) is determined after the
sleep control data (S0 to S1) is transferred.
•
CCB interface, shift register, control register, latch, and multiplexer
The circuits are not reset so that serial data can be input during the reset period.
Grid
D rive r
Segment Driver
57
MPX
17 1
/BLK
VFL
VDD
VSS1
VSS2
La tch
D im me r
Timin g
Ge nerato r
Con tro l
R egiste r
16
57
Shift Reg ister
Tim in g
Ge nerato r
Key Buffer
Divider
C om ma nd
Inte rfa ce
Key Sca n
Clo ck
OSCI
Ge nerato r
Block than are reset
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VFD Driver/Controller IC
PT6332
OUTPUT PIN STATES DURING THE RESET PERIOD
(when /BLK is low)
Output Pin
SG1 to SG56
GR1 to GR3
KS1 to KS4
KS5
State during Reset
L
L
X *1
H
DO
H *2
Notes:
1. The state of this pin is undefined after power has been applied until the sleep control data (S0 to S1)
are transferred.
2. Since this pin is an open-drain output, a pull-up resistor (between 1 and 10KΩ) is required. It
remains high during the reset period even if the controller attempts to read the key data.
NOTE ON THE SEGMENT AND DIGIT WAVEFORMS
Digit wa ve form
Segment w aveform 1
Segment w aveform 2
Figure 8
The digit waveform is somewhat deformed due to the VFD panel itself and the circuit wiring.
Furthermore, if a segment waveform such as segment waveform 1 in which no dimming is applied is
used, the display will glow dimly. Therefore, applications must take this waveform deformation into
account and apply adequate dimming such as that shown in segment waveform 2 so that this
phenomenon does not occur.
NOTE ON CONTROLLER TRACSFER OF DISPLAY DATA
Since the display data is transferred in three operations as shown in figures 1 & 2, we strongly
recommend that applications transfer all the data within a 30ms period to assure display quality.
PT6332 V1.0
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VFD Driver/Controller IC
PT6332
CONTROLLER KEY DATA READOUT PROCEDURE
WHEN THE CONTROLLER USES A TIMER TO READ OUT THE KEY DATA
•
Flowchart
CE=L
DO=L
NO
YES
Key data read
processing
•
Timing Chart
Key Input
Key on
Key on
Key Scan
t6
t5
t5
t5
CE
DI
t8
t8
t8
t7
t7
t7
Key data read
DO
Key data read request
t9
t9
t9
t9
Controller determination
(key on)
Controller determination
(key on)
Controller determination
(key off)
Controller determination
(key on)
Controller determination
(key off)
t5
- Key scan execution time (38400T [s]) when the key data for two key scan operations matches.
t6
- Key scan execution time (76800T [s]) when the key data for the first two key scan operations
does not match.
t7
t8
- Key address (8FH) transfer time
- Key data readout time
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VFD Driver/Controller IC
PT6332
•
Operation
When the controller use timer processing for key on/off determination and key data readout, it must set
CE low and check the state of DO at least once every t9 period. If DO is low, the controller must
recognize that a key has been pressed and read out the key data.
The period t9 must obey the following inequality:
t9 > t7 + t8 + t6
Note: If the controller reads out key data when DO is high, both the key data (KD1 to KD25) and the
sleep acknowledge data will be invalid data.
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VFD Driver/Controller IC
PT6332
WHEN THE CONTROLLER USES INTERRUPT PROCESSING TO READ OUT THE
KEY DATA
•
Flowchart
CE=L
DO=L
NO
YES
Key data read
processing
Wait period
(st Least t10)
CE=L
NO
DO=H
YES
Key off
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VFD Driver/Controller IC
PT6332
•
Timing Chart
Key Input
Key on
Key on
Key Scan
t5
t5
t6
t5
CE
DI
t8
t8
t8
t8
Key address
t7
t7
t7
t7
Key data read
DO
Key data read request
t10
t10
t10
t10
Controller
determination
(key on)
Controller
Controller
determination
(key on)
Controller
Controller
Controller
determination
(key off)
determination
determination
determination
(key off)
(key on)
(key on)
t5
- Key scan execution time (38400T [s]) when the key data for two key scan operations matches.
t6
- Key scan execution time (76800T [s]) when the key data for the first two key scan operations
does not match.
t7
- Key address (8FH) transfer time
1
T =
[s]
fosc
t8
- Key data readout time
•
Operation
When the controller use interrupt processing for key on/off determination and key data readout, it must
check the state of DO when CE is low, and perform a key data readout if DO is low. The next time the
controller checks the on/off states of the keys, it must make that determination at a time t10 after the
last readout on the state of DO when CE is low, and then read out the key data.
The time t10 must obey the following inequality:
t10 > t6
Note:
1. If the controller reads out key data when DO is high, both the key data (KD1 to KD25) and the sleep
acknowledge data will be invalid data.
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VFD Driver/Controller IC
PT6332
ABSOLUTE MAXIMUM RATINGS
(VSS=0V, Ta=25
℃)
Parameter
Symbol
VDD max VDD
VFL max VFL
Condition
Rating
-0.3 ~ +6.5
-0.3 ~ +20
Unit
V
V
Maximum Supply Voltage
VIN1
VIN2
DI, CL, CE, /BLK
OSCI, KI1 to KI5
SG1 to SG52,
-0.3 ~ VDD+0.3
-0.3 to VDD+0.3
V
V
Input Voltage
VOUT1
SG53/P4 to SG56/P1,
GR1, GR2, GR3/SG57
KS1 to KS5
-0.3 to VFL+0.3
V
Output Voltage
VOUT2
VOUT3
-0.3 to VDD+0.3
-0.3 ~ VDD+0.3
V
V
DO
SG1 to SG52,
IOUT1
6
µA
SG53/P4 to SG56/P1
GR1, GR2, GR3/SG57
KS1 to KS5
Output Current
IOUT2
IOUT3
60
1
400
mA
mA
mW
℃
Allowable Power Dissipation
Operating Temperature
Storage Temperature
Pd max Ta=85
℃
Topr
Tstg
-
-
-40 to +85
-65 to +150
℃
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VFD Driver/Controller IC
PT6332
ALLOWABLE OPERATING RANGES
(Ta=25
℃, VDD=3.3 to 5V, VFL=18V, VSS=0V)
Parameter
Symbol
VDD
Condition
Min
3
8
0.8 VDD
0.6 VDD
Typ
5.0
12
-
Max
5.5
18
5.5
VDD
Unit
V
V
V
V
VDD
VFL
Supply Voltage
VFL
VIH1
VIH2
DI, CL, CE, /BLK
KI1 to KI5
DI, CL, CE, /BLK,
KI1 to KI5
Input High-Level Voltage
Low-Level Input Voltage
-
VIL
0
0.2 VDD
V
Guaranteed Oscillator Range
Recommended External
Resistance
fosc
ROSC
OSCI
0.9
-
-
2.4
12
7.5
3.7
-
-
MHz
KΩ
VDD=5V
VDD=3.3V
OSCI
Recommended External
Capacitance
COSC
t∅L
t∅H
tds
OSCI
15
33
100
pF
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
5V
3.3V
5V
3.3V
5V
3.3V
5V
3.3V
5V
3.3V
5V
3.3V
5V
3.3V
5V
160
240
160
240
160
240
160
240
160
240
160
240
160
240
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Clock Low-Level Pulse Width
Clock High-Level Pulse Width
Data Setup Time
CL: Figure 9
CL: Figure 9
DI, CL: Figure 9
DI, CL: Figure 9
CE, CL: Figure 9
CE, CL: Figure 9
CE, CL: Figure 9
Data Hold Time
tdh
tcp
CE Wait Time
CE Setup Time
tcs
CE Hold Time
tch
-
DO, RPU=4.7KΩ,
CL=10pf*: Figure 9
DO, RPU=4.7KΩ,
CL=10pf*: Figure 9
1.5
1.6
1.5
1.6
-
DO Output Delay Time
DO Rise Time
tdc
3.3V
5V
3.3V
5V
-
-
-
10
tdr
/BLK Switching Time
tC
/BLK, CE: Figure 6
3.3V
14
-
PT6332 V1.0
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VFD Driver/Controller IC
PT6332
ELECTRICAL CHARACTERISTICS
(Ta=25
℃, VDD=3.3 to 5V, VFL=18V, VSS=0V)
Parameter
High Level Input
Current
Symbol
Conditions
Min.
Typ.
Max.
Unit
IIH
DI, CL, CE, /BLK: VIN=5.0V
-
-
5
µA
Low Level Input
Current
Input Floating
Voltage
IIL
DI, CL, CE, /BLK, VIN=0V
KI1~KI5
-5
-
-
µA
V
VIF
-
-
100
-
0.05VDD
Pull-down
RPD
IOFFH
KI1~KI5: VDD=5.0V
DO: VO=5.0V
50
-
250
KΩ
µA
Resistance
Output Off Leakage
Current
5
-
SG1~SG52,
SG53/P4~SG56/P1: IO=-2mA
GR1, GR2, GR3/SG57: IO=-50mA VFL-1.3
VOH1
VOH2
VOH3
VFL-0.6
-
-
V
V
V
High Level Output
Voltage
-
5V
3.3V
VDD-1.2 VDD-0.5
VDD-1.2 VDD-0.5
VDD-0.2
VDD-0.2
KS1~KS5: IO=-500µA
SG1~SG52,
VOL1
SG53/P4~SG56/P1,
-
-
0.5
V
GR1, GR2, GR3/SG57: IO=50µA
5V
KS1~KS5: IO=25µA
3.3V
Low Level Output
Voltage
0.2
0.2
0.5
0.5
0.1
0.1
2.4
1.5
1.2
0.5
0.4
-
VOL2
VOL3
V
V
5V
-
-
-
-
-
DO: IO=1mA
3.3V
ROSC=12KΩ, COSC=33pF
ROSC=7.5KΩ, COSC=33pF
DI, CL, CE, /BLK, KI1~KI5
C0~C2=0
Sleep mode, Normal mode
Figure 1~4
C0~C2=1
5V
3.3V
Oscillator Frequency
Hysteresis Voltage
fOSC
VH
MHZ
V
1.7
0.1VDD
-
-
-
-
100
IDD1
IDD2
µA
Current Drain
-
-
-
-
5
Test mode
Output open: fOSC=2.4MHz
10
mA
PT6332 V1.0
- 32 -
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
When stopped with CL at the low level
V
IH 1
CE
V
IL
tφ
H
tφ
L
V
IH1
50 %
CL
V
IL
tcp tcs
tch
V
IH1
IL
DI
V
tds
tdh
DO
D0
D1
tdc
tdr
When stopped with CL at the HIGH level
V
IH 1
V
IL
CE
tφ
H
tφ
L
V
IH1
50 %
CL
DI
V
IL
tcp tcs
tch
V
IH1
IL
V
tds
tdh
D0
D1
DO
tdr
tdc
Figure 9
PT6332 V1.0
- 33 -
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
APPLICATION CIRCUIT
Key matrix with up to 25 keys
VSS1
KS1
61
62
63
40
39
38
SG21
SG22
SG23
KS2
64
65
66
67
KS3
KS4
SG24
SG25
37
36
KS5
KI1
KI2
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SG26
SG27
68
69
70
71
72
73
74
75
76
77
78
79
80
SG28
SG29
KI3
KI4
SG30
KI5
SG31
SG32
PT6332
DT
/BLK
DO
SG33
SG34
VDD
MCU
CE
SG35
*
CL
SG36
SG37
SG38
DI
VDD
OSCI
VSS2
5V/3.3V
SG39
SG40
33p
12K
Note: *- Since DO is an open-drain output, a pull-up resistor is required. Select a value in the range 1 to
10KΩ that is most appropriate for the capacitance of the external lines so that the waveform is not
distorted.
PT6332 V1.0
- 34 -
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
ORDER INFORMATION
Valid Part Number
Package Type
Top Code
PT6332-LQ
PT6332-LQ
80 Pin, LQFP
PT6332 V1.0
- 35 -
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
PACKAGE INFORMATION
80 PINS, LQFP (BODY SIZE: 12MMx12MM, PITCH: 0.50MM,
THK: 1.40MM)
D
D1
A
A2
-D-
A1
-A-
-B-
c
e
b
θ
1
C SEATING PLANE
θ
ccc
C
θ
2
R1
R2
-H-
GAUGE PLANE
0.25mm
S
L
θ
3
PT6332 V1.0
- 36 -
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
VFD Driver/Controller IC
PT6332
Symbol
Min.
-
Nom.
Max.
1.60
0.15
1.45
0.27
A
A1
A2
b
-
0.05
1.35
0.17
-
1.40
0.22
D
14.00 BSC.
D1
e
12.00 BSC.
0.50 BSC.
E
14.00 BSC.
E1
S
12.00 BSC.
0.20
0.08
0.08
0.45
-
-
R1
R2
L
-
-
-
0.20
0.75
0.60
L1
C
1.00 REF.
-
0.09
0.20
θ
0
°
°
°
°
3.5
°
7°
-
-
θ1
θ2
θ3
0
11
12°
13
°
°
11
12°
13
ccc
0.08
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. The top package body may be smaller than the bottom package size as much as 0.15mm.
3. Datum A-B and D to be determined at the datum plane H.
4. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25mm per side.
d1 and E1 are maximum plastic body size dimensions including mold mismatch.
5. Controlling Dimensions: Millimeters
6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the
lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be located
on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm
for 0.4mm and 0.5mm pitch package.
7. A1 is defined as the distance from the seating plane to the lowest point on the package body.
8. Refer to JEDEC MS-026 Variation BDD.
JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY CORPORAITON.
PT6332 V1.0
- 37 -
February, 2006
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