DI-40 [POWERINT]
2.5 V, 20 W DC-DC Converter with Synchronous Rectification; 2.5 V ， 20W的DC-DC转换器采用同步整流
| 型号： | DI-40 |
| 厂家： | 
Power Integrations |
| 描述： | 2.5 V, 20 W DC-DC Converter with Synchronous Rectification |
| 文件： | 总2页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Design Idea DI-40
DPA-Switch 2.5 V, 20 W DC-DC
Converter with Synchronous Rectification
Topology
Forward
Device
Power Output
Input Voltage
Output Voltage
Application
DC-DC Converter
20 W
36-75 VDC
DPA424R
2.5 V
Capacitor C8 and the gate capacitance of Q1 reset T1 during
DPA-Switch off-time. Zener VR1 provides a hard voltage
clamp to limit DRAIN voltage under output transient and
overload conditions.
Design Highlights
• Extremely low component count
• High efficiency - 86% using synchronous rectification
• No current sense resistor or current transformer required
• Output overload, open loop and thermal protection
• Accurate input under/overvoltage meets ETSI standards
• 300 kHz switching frequency - optimizes efficiency when
simple self-driven synchronous rectification is used
Since the output voltage is low, the U2 LED is supplied with
a higher voltage derived from a winding on output choke L2.
The DPA-Switch bias supply is derived from a forward
winding on transformer T1. Flyback windings are not
recommended for this purpose, since the bias capacitor C4
would create high capacitive loading during DPA-Switch
off-time,preventingthetransformerfromefficientlyresetting.
Operation
DPA-Switchgreatlysimplifiesthedesigncomparedtoadiscrete
implementation. Resistor R1 programs the input UV/OV
thresholds. The tight tolerance of the UV/OV thresholds limits
the range of gate drive voltages applied to MOSFETs Q1 and
Q2, eliminating the need for gate voltage clamp circuitry. The
self-drivensynchronousrectificationconfigurationistherefore
very simple, with R13 filtering voltage spikes at the gate of Q2,
and D3 preventing the body diode of Q1 from conducting.
Key Design Points
• For nominal under-voltage set point VUV
:
R1=(VUV- 2.35 V)/50 µA. VOV = (R1 x 135 µA)+2.5 V.
• Locate C5, C6, and R4 close to U1 CONTROL pin, with
ground connected to SOURCE pin.
• Minimize primary and secondary layout loop area to
reduce parasitic inductance.
C7
1 nF
R14
1.5 kV
10
Ω
L2
+
VIN
D3
3.3 µH
36 - 75 VDC
T1
2.5 V, 8 A
12CWQ03FM
8 A
5, 6
1
7, 8
1
9, 10
L1
1 µH 2.5 A
2
R13
10 Ω
C9, C10
100 µF
10 V
C11
1 µF
10 V
D2
BAV19WS
Q1
SI4842DY
R1
619 kΩ
RTN
6, 7
Q2
SI4842DY
C1, C2
1 µF
100 V
C3
1 µF
100 V
C8
R5
2.2 nF 1.0 Ω
C12
4.7 µF
20 V
4
2
3
L3
D1
2.2 mH
40 mA
BAV19WS
C4
1 µF
D4
BAV19WS
U2
PC357
N1T
U2
DPA-Switch
L
D
R7
10 kΩ
U1
R10
10.2 kΩ
1%
CONTROL
DPA424R
C
VR1
SMBJ150
C13
100 nF
S
X
F
R4
1.0 Ω
D3
BAV19WS
R6
R12
C5
0.22 µF
150 Ω
5.1 Ω
R9
R3
15 kΩ
1%
C6
68 µF
10 V
220 Ω
C15
10 µF
10 V
U3
LMV431
AIM5X
C14
1 µF
VIN
R11
10.0 kΩ
1%
PI-3264-051303
Figure 1. DPA-Switch 20 W DC to DC Converter.
.
May 2003
DI-40
www.powerint.com
DI-40
• OptocouplerU2shouldhavecontrolledCTRof100-200%
for optimum loop stability.
TRANSFORMER PARAMETERS
• Size transformer reset components C8 and R5, and the Q1
gate capacitance to assure transformer reset at minimum
operating voltage without exceeding 170 V drain voltage
at high line.
PR1408
EPCOS N87 material ungapped
Core Material
P1408 8 pin
(B&B B-096 or equivalent)
Bobbin
Turns
• Set Zener VR1 clamp voltage to 150 V to guarantee both
Bias: 6T, 32 AWG
Primary: 7T + 7T, 2 x 28 AWG
Secondary: 2T, 4 x 26 AWG
transformer reset and limit DRAIN voltage below BVDSS
.
• Scale primary side forward bias winding to provide
12 V to 15 V at minimum input voltage, nominal load.
• Secondary choke winding provides 5 V at nominal load.
• Main primary power return should be connected to the
DPA-Switch tab, not to the SOURCE pin.
Bias: (3-2), Tape
Primary: (4-FL), Tape
Secondary: (6, 7-9, 10), Tape
Primary: (FL-10), Tape
Winding Order
(Pin Numbers)
• Consult AN-31 for additional design tips.
Primary Inductance
392 µH ± 25%
3 MHz (minimum)
1 µH (maximum)
Primary Resonant
Frequency
95
90
85
80
75
Leakage Inductance
Table 1. Transformer Construction Information.
OUTPUT INDUCTOR PARAMETERS
EPCOS N87 material
VIN = 36 VDC
70
Gap for AL of 206 nH/T2
Core
VIN = 48 VDC
VIN = 60 VDC
VIN = 72 VDC
65
60
P1408 8 pin
Bobbin
(B&B B-096 or equivalent)
Bias: 10T, 32 AWG
Winding Details
Main: 4T, 4 x 26 AWG
0
5
10
Output Power (W)
Figure 2. Efficiency vs. Output Power.
15
20
Winding Order
(Pin Numbers)
Bias: (1-2), Tape
Main: (7,8-5,6), Tape
Inductance Pins 5,6-7,8
3.3 µH ± 10%
Table 2. Output Inductor Construction Information.
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Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license
under its patent rights or the rights of others. The products and applications illustrated herein (including circuits external to the products and
transformer construction) may be covered by one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent
applications assigned to Power Integrations. A complete list of Power Integrations’ patents may be found at www.powerint.com.
The PI Logo, TOPSwitch, TinySwitch, LinkSwitch and EcoSmart are registered trademarks of Power Integrations, Inc.
PI Expert and DPA-Switch are trademarks of Power Integrations, Inc. ©Copyright 2003, Power Integrations, Inc.
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