RM7000C-533T [PMC]
Microprocessor,;
| 型号： | RM7000C-533T |
| 厂家： | 
PMC-SIERRA, INC |
| 描述： | Microprocessor, |
| 文件： | 总2页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RM7000C™
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
•
Fast Packet Cache™ increases
system efficiency in networking
applications
• Integrated memory management unit
FEATURES
•
•
•
Fully associative joint TLB (shared
by I and D translations)
• Dual issue symmetric superscalar
microprocessor with instruction
prefetch optimized for system level
price/performance
• Integrated external cache controller
(up to 64 MB)
64/48 dual entries map 128/96
pages
•
User-selectable EZ Cache protocol
eliminates the need for external tag
RAMs.
Variable page size
•
533, 600 MHz operating frequency
• Embedded application enhancements
•
>1080 Dhrystone 2.1 MIPS @ 600
MHz
•
Specialized DSP integer Multiply-
Accumulate instructions,
• High-performance floating-point unit -
1600 MFLOPS maximum
• High-performance system interface
(MAD/MADU) and three-operand
multiply instruction (MUL)
•
•
•
1280 MB per second peak
throughput
•
•
•
Single cycle repeat rate for common
single-precision operations and
some double-precision operations
•
•
•
I&D Test/Break-point (Watch)
registers for emulation & debug
200 MHz maximum frequency using
HSTL signaling on the SysAD bus
Single cycle repeat rate for single-
precision combined multiply-add
operations
Performance counter for system
and software tuning & debug
Multiplexed address/data bus
(SysAD) supports 1.5 V, 2.5 V, 3.3
V I/O logic
Fourteen fully prioritized vectored
interrupts - 10 external, 2 internal, 2
software
Two cycle repeat rate for double-
precision multiply and double-
precision combined multiply-add
operations
•
Processor clock multipliers 2, 2.5, 3,
3.5, 4, 4.5, 5, 6, 7, 8, 9
• Fully static CMOS design with dynamic
power down logic
• Pin compatible with RM5271, RM7000,
RM7000A and RM7000B in 304-pin
TBGA package, 31x31 mm
• Integrated primary and secondary
caches
• MIPS IV superset instruction set
architecture
•
•
•
All are 4-way set associative with
32-byte line size
•
Data PREFETCH instruction allows
the processor to overlap cache miss
latency and instruction execution
16 KB instruction, 16 KB data, 256
KB on-chip secondary
Per line cache locking in primaries
and secondary
•
Single-cycle floating-point multiply-
add
BLOCK DIAGRAM
64-bit Integer Unit
Dual-Issue Superscalar
System Control
PC Unit
64-bit FP Unit
Double/Single IEEE754
Integer Multiplier
Instr. Dispatch
I-Cache
MMU
D-Cache
16KB, 4-way, lockable
Fully Assoc., 48 or 64 Entry
16KB, 4-way, lockable
System Cache (L2)
256KB, 4-way, lockable
Bus Interface Unit
L3 Cache Control
Int Ctlr
64-bit
SysA /D Bus & L3 Ctr
NMI, INT9 – INT0
PMC- 2011604 (R3)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2002
RM7000C™
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
•
Red Hat
PACKAGING
APPLICATIONS
• Evaluation Boards and Companion
Chips
• Voice Gateways
•
Fully Static 0.13µ CMOS design
with dynamic power down logic
• Multi-Service Access Platforms
• DSLAMs/Access Concentrators
• Remote Access Switches
• Web Switches
• Layer 3 Switches
• Backbone Switches/Routers
• RAIDs
• Set Top Boxes
• Networked Printers
• Cellular Base Stations
•
Marvell Technology
•
304 pin TBGA package, 31x31 mm
•
EV-64120A-7000: 32/64-bit,
33/66MHz PCI
DEVELOPMENT TOOLS
• Operating Systems:
•
EV-64240-7000: 32/64-bit,
33/66MHz PCI
•
•
Momentum Computer
•
•
•
•
Linux by MontaVista and Red Hat
VxWorks by Wind River Systems
Nucleus by Accelerated Technology
Neutrino by QNX Software Systems
•
Ocelot-C Compact PCI Develop-
ment Platform
Logic Analyzers and Emulation
•
•
•
•
HP
Tektronix
Corelis
Crescent Heart Software
• Compiler Suites
•
Algorithmics
•
Green Hills Software
TYPICAL APPLICATION
RM7000C
64-Bit
100MHz
L3 Cache
SDRAM
64-Bit
100MHz
Marvell
GT-64240
64-
bit
PCI Bus
32/64-bit @ 33MHz
Data
Buffer
64-
bit
32-
bit
32-
bit
8-bit
Boot-Flash
PCI-to-PCI
Bridge
Ethernet
MAC
Ethernet
MAC
Flash
Disk
Watchdog,
I2C & Control
Registers
Dual UART
Head Office:
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
PMC- 2011604 (R3)
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
© Copyright PMC-Sierra, Inc. 2002. All
rights reserved. RM7000C is a trademark of
PMC-Sierra Inc.
Tel: 604.415.6000
Fax: 604.415.6200
info@pmc-sierra.com
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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