RM7035C [PMC]

Microprocessor,;


型号：	RM7035C
厂家：	PMC-SIERRA, INC
描述：	Microprocessor,
文件：	总2页 (文件大小：88K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RM7035C/RM7065C

Microprocessors

Preliminary

64-Bit MIPS RISC Microprocessors with Integrated L2 Cache

•

16 Kbytes instruction, 16 Kbytes

data, 256 Kbytes on-chip

secondary.

•

Single-cycle floating-point multiply-

add.

FEATURES

• Dual issue symmetric superscalar

microprocessor with instruction

prefetch optimized for system level

price/performance:

• Integrated memory management unit:

•

Per line cache locking in primaries

and secondary.

•

Fully associative joint TLB (shared

by I and D translations).

Fast Packet Cache™ increases

system efficiency in networking

applications.

64/48 dual entries map 128/96

pages.

•

466, 533, 600 MHz operating

frequency.

Variable page size.

•

>1380 Dhrystone 2.1 MIPS @

600 MHz.

• High-performance floating-point unit -

1600 MFLOPS maximum:

• Embedded application enhancements:

•

Specialized DSP integer Multiply-

Accumulate instructions,

(MAD/MADU) and three-operand

multiply instruction (MUL).

• High-performance system interface:

•

Single cycle repeat rate for common

single-precision operations and

some double-precision operations.

•

1600 Mbyte/s peak throughput.

•

200 MHz maximum frequency using

HSTL signaling on the SysAD bus.

Single cycle repeat rate for single-

precision combined multiply-add

operations.

•

I&D Test/Break-point (Watch)

registers for emulation & debug.

•

Multiplexed address/data (SysAD)

bus supports 1.5 V, 2.5 V, 3.3 V I/O

logic.

Performance counter for system

and software tuning & debug.

Two cycle repeat rate for double-

precision multiply and double-

precision combined multiply-add

operations.

•

Processor clock multipliers 2, 2.5, 3,

3.5, 4, 4.5, 5, 6, 7, 8, 9.

14 fully prioritized vectored

interrupts - 10 external, 2 internal, 2

software.

Support for 64- or 32-bit interfaces.

• Integrated primary and secondary

caches:

• MIPS IV superset instruction set

architecture:

•

All are 4-way set associative with

32-byte line size.

•

Data PREFETCH instruction allows

the processor to overlap cache miss

latency and instruction execution.

Integrated External External Bus

CPU Frequency

VccInt VccIO

Device

I/D Cache

L2 Cache

Support

Bus

Width

Frequency

(MHz)

Package

(MHz)

(V)

RM7035C

RM7065C

466,533,600

16KB/16KB

256 KB

32-bit

64-bit

200

1.3

2.5/3.3 128-ExposedPad™

2.5/3.3

256-TBGA or

216-ExposedPad™

BLOCK DIAGRAM

64-bit Integer Unit

Dual-Issue

64-bit Floating-Point Unit

Double / Single

IEEE 754

System Control

PC Unit

Superscalar

Integer Multiplier

Instruction Dispatch

Memory Management Unit

Fully Associative

Instruction Cache

16 KB, 4-way, lockable

Data Cache

16 KB, 4-way, lockable

48 or 64 Entry

System Cache (L2)

256 KB, 4-way, lockable

Bus Interface Unit

Interrupt Controller

NMI, INT9 – INT0

32-bit (RM7035C)

32/64-bit (RM7065C)

SysAD Bus

PMC-2020578

Issue 2

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,

AND FOR ITS CUSTOMERS’ INTERNAL USE

RM7035C/RM7065C

64-Bit MIPS RISC Microprocessors with Integrated L2 Cache

• Compiler Suites

•

Momentum Computer

PACKAGING

• Fully Static 0.13µ CMOS design with

dynamic power down logic.

• RM7035C is available in a 128-pin

ExposedPad™ 20 x 20 mm package,

pin-compatible with the RM5231A 128-

pin ExposedPad™ product.

•

GNU

•

Evaluation platform: Ocelot C.

Features RM7000C.

MIPS Technologies

Green Hills Software

Red Hat

• Logic Analyzers and Emulation

•

Tektronix

Corelis

Crescent Heart Software

• Evaluation Boards and Companion

Chips

• RM7065 package options:

•

ITE (RM7035C only):

•

256-pin TBGA package,

27 x 27 mm, pin compatible with the

RM7065A TBGA product.

•

System controller: IT8172G

Evaluation board: IT8172 PDK-

BSP

APPLICATIONS

• Voice Gateways

•

216-pin ExposedPad™ package,

24 x 24 mm, pin compatible with the

RM5261A ExposedPad™ product.

•

Marvell Semiconductor (RM7065C

only):

• Multi-Service Access Platforms

• DSLAMs/Access Concentrators

• Remote Access Switches

• Web Switches

• Layer 3 Switches

• Backbone Switches/Routers

• RAIDs

• Set Top Boxes

• Networked Printers

• Cellular Base Stations

•

System controllers: MV-64340,

GT-64240, GT-96122

• Lead-free (Pb-free) options available.

•

Evaluation platforms: EV-64340,

EV-64240. Both Marvell evalua-

tion boards feature the RM7000C,

which features the same CPU

core as the RM7065C. The

RM7065C does not provide L3

cache functionality.

DEVELOPMENT TOOLS

• Operating Systems:

•

Linux by MontaVista and Red Hat

VxWorks by Wind River Systems

Nucleus by Accelerated Technology

Neutrino by QNX Software Systems

TYPICAL APPLICATIONS

RM7035C

RM7065C

32-Bit

64-Bit

100 MHz

200 MHz

ITE

32-Bit

100 MHz

64-Bit

183 MHz

Marvell

IT-8172G

ASIC

DDR

SDRAM

MV-64340

SDRAM

PCI Bus

32-bit @ 33 MHz

PCI-(X) Bus

2x32/64-bit @ 66 MHz

32-bit

2x64-bit

Data

Buffer

32-bit

64-bit

32-bit

8-bit

Boot-Flash

PCI-to-PCI

Bridge

PCI-to-PCI

Bridge

GbE MAC

Flash

Disk

Flash

Disk

Watchdog,

I²C & Control

Registers

Watchdog,

I²C & Control

Registers

Dual UART

Head Office:

PMC-Sierra, Inc.

8555 Baxter Place

Burnaby, B.C. V5A 4V7

Canada

Tel: 1.604.415.6000

Fax: 1.604.415.6200

To order documentation,

send email to:

document@pmc-sierra.com

or contact the head office,

Attn: Document Coordinator

All product documentation is available

on our web site at:

http://www.pmc-sierra.com

For corporate information,

send email to:

PMC-2020578 (P2)

rights reserved. February 2003.

For a complete list of PMC-Sierra’s

trademarks and registered trademarks,

visit: http://www.pmc-sierra.com/legal/.

ExposedPad is a trademark of Amkor

Technology, Inc. All other trademarks are

the properaty of the respective owners.

info@pmc-sierra.com

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

RM7035C [PMC]

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