P502-52SC [PLL]
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz); 低相位噪声分频器2 VCXO （ 10MHz至20MHz的）
| 型号： | P502-52SC |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz) |
| 文件： | 总5页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL502-52
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
FEATURES
PIN CONFIGURATION
•
Integrated voltage-controlled crystal oscillator
circuitry (VCXO) (pull range 380ppm minimum).
VCXO tuning range: 0V - VDDV.
Uses inexpensive fundamental-mode parallel
resonant crystals (from 20 to 40MHz).
Integrated divider by 2: output range of 10MHz
to 20MHz.
XOUT
N/C
XIN
1
2
3
4
8
7
6
5
•
•
OE^
VDD
CLK
VCON
GND
•
•
•
2.5V or 3.3V supply voltage.
Selectable High Drive (30mA) or Standard Drive
(10mA) output.
Note: ^ denotes internal pull up
•
Available in 8-Pin TSSOP or SOIC.
OUTPUT RANGE
DESCRIPTION
FREQUENCY
RANGE
OUTPUT
BUFFER
DIVIDER
The PLL502-52 is a monolithic low jitter, high per-
formance CMOS VCXO IC Die. It allows the control
of the output frequency with an input voltage
(VCON), using a low cost crystal.
10 - 20MHz
CMOS
÷ 2
This makes the PLL502-52 ideal for a wide range of
applications requiring a VCXO output in the 10MHz
to 20MHz range, using a fundamental crystal ranging
from 20 to 40 MHz.
BLOCK DIAGRAM
X IN
X TA L
C LK
O S C
X O U T
V A R IC A P
V C O N
O E
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/17/04 Page 1
PLL502-52
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
PIN DESCRIPTIONS
Name
Number
Type
Description
XOUT
N/C
1
2
3
4
5
6
I
-
Crystal output. See Crystal Specifications on page 4.
Not connected.
Voltage Control input.
Ground.
VCON
GND
CLK
I
P
O
P
Output clock.
Power supply.
VDD
Output enable input. Disables (tri-state) output when low. Internal pull-up
enables output by default if pin is not connected to low.
Crystal input. See Crystal Specifications on page 4.
OE
7
8
I
I
XIN
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
-0.5
-0.5
-65
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. DC Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current, Dynamic, with
Loaded Outputs
FXIN = 20 - 52MHz
Output load of 10pF
IDD
10
mA
Operating Voltage
VDD
IOH
IOL
2.25
30
3.63
V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
mA
mA
mA
mA
mA
V
Output drive current
(High Drive)
30
IOH
IOL
10
Output drive current
(Standard Drive)
10
Short Circuit Current
VCXO Control Voltage
±50
VCON
0
VDD
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/17/04 Page 2
PLL502-52
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
3. AC Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input Crystal Frequency
20
52
MHz
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
2.4
ns
%
0.3V ~ 3.0V with 15 pF load
Measured @ 50% VDD
1.2
50
Output Clock Duty Cycle
45
55
4. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
TVCXOSTB
From power valid
10
ms
FXIN = 20 - 40MHz;
XTAL C0/C1 < 250
0V ≤ VCON ≤ 3.3V
VCXO Tuning Range
500
ppm
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
ppm
ppm/V
%
VCON=1.65V ±1.65V
±200
150
80
10
VCON input impedance
VCON modulation BW
kΩ
25
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
5. Jitter Specifications
PARAMETERS
Period jitter RMS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
20MHz
20MHz
2.5
20
1
ps
ps
ps
Period jitter peak-to-peak
Integrated jitter RMS
Integrated 12 kHz to 20 MHz at 20MHz
6. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz
-120
@10kHz
-140
@100kHz
UNITS
Phase Noise relative
to carrier
20MHz
-65
-90
-147
dBc/Hz
Note: Phase Noise at VCON = 0V – to be measured
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/17/04 Page 3
PLL502-52
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
7. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
FXIN
Parallel Fundamental Mode
20
40
MHz
Crystal Loading Rating
Crystal Pullability
CL (xtal)
C0/C1 (xtal)
RE
At Vcon = 1.65V
AT cut
9.5
pF
-
250
30
Recommended ESR
AT cut
Ω
Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nomi-
nal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC
TSSOP
Symbol
Min.
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
Min.
-
Max.
1.20
0.15
0.30
0.20
3.10
4.50
6.60
0.75
E
H
A
A1
B
C
D
E
H
L
e
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
0.05
0.19
0.09
2.90
4.30
6.20
0.45
D
A
A1
C
0.65 BSC
1.27 BSC
L
B
e
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/17/04 Page 4
PLL502-52
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL502-52 (H) X C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
Optional High Drive
PACKAGE TYPE
O=TSSOP , S=SOIC
Order Number
Marking
Package Option
PLL502-52OC-R
PLL502-52OC
PLL502-52HOC-R
PLL502-52HOC
P502-52OC
P502-52OC
P502-52HOC
P502-52HOC
TSSOP - Tape and Reel
TSSOP – Tube
TSSOP - Tape and Reel
TSSOP - Tube
PLL502-52SC-R
PLL502-52SC
PLL502-52HSC-R
PLL502-52HSC
P502-52SC
P502-52SC
P502-52HSC
P502-52HSC
SOIC - Tape and Reel
SOIC - Tube
SOIC - Tape and Reel
SOIC - Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/14/00 Page 5
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