P5020NSE1VNB [FREESCALE]
QorIQ P5020/P5010 Processors; 的QorIQ P5020 / P5010处理器
| 型号： | P5020NSE1VNB |
| 厂家： | 
Freescale |
| 描述： | QorIQ P5020/P5010 Processors |
| 文件： | 总2页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QorIQ Communications Platforms
QorIQ
P5020/P5010 Processors
Overview
The QorIQ P5 family delivers scalable 64-bit processing with single-, dual- and
quad-core devices. With frequencies scaling up to 2.0 GHz, a tightly coupled cache
hierarchy for low latency and integrated hardware acceleration, the P5020 (dual-core)
and P5010 (single-core) devices are ideally suited for compute intensive, power-
conscious control plane applications.
QorIQ P5020/P5010 Processors
Target Markets and Applications
The P5020 is designed for high-
performance, power-constrained control
plane applications and provides an
ideal combination of core performance,
integrated accelerators and advanced I/O
required for the following compute-intensive
applications:
*Only Available on P5020
*Only Available on P5020
1024 KB
Frontside CoreNet
Platform Cache
64-bit
DDR2/3
Memory Controller
Power Architecture®
512 KB
Backside
L2 Cache
e5500 Core
1024 KB
Frontside CoreNet
Platform Cache
64-bit
DDR2/3
Memory Controller
32 KB
D-Cache
32 KB
I-Cache
Security Fuse Processor
Security Monitor
2x USB 2.0
eSDHC
CoreNet Coherency Fabric
Peripheral Access
Management Unit
PAMU
PAMU
PAMU
PAMU
Frame Manager
Real-Time Debug
Serial
RapidIO®
Mgr.
RapidIO
Message
Unit
eLBC
Queue
Mgr.
Security
4.0
Watchpoint
Cross
Trigger
2x DMA
Parse, Classify,
Distribute
SD/MMC
• Enterprise equipment: Router, switch,
services
SATA SATA
2.0
2x DUART
2x I2C
2.0
Perf. CoreNet
Monitor Trace
Pattern
Match
Engine
2.0
1GE 1GE
RAID
5/6
Engine
PCIe/
Buffer
Mgr.
PCIe
SRIO
SRIO
PCIe
10 GE
1GE
PCIe
SPI, GPIO
Aurora
1GE 1GE
• Data center: Server appliance, SAN
storage controller, iSCSI controller,
FCoE bridging
18-Lane 5 GHz SerDes
Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)
Accelerators and Memory Control Networking Elements
Basic Peripherals and Interconnect
• Aerospace and defense
• Industrial computing: Single-board
computers, test/measurement, robotics
P5 Family Comparison Chart
P5020/P5010
P5040/P5021
CPU cores
Threads
Max core frequency 1.6 to 2.0 GHz
2x 64-bit e5500, 1x (P5010)
2/1 (single thread per core)
4x 64-bit e5500, 2x (P5021)
4/2 (single thread per core)
1.8 to 2.4 GHz
L2
512 KB per core
512 KB per core
L3/Platform
DDR I/F
2 MB (P5020)/1 MB (P5010)
2x 64-bit DDR3 (up to 1333 MT/s)
1x 64-bit DDR3 (P5010)
4x PCIe v2.0
5x 1 GbE, 1x 10 GbE
2x SRIO v2.1
2 MB (both P5040 and P5021)
2x 64-bit DDR3 (up to 1600 MT/s)
PCI Express®
GbE, 10 GbE
SRIO
3x PCIe v2.0 (incl. 1 x 8)
10x 1 GbE, 2x 10 GbE
N/A
(supports Type 9 and 11 messaging)
18 lanes
1295-pin 37.5 x 37.5 mm FC-PBGA
SerDes lanes
Package
20 lanes
1295-pin 37.5 x 37.5 mm FC-PBGA
• Up to 64 GB of addressable memory space
e5500 Core
The P5020 is based on the 64-bit e5500 Power
Architecture® core. The e5500 core uses a
seven-stage pipeline for low latency response to
unpredictable code execution paths, boosting its
single-threaded performance. Key features:
• Hybrid 32-bit mode to support legacy software
and seamless transition to 64-bit architecture
Virtualization
The P5020 includes support for hardware-
assisted virtualization. The e5500 core offers
an extra core privilege level (hypervisor).
Virtualization software for the P5 family includes
kernel-based virtual machine (KVM), Linux®
containers, Freescale hypervisor and commercial
virtualization software from Green Hills® Software
and Enea®.
• Supports up to 2.0 GHz core frequencies
• Tightly-coupled low latency cache hierarchy:
32 KB I/D (L1), 512 KB L2 per core
• Up to 2 MB of shared platform cache (L3)
• 3.0 DMIPS/MHz per core
DPAA Hardware Accelerators
P5020/P5010 Features List
Frame manager (FMAN)
12 Gb/s classify, parse
and distribute
Two (P5020) or one (P5010)
single threaded e5500 cores
built on Power Architecture®
technology
•
•
•
Up to 2.0 GHz with 64-bit ISA support (Power Architecture V2.06 compliant)
Three levels of instruction: User, supervisor, hypervisor
Hybrid 32-bit mode to support legacy software and transition to 64-bit
architecture
Buffer manager (BMAN)
Queue manager (QMAN)
Security (SEC)
64 buffer pools
Up to 224 queues
17 Gb/s: 3 DES, AES
10 Gb/s aggregate
CoreNet platform cache (CPC)
Hierarchical interconnect fabric
•
•
2.0 MB configured as dual 1 MB blocks (1 MB only for P5010)
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet endpoints
Pattern matching engine
(PME)
•
QMAN fabric supporting packet-level queue management and quality of
service scheduling
RapidIO® manager
Supports type 9 and
type 11 messaging
Two 64-bit DDR3/3L SDRAM
memory controllers with ECC
and interleaving support
•
•
Up to 1333 MT/s
Memory pre-fetch engine
RAID5/6 engine
Calculates parity for
network attached
storage and direct
attached storage
applications
DPAA incorporating acceleration
for the following functions
•
•
•
•
•
Packet parsing, classification and distribution (FMAN)
QMAN for scheduling, packet sequencing and congestion management
Hardware BMAN for buffer allocation and de-allocation
Cryptography acceleration (SEC 4.2) at up to 40 Gb/s
Data Path Acceleration Architecture
(DPAA)
RegEx pattern matching acceleration (PME 2.1) at up to 10 Gb/s
SerDes
•
•
18 lanes at up to 5 Gb/s
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA
The P5020 integrates QorIQ DPAA, an
innovative multicore infrastructure for
Ethernet interfaces
High-speed peripheral interfaces
•
•
One 10 Gb/s Ethernet MACs
5x 1 Gb/s Ethernet MACs
scheduling work to cores (physical and virtual),
hardware accelerators and network interfaces.
The FMAN, a primary element of the DPAA,
parses headers from incoming packets and
classifies and selects data buffers with optional
policing and congestion management. The
FMAN passes its work to the QMAN, which
assigns it to cores or accelerators with a multi-
level scheduling hierarchy. The P5020 also
offers accelerators for cryptography, enhanced
regular expression pattern matching and
RAID5/6 offload.
•
•
Four PCI Express 2.0 controllers
Two Serial RapidIO® controllers/ports (sRIO port) v1.3-compliant with
features of v2.1
•
Two serial ATA (SATA 2.0) controllers
Additional peripheral interfaces
•
•
•
•
•
•
Two Full-Speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface
Four I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
•
•
Dual four channel
Support for hardware
virtualization and partitioning
enforcement
Extra privileged level for hypervisor support
QorIQ trust architecture 1.1
•
Secure boot, secure debug, tamper detection, volatile key storage
System Peripherals and Networking
For networking, the FMAN supports one
10 Gb/s and 5x 1 Gb/s MAC controllers that
connect to PHYs, switches and backplanes
over RGMII, SGMII and XAUI. High-speed
system expansion is supported through four
PCI Express® v2.0 controllers that support a
variety of lane widths. Other peripherals include
SATA, SD/MMC, I2C, UART, SPI, NOR/NAND
controller, GPIO and dual 1333 MT/s DDR3/3L
controllers.
• Mentor Graphics®: Commercial-grade
Linux solution
• QNX®: Real-time OS and development tool
support
Software and Tool Support
• Enea: Real-time operating system support
and virtualization software
• Green Hills: Comprehensive portfolio of
software and hardware development tools,
trace tools, real-time operating systems
and virtualization software
• QorIQ P5020 development system
(P5020DS-PB)
For more information, please visit freescale.com/QorIQ
Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a
trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.
The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and
service marks licensed by Power.org. © 2012, 2013 Freescale Semiconductor,Inc.
Document Number: QP5020FS REV 4
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