FD5110TE-25.0M-YYY-T500 [PLETRONICS]
Processor Specific Clock Generator, 230MHz, CMOS, CDSO6, 3.20 X 5 MM, CERAMIC LCC-6;
| 型号： | FD5110TE-25.0M-YYY-T500 |
| 厂家： | 
PLETRONICS, INC. |
| 描述： | Processor Specific Clock Generator, 230MHz, CMOS, CDSO6, 3.20 X 5 MM, CERAMIC LCC-6 时钟 CD 外围集成电路 晶体 |
| 文件： | 总12页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FD5T Series
Programmable
CMOS Clock Oscillator
November 2008
• Pletronics’ FD5T Series is a quartz crystal
controlled precision square wave generator with a
programmable CMOS output
• Output frequency from 12 KHz to 230 MHZ
• Selectable low jitter or spread spectrum output.
• Device characteristics may be either factory or
field programmable
• 3.2 x 5 mm LCC Ceramic Package
• Low power
• This is a low cost, mass produced oscillator.
• Tape and Reel or cut tape packaging is
available.
• Designed for high density SMD needs
• Excellent frequency stability options
• 1.8V, 2.5 or 3.3V LVCMOS outputs
Vdd 1.8V (5)
Reference
Vddout (6)
oscillator
optional
Voltage
Optional
Vcontrol
(4)
Out
controlled
Divider #1
/1 to /1023
PLL Multiplier #1
optional Spread Spectrum
optional Bypass Mode
MUX #1
Y1
S2/SCL (1)
S1/SDA (2)
- Programming
control
- eePROM
- SDA/SCL
Registers
Ground (3)
- Sx Control
Pletronics Inc. certifies this device is in accordance with the
RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 0.09 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e4
Absolute Maximum Ratings:
Parameter
Unit
VDD
-0.5V to +2.5V
-0.5V to +4.6V
VDDOUT
Vi Input Voltage
-0.5V to VDD+ 0.5V
-0.5V to VDDOUT + 0.5V
_+ 50 mA
125oC
50oC/Watt
Vo Output Voltage
Io Continuous Output Current
Tj Maximum Junction Temperature
Thermal Resistance, Junction to Case
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2008, Pletronics Inc.
FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Description:
The FD5T series Programmable CMOS Clock Oscillator is a modular PLL-based low cost, high-
performance oscillator. The frequency range is from 12KHz to 230MHZ.
The FD5T base frequency, as noted in the device part number, is established during manufacture and is
permanently fixed. For convenience, the divider for output OUT characteristics may be pre-programmed
at the factory, or field programmed.
The FD5T has a separate output supply pin, VDDOUT, for either 1.8, 2.5 or 3.3V output logic levels. The
device supply, VDD which provides power to all the internal circuits, is nominally 1.8V.
The deep M/N PLL divider ratio allows the generation of zero-ppm clocks for applications such as WLAN,
BlueTooth, Ethernet, USB, IEEE1394, etc. from the base frequency.
The PLL supports Spread Spectrum Clocking (SSC). SSC may be programmed to be either center-
spread or down-spread. This is an important technique to reduce electro-magnetic interference (EMI).
The device supports non-volatile eePROM programming for easy customization of the device. As
shipped, the device is pre-programmed. Standard combinations are denoted by three characters in the
device part number. However, the FD5T may be reprogrammed to a different configuration.
Reprogramming may be either prior to assembly, or in-circuit via a 2-wire SDA/SCL I2C bus. In-circuit
programming is not allowed if the VCXO function is needed.
Two programmable control inputs, S1 and S2, may be used to control various aspects of FD55T operation
including selection of alternative frequency set(s), selection of SSC functionality, output tri-state and
power-down.
Reference Oscillator
The Reference Oscillator is an AT cut quartz crystal based oscillator. This oscillator is very similar to the
Pletronics SM77xxH product oscillator. This signal is the lowest jitter and can be an output or can be
divided down by the Divider #1. The user may specify any frequency between 12MHz and 32MHz for
this reference. All output frequencies are derived from (referenced to) this Reference Oscillator.
The VCXO input has a limited voltage range, the VCXO is associated with the internal 1.8V core. A
resistor in series with the Vcontrol input will permit interfacing to 3.3V analog circuits, the voltage range
that changes the frequency will still be limited but the larger voltages swings will not cause problems.
The VCXO function is only enabled (internally connected) if the part number indicates a VCXO
specification. When the VCXO function is enabled the I2C programming mode will be disabled.
PLL Multipliers
The PLL Multiplier can multiply the Reference Oscillator frequency from 1 (bypass mode) to any value
that is <=230MHz (the lowest frequency is the Reference Oscillator frequency).
The PLL Multipliers can have two setup options, 0 or 1, depending on which option is chosen and set by
the Sx control signals and the user’s definitions are stored in eePROM.
Spread Spectrum
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FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Each PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the
modulation of the output frequency by a user-set amount. The modulation can be centered on the
output frequency or down side only. Which of the 1 of 8 SS settings is being used is set by the Sx input
and the user definition. The value is a percentage of the output frequency that will be modulated.
SS Option
Down Side Modulation
No SS
Centered Modulation
No SS
0
1
2
3
4
5
6
7
-0.25%
+_0.25%
-0.50%
+_0.50%
-0.75%
+_0.75%
-1.00%
+_1.00%
-1.25%
+_1.25%
-1.50%
+_1.50%
-2.00%
+_2.00%
Divider Section
The dividers operate on the output of the PLL. The divider on the PLL can divide by 1 through 127, the
value is user defined. There is only 1 setting allowed per divider. These are not set by the Sx input
state.
The dividers add very little jitter to the output signals.
Multiplexers
MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from
PLL Multiplier #1. MUX #3 connect various divider outputs to the output buffer.
The device can make only one of the setting of connections shown in the block diagram (only one
pattern stored in eePROM).
Output Buffer
The output buffer can have 3 modes of operation:
1) Tri State
2) Active Low
3) The signal output of the Multiplexer
There can be two options stored for the Output Buffer, State 0 and State 1. The four Sx input settings
can have assigned one of the two Output Buffer states for each of Output Buffer sets.
Control Inputs
The two inputs, S1/SDA and S2/SCL can be configured in two ways.
1) Used as 2 user inputs to permit up to 4 states, Sx input setting.
2) The SDA and SCL become clock and data inputs to write to the FD5T internal setting memory.
The interface follows the I2C protocol. If the SDA and SCL are not set then the internal eePROM
sets the operation. (Not allowed if the VCXO function is specified.)
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3
FD5T Series Programmable
CMOS Clock Oscillator
November 2008
PART NUMBER:
FD5 1 45 T L E -25.0M -YYY -XX
Packaging code or blank
T250 = 250 per Tape and Reel
T500 = 500 per Tape and Reel
T1K = 1000 per Tape and Reel
Configuration Number
This is a 3 character alpha-numeric code issued by
Pletronics that defines the FD5T function (the output pin
functions, the available frequencies and the pin number
assignments). Each configuration is given a unique value.
Base Frequency (Crystal oscillator frequency) in MHZ
Optional Enhanced Operating temperature Range
Blank = Temp. range -20oC to +70oC
E = Temp. range -40oC to +85oC
Blank = VDDOUT 3.3V, 2.5V and 1.8V device
L = VDDOUT 1.8V only high output drive level device
Series Model
Frequency Stability for fixed frequency oscillator
45 = _+ 50 ppm
44 = _+ 25 ppm
20 = _+ 20 ppm
15 = _+ 15 ppm
10 = _+ 10 ppm
Frequency Pull Ability for VCXO option enabled
99 = _+ 100 ppm Absolute Pull Range (APR)
75 = +_ 25 ppm Absolute Pull Range (APR)
50 = +_ 50 ppm Absolute Pull Range (APR)
1 = 1 output 1 PLL version
Series Model
Part Marking:
PLE FD51
ZZZ
YMD
Marking Legend: PLE = Pletronics
ZZZ = configuration
All other marking is internal factory codes
X
YMD
=
Model type
Date of Manufacture
(year-month-day)
=
Codes for Date Code YMD
Code
Code
8
9
0
1
2
A
B
C
D
E
F
G
H
J
K
L
M
Year
Month
2008 2009 2010 2011 2012
JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC
Code
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
A
10
U
B
11
V
C
D
13
X
E
14
Y
F
15
Z
G
12
W
28
16
Day
Code
Day
H
J
K
L
M
21
N
P
R
T
17
18
19
20
22
23
24
25
26
27
29
30
31
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FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Electrical Specification over the specified temperature range
Item
Min
12
Max
32
Unit
MHZ
MHZ
MHZ
ppm
Condition
Base Frequency
Frequency Range OUT1
Frequency Range OUT2 - 7
0.0117
0.0945
-50
230
230
+50
+25
Base Frequency / (1 to 1023) -or- PLL1
For all supply voltages, load changes,
aging for 1 year, shock, vibration and
temperatures
Frequency Accuracy
“45"
“44"
-25
-20
+20
“20"
Recommended Operating Conditions
Device Supply Voltage VDD
Output Supply Voltage VDDOUT
Output Supply Voltage “L” VDDOUT
Low Level Input voltage
1.7
1.7
1.7
--
1.9
3.6
1.9
30
--
V
V
V
%
of VDD
High Level Input voltage
70
0
%
of VDD
Input Voltage Range, S1, S2
Input current for: S1, S2
3.6
5
V
VTH is 0.5 * VDD
VIN = VDD; VDD = 1.9V
0
µA
µA
mA
mA
mA
mA
pf
-4
0
VIN = 0.0VD; VDD = 1.9V
Output Current, VDDOUT = 3.3V
Output Current, VDDOUT = 2.5V
Output Current, VDDOUT = 1.8V
Output Current “L”, VDDOUT = 1.8V
Output Load, LVCMOS
-12
-10
-5
+12
+10
+5
+8
10
-8
--
Higher loads can be used
IOH = -0.1 mA
LVCMOS Output Parameters for VDDOUT = 3.3v
Output High, VDDOUT = 3.3V
2.9
2.4
2.2
--
--
--
V
V
I
I
OH = -8.0 mA
OH = -12.0 mA
--
V
Output Low, VDDOUT = 3.3V
0.1
0.5
0.8
0.6
55
100
90
V
IOH = +0.1 mA
--
V
I
I
OH = +8.0 mA
OH = +12.0 mA
--
V
Rise & Fall Time
--
nS
%
pS
pS
V
DDOUT = 3.3v, 20 - 80%, 10pF Load
Output Symmetry
45
--
at 50% point of VDDOUT
Peak-to-Peak Jitter(1)(2)
Cycle-to-Cycle Jitter(1)(2)
--
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5
FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Item
Min
Max
Unit
Condition
LVCMOS Output Parameters for VDDOUT = 2.5v
Output High, VDDOUT = 2.5V
Output Low, VDDOUT = 2.5V
2.2
1.7
1.6
--
--
--
V
V
IOH = -0.1 mA
I
I
OH = -6.0 mA
OH = -10.0 mA
--
V
0.1
0.5
0.7
0.6
55
100
90
V
IOH = +0.1 mA
--
V
I
I
OH = +6.0 mA
OH = +10.0 mA
--
V
Rise & Fall Time
--
nS
%
pS
pS
V
DDOUT = 2.5v, 20 - 80%, 10pF Load
Output Symmetry
45
--
at 50% point of VDDOUT
Peak-to-Peak Jitter(1)(2)
Cycle-to-Cycle Jitter(1)(2)
--
LVCMOS Output Parameters for VDDOUT = 1.8v
Output High, VDDOUT = 1.8V
1.6
1.4
1.1
--
--
--
V
V
IOH = -0.1 mA
I
I
OH = -3.0 mA
OH = -6.0 mA
--
V
Output Low, VDDOUT = 1.8V
0.1
0.3
0.6
0.9
55
V
IOH = +0.1 mA
--
V
I
I
OH = +3.0 mA
OH = +6.0 mA
--
V
Rise & Fall Time
--
nS
%
pS
pS
V
DDOUT = 1.8v, 20 - 80%, 10pF Load
Output Symmetry
45
--
at 50% point of VDDOUT
Peak-to-Peak Jitter(1)(2)
Cycle-to-Cycle Jitter(1)(2)
140
120
--
LVCMOS Output Parameters for VDDOUT = 1.8v “L” Version
Output High, VDDOUT = 1.8V
1.6
1.4
1.1
--
--
--
V
V
IOH = -0.1 mA
I
I
OH = -4.0 mA
OH = -8.0 mA
--
V
Output Low, VDDOUT = 1.8V
0.1
0.3
0.6
0.7
55
V
IOH = +0.1 mA
--
V
I
I
OH = +4.0 mA
OH = +8.0 mA
--
V
Rise & Fall Time
nS
%
pS
pS
V
DDOUT = 1.8v, 20 - 80%, 10pF Load
Output Symmetry
45
--
at 50% point of VDDOUT
Peak-to-Peak Jitter(1)(2)
Cycle-to-Cycle Jitter(1)(2)
140
120
--
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6
FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Item
Min
Max
Unit
Condition
VCXO Function
Vcontrol Input Range Usable
0.5
VDD - 0.5V
V
V
The slope is positive
Vcontrol Input Range Allowed
- Direct connect to Vcontrol
- Limit current to _+ 3mA
0.0
-1.0
VDD
4.0
The slope is positive
Recommend >=1K ohm to Vcontrol
Pull Ability specified in the P.N.
Linearity
-10
+10
%
(1) 10,000 cycles
(2) Jitter depends on the device configuration.
Data is taken under the following conditions: 1-PLL; 27MHz Crystal, (measured at Out3).
Frequency Tolerance:
For the FD5115T and the FD5110T devices, Pletronics recommends that the tight
tolerance be required on the PLL outputs only. In this case the reference frequency
output would only achieve ±25ppm tolerance. This will reduce the cost of the device.
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7
FD5T Series Programmable
CMOS Clock Oscillator
November 2008
FD51xxT
IDDOUT Current for Various Number of Outputs On
No Load
VDD=1.8V
V
DDOUT=3.3V
VDDOUT=2.5V
VDDOUT=1.8V
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
5
4.5
4
3.5
3
1 Output On
2.5
2
All outputs Off
1.5
1
0.5
0
10
30
50
70
90
110 130 150 170 190 210 230
10
30
50
70
90
110 130 150 170 190 210 230
Fout (MHz)
10 30 50 70 90 110 130 150 170 190 210 230
Fout (MHz)
Fout (MHz)
FD51xxTL VDD = VDDOUT=1.8V
No Load
FD5 Series IDD versus PLLs Used
VDD=1.8V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
30
25
20
15
10
5
1 PLL On
1 Output On
All outputs Off
All PLLs Off
0
10
30
50
70
90
110
130
150
170
190
210
230
10
30
50
70
90
110 130 150 170 190 210 230
Fout (MHz)
PLL Frequency (MHz)
Phase noise of the reference signal, Out3.
25MHz Reference Frequency
RMS jitter is 1.4pS from 10Hz to 2MHz
Example of the PLL synthesizing a frequency.
25MHz Reference Frequency
Multiply by 8 to 200MHz
Divide the 200MHz PLL output by 8
Phase noise plot of the resulting 25MHz on Out 3
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FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Load Circuit and Test Waveform
Symmetry
Vhigh
90% * Vcc
50% * Vcc
10% * Vcc
Vlow
Ground
Trise
Tfall
Reliability: Environmental Compliance
Parameter
Condition
Mechanical Shock
Vibration
MIL-STD-883 Method 2002, Condition B
MIL-STD-883 Method 2007, Condition A
MIL-STD-883 Method 2003
Solderability
Thermal Shock
MIL-STD-883 Method 1011, Condition A
ESD Rating
Model
Minimum Voltage Conditions
Human Body Model
Charged Device Model
1500
1000
MIL-STD-883 Method 3115
JESD 22-C101
Package Labeling
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Courier New
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Arial
Bar code is 39-Full ASCII
(Label will show FD55)
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FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Mechanical:
Inches
mm
A
0.197 +_0.006
5.00 +_0.15
B
C
0.125 +_0.006
0.053 max
3.20 +_0.15
1.35 max
1.27
1
2
6
5
D1 0.050
E1 0.050
1.27
F1
0.004
0.10
G1 0.039
H1 0.025
1.00
3
4
0.63
I1
0.020
0.50
1 Typical dimensions
Not to Scale
J1
0.004R
0.10R
0.20R
Contacts:
Gold 11.8 µinches 0.3 µm minimum over
Nickel 50 to 350 µinches 1.27 to 8.89 µm
K1 0.008R
Pad Functions:
Pad
Function
Note
1
S1/SDA
Serial Data Clock (optional V control - VCXO)
Serial Data
S2
S1
Input to select 1 of 4
preprogrammed functions of
the outputs (optional)
2
3
S2/SCL
Ground (GND)
Crystal reference frequency divided by 1 through 1023
PLL1 frequency divided by 1 through 1023
4
5
Out (Y3)
VDD
1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the
package pin.
6
VDDOUT
1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass
capacitor required near the package pin.
All unused inputs should be pulled high.
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10
FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Reflow Cycle (typical for lead free-processing)
260°C Maximum
10 Seconds Maximum
250
200
150
100
215°C±10°C
175°C±10°C
Approximately 50 Seconds
120 to 160 Seconds
Allowed rate of temperature change
The part may be reflowed 2Mtiamximeusmw4°iCthpoerusetcdonedgradation.
Tape and Reel: available for quantities of 250 to 1000 per reel, cut tape for < 250
Constant Dimensions Table 1
T1
Max
Tape
Size
D1
Min
S1
Min
T
Max
D0
E1
P0
P2
8mm
12mm
16mm
24mm
1.0
1.5
1.5
1.5
2.0
_+0.05
1.75
+_0.1
1.5
4.0
0.6
0.6
0.1
+0.1
-0.0
_+0.1
2.0
+_0.1
Variable Dimensions Table 2
Tape
Size
B1
Max
E2 Min
14.25
F
P1
T2
Max
W
Max
Ao, Bo &
Ko
16 mm
12.1
7.5 +_0.1
8.0 +_0.1
8.0
16.3
Note 1
Note 1: Embossed cavity to conform to EIA-481-B
Not to scale
REEL DIMENSIONS
A
B
inches
mm
7.0
177.8
2.50
63.5
10.0
254.0
13.0
330.2
3.75
95.3
inches
mm
4.00
101.6
Tape
Width
C
D
mm
13.0 +0.5 / -0.2
mm
16.4
+2.0
-0.0
16.4
+2.0
-0.0
16.4
+2.0
-0.0
16.0
Reel dimensions may vary from the above
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FD5T Series Programmable
CMOS Clock Oscillator
November 2008
IMPORTANT NOTICE
Pletronics Incorporated (PLE) reserves the right to make corrections, improvements, modifications and
other changes to this product at any time. PLE reserves the right to discontinue any product or service
without notice. Customers are responsible for obtaining the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to
PLE’s terms and conditions of sale supplied at the time of order acknowledgment.
PLE warrants performance of this product to the specifications applicable at the time of sale in accordance
with PLE’s limited warranty. Testing and other quality control techniques are used to the extent PLE
deems necessary to support this warranty. Except where mandated by specific contractual documents,
testing of all parameters of each product is not necessarily performed.
PLE assumes no liability for application assistance or customer product design. Customers are
responsible for their products and applications using PLE components. To minimize the risks associated
with the customer products and applications, customers should provide adequate design and operating
safeguards.
PLE products are not designed, intended, authorized or warranted to be suitable for use in life support
applications, devices or systems or other critical applications that may involve potential risks of death,
personal injury or severe property or environmental damage. Inclusion of PLE products in such
applications is understood to be fully at the risk of the customer. Use of PLE products in such applications
requires the written approval of an appropriate PLE officer. Questions concerning potential risk
applications should be directed to PLE.
PLE does not warrant or represent that any license, either express or implied, is granted under any PLE
patent right, copyright, artwork or other intellectual property right relating to any combination, machine or
process which PLE product or services are used. Information published by PLE regarding third-party
products or services does not constitute a license from PLE to use such products or services or a warranty
or endorsement thereof. Use of such information may require a license from a third party under the
patents or other intellectual property of the third party, or a license from PLE under the patents or other
intellectual property of PLE.
Reproduction of information in PLE data sheets or web site is permissible only if the reproduction is
without alteration and is accompanied by associated warranties, conditions, limitations and notices.
Reproduction of this information with alteration is an unfair and deceptive business practice. PLE is not
responsible or liable for such altered documents.
Resale of PLE products or services with statements different from or beyond the parameters stated by
PLE for that product or service voids all express and implied warranties for the associated PLE product or
service and is an unfair or deceptive business practice. PLE is not responsible for any such statements.
Contacting Pletronics Inc.
Pletronics Inc.
Tel: 425-776-1880
19013 36th Ave. West
Lynnwood, WA 98036-5761 USA
Fax: 425-776-2760
E-mail: ple-sales@pletronics.com
URL: www.pletronics.com
Copyright © 2008 Pletronics Inc.
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12
相关型号：
FD5110TL-32.768K-T1K
Clock Generator, 0.32768MHz, CMOS, CDSO6, 3.20 X 5 MM, CERAMIC LCC-6
PLETRONICS
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