FD5110TE-32.768K-T250 [PLETRONICS]
CMOS Clock Oscillator; CMOS时钟振荡器
| 型号： | FD5110TE-32.768K-T250 |
| 厂家： | 
PLETRONICS, INC. |
| 描述： | CMOS Clock Oscillator |
| 文件： | 总11页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FD5T Series
FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
• Pletronics’ FD51T Series is a quartz crystal
controlled precision square wave generator
• Output frequency 32.768KHz
• 3.2 x 5 mm LCC Ceramic Package
• Stability is much better than
an XY cut watch crystal
• Selectable low jitter or spread spectrum output.
• Device characteristics may be either factory or
field programmable
• Tape and Reel or cut tape packaging is available
•
• Very fast Start-up time, <10mS
• Low power
• 1.8V, 2.5 or 3.3V LVCMOS outputs
• Designed for high density SMD needs
Vdd 1.8V (5)
Reference
Vddout (6)
oscillator
optional
Voltage
Optional
Vcontrol
(4)
Out
controlled
Divider #1
/1 to /1023
PLL Multiplier #1
optional Spread Spectrum
optional Bypass Mode
MUX #1
Y1
S2/SCL (1)
S1/SDA (2)
- Programming
control
- eePROM
- SDA/SCL
Registers
Ground (3)
- Sx Control
Pletronics Inc. certifies this device is in accordance with the
RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 0.09 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e4
Absolute Maximum Ratings:
Parameter
Unit
VDD
-0.5V to +2.5V
-0.5V to +4.6V
VDDOUT
Vi Input Voltage
-0.5V to VDD+ 0.5V
-0.5V to VDDOUT + 0.5V
_+ 50 mA
125oC
50oC/Watt
Vo Output Voltage
Io Continuous Output Current
Tj Maximum Junction Temperature
Thermal Resistance, Junction to Case
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2009, Pletronics Inc.
FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Description:
The FD51xxT-32.768K is derived from the PLE FD51T series Programmable CMOS Clock Oscillator
which is a modular PLL-based low cost, high-performance oscillator. The frequency output is set to
32.768KHz. The FD51xxT-32.768K base frequency is a 24.576MHz AT cut fundamental mode crystal.
The FD5T has a separate output supply pin, VDDOUT, for either 1.8, 2.5 or 3.3V output logic levels. The
device supply, VDD which provides power to all the internal circuits, is nominally 1.8V.
The PLL is only utilized to support Spread Spectrum Clocking (SSC), in all other cases the PLL is disabled
to reduce power. SSC may be programmed to be either center-spread or down-spread. This is an
important technique to reduce electro-magnetic interference (EMI).
The device supports non-volatile eePROM programming for easy customization of the device. As
shipped, the device is pre-programmed. However, the FD51xxT-32.768K may be reprogrammed to a
different configuration. Reprogramming may be either prior to assembly, or in-circuit via a 2-wire
SDA/SCL I2C bus. In-circuit programming is not allowed if the VCXO function is needed.
Two programmable control inputs, S1 and S2, may be used to control various aspects of
FD51xxT-32.768K operation including selection of alternative frequency set(s), selection of SSC
functionality, output tri-state and power-down.
Reference Oscillator
The VCXO input has a limited voltage range, the VCXO is associated with the internal 1.8V core. A
resistor in series with the Vcontrol input will permit interfacing to 3.3V analog circuits, the voltage range
that changes the frequency will still be limited but the larger voltages swings will not cause problems.
The VCXO function is only enabled (internally connected) if the part number indicates a VCXO
specification. When the VCXO function is enabled the I2C programming mode will be disabled.
PLL Multiplier
The PLL Multiplier is enabled when tight tolerances are needed or when the spread spectrum function is
needed.
Spread Spectrum
The PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the
modulation of the output frequency by a user-set amount.
Divider Section
The dividers operate on the output of the PLL. The divider on the PLL can divide by 1 through 1023 and
is set to 750 in this case. There is only 1 setting allowed per divider. These are not set by the Sx input
state.
The dividers add very little jitter to the output signals.
Multiplexers
MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
PLL Multiplier #1.
The device can make only one of the setting of connections shown in the block diagram (only one
pattern stored in eePROM).
Control Inputs
The two inputs, S1/SDA and S2/SCL can be configured in two ways.
1) Used as 2 user inputs to permit up to 4 states, Sx input setting.
2) The SDA and SCL become clock and data inputs to write to the FD5T internal setting memory.
The interface follows the I2C protocol. If the SDA and SCL are not set then the internal eePROM
sets the operation. (Not allowed if the VCXO function is specified.)
Standard Configuration
S1
S2
Output
SS
---
PLL
Low
High
Low
High
Low
Low
High
High
Tri State
Disable
Enable
Enable
Disable
32.768KHz
32.768KHz
32.768KHz
±1% centered
±2% centered
none
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
PART NUMBER:
FD5 1 45 T L E -32.768K -YYY
Packaging code or blank
T250 = 250 per Tape and Reel
T500 = 500 per Tape and Reel
T1K = 1000 per Tape and Reel
Output Frequency - 32.768KHz
Optional Enhanced Operating temperature Range
Blank = Temp. range -20oC to +70oC
E = Temp. range -40oC to +85oC
Blank = VDDOUT 3.3V, 2.5V and 1.8V device
L = VDDOUT 1.8V only - high output drive level device
Series Model
Frequency Stability for fixed frequency oscillator
45 = _+ 50 ppm
44 = _+ 25 ppm
20 = _+ 20 ppm
15 = +_ 15 ppm1
10 = +_ 10 ppm1
Frequency Pull Ability for VCXO option enabled
99 = _+ 100 ppm Absolute Pull Range (APR)
75 = +_ 25 ppm Absolute Pull Range (APR)
50 = +_ 50 ppm Absolute Pull Range (APR)
1 = 1 output 1 PLL version
Series Model
1In these cases the PLL will be enabled and the power dissipation will be higher.
Part Marking:
PLE FD51
32.768K
YMD
Marking Legend: PLE = Pletronics
YMD Date of Manufacture (year-month-day)
All other marking is internal factory codes
=
Codes for Date Code YMD
Code
Code
8
9
0
1
2
A
B
C
D
E
F
G
H
J
K
L
M
Year
Month
2008 2009 2010 2011 2012
JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC
Code
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
A
10
U
B
11
V
C
D
13
X
E
14
Y
F
15
Z
G
12
W
28
16
Day
Code
Day
H
J
K
L
M
21
N
P
R
T
17
18
19
20
22
23
24
25
26
27
29
30
31
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Electrical Specification over the specified temperature range,
Item
Min
-50
-25
-20
-15
-10
Max
+50
+25
+20
+15
+10
Unit
Condition
ppm
For all supply voltages, load changes,
aging for 1 year, shock, vibration and
temperatures
Frequency Accuracy
“45"
“44"
“20"
“15"
“10"
Start-up Time
--
10
mS
Recommended Operating Conditions
Device Supply Voltage VDD
Output Supply Voltage VDDOUT
Output Supply Voltage “L” VDDOUT
Low Level Input voltage
1.7
1.7
1.7
--
1.9
3.6
1.9
30
--
V
V
V
%
of VDD
High Level Input voltage
70
0
%
of VDD
Input Voltage Range, S1, S2
Input current for: S1, S2
3.6
5
V
VTH is 0.5 * VDD
VIN = VDD; VDD = 1.9V
0
µA
µA
mA
mA
mA
mA
pf
-4
0
VIN = 0.0VD; VDD = 1.9V
Output Current, VDDOUT = 3.3V
Output Current, VDDOUT = 2.5V
Output Current, VDDOUT = 1.8V
Output Current “L”, VDDOUT = 1.8V
Output Load, LVCMOS
-12
-10
-5
+12
+10
+5
+8
10
-8
--
Higher loads can be used
IOH = -0.1 mA
LVCMOS Output Parameters for VDDOUT = 3.3v
Output High, VDDOUT = 3.3V
2.9
2.4
2.2
--
--
--
V
V
I
I
OH = -8.0 mA
OH = -12.0 mA
--
V
Output Low, VDDOUT = 3.3V
0.1
0.5
0.8
0.6
2.5
9
V
IOH = +0.1 mA
--
V
I
I
OH = +8.0 mA
OH = +12.0 mA
--
V
Rise & Fall Time
IDD (no PLL enabled)
IDD (PLL enabled)
IDDOUT
--
nS
mA
mA
uA
%
VDDOUT = 3.3v, 20 - 80%, 10pF Load
--
--
SS option or 15ppm or 10 ppm stability
10pF Load
--
5
Output Symmetry
Peak-to-Peak Jitter(1)
45
--
55
10
at 50% point of VDDOUT
pS
(No SS and PLL disabled)
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Item
Min
Max
Unit
Condition
LVCMOS Output Parameters for VDDOUT = 2.5v
Output High, VDDOUT = 2.5V
Output Low, VDDOUT = 2.5V
2.2
1.7
1.6
--
--
--
V
V
IOH = -0.1 mA
I
I
OH = -6.0 mA
OH = -10.0 mA
--
V
0.1
0.5
0.7
0.6
55
2.5
9
V
IOH = +0.1 mA
--
V
I
I
OH = +6.0 mA
OH = +10.0 mA
--
V
Rise & Fall Time
Output Symmetry
IDD (no PLL enabled)
IDD (PLL enabled)
IDDOUT
--
nS
%
VDDOUT = 2.5v, 20 - 80%, 10pF Load
45
--
at 50% point of VDDOUT
mA
mA
uA
pS
--
SS option or 15ppm or 10 ppm stability
10pF Load
--
4
Peak-to-Peak Jitter(1)
--
10
(No SS and PLL disabled)
LVCMOS Output Parameters for VDDOUT = 1.8v
Output High, VDDOUT = 1.8V
1.6
1.4
1.1
--
--
--
V
V
IOH = -0.1 mA
I
I
OH = -3.0 mA
OH = -6.0 mA
--
V
Output Low, VDDOUT = 1.8V
0.1
0.3
0.6
0.9
55
2.5
9
V
IOH = +0.1 mA
--
V
I
I
OH = +3.0 mA
OH = +6.0 mA
--
V
Rise & Fall Time
Output Symmetry
IDD (no PLL enabled)
IDD (PLL enabled)
IDDOUT
--
nS
%
VDDOUT = 1.8v, 20 - 80%, 10pF Load
45
--
at 50% point of VDDOUT
mA
mA
uA
pS
--
SS option or 15ppm or 10 ppm stability
10pF Load
--
2.5
10
Peak-to-Peak Jitter(1)
--
(No SS and PLL disabled)
LVCMOS Output Parameters for VDDOUT = 1.8v “L” Version
Output High, VDDOUT = 1.8V
Output Low, VDDOUT = 1.8V
Rise & Fall Time
1.6
1.4
1.1
--
--
V
V
IOH = -0.1 mA
--
I
I
OH = -4.0 mA
OH = -8.0 mA
--
V
0.1
0.3
0.6
0.7
V
IOH = +0.1 mA
--
V
I
I
OH = +4.0 mA
OH = +8.0 mA
--
V
nS
VDDOUT = 1.8v, 20 - 80%, 10pF Load
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Item
Min
45
--
Max
55
2.5
9
Unit
%
Condition
Output Symmetry
IDD (no PLL enabled)
IDD (PLL enabled)
IDDOUT
at 50% point of VDDOUT
mA
mA
uA
--
SS option or 15ppm or 10 ppm stability
10pF Load
--
3
Peak-to-Peak Jitter(1)
VCXO Function
Vcontrol Input Range Usable
--
10
pS
(No SS and PLL disabled)
0.5
VDD - 0.5V
V
V
The slope is positive
Vcontrol Input Range Allowed
- Direct connect to Vcontrol
- Limit current to _+ 3mA
0.0
-1.0
VDD
4.0
The slope is positive
Recommend >=1K ohm to Vcontrol
Pull Ability specified in the P.N.
Linearity
--
--
-10
+10
%
(1) 10,000 cycles
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Load Circuit and Test Waveform
Symmetry
Vhigh
90% * Vcc
50% * Vcc
10% * Vcc
Vlow
Ground
Trise
Tfall
Reliability: Environmental Compliance
Parameter
Condition
Mechanical Shock
Vibration
MIL-STD-883 Method 2002, Condition B
MIL-STD-883 Method 2007, Condition A
MIL-STD-883 Method 2003
Solderability
Thermal Shock
MIL-STD-883 Method 1011, Condition A
ESD Rating
Model
Minimum Voltage Conditions
Human Body Model
Charged Device Model
1500
1000
MIL-STD-883 Method 3115
JESD 22-C101
Package Labeling
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Courier New
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Arial
Bar code is 39-Full ASCII
(Label will show FD51xxT-32.768K)
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Mechanical:
Inches
mm
A
0.197 +_0.006
5.00 +_0.15
B
C
0.125 +_0.006
0.053 max
3.20 +_0.15
1.35 max
1.27
1
2
6
5
D1 0.050
E1 0.050
1.27
F1
0.004
0.10
G1 0.039
H1 0.025
1.00
3
4
0.63
I1
0.020
0.50
1 Typical dimensions
Not to Scale
J1
0.004R
0.10R
0.20R
Contacts:
Gold 11.8 µinches 0.3 µm minimum over
Nickel 50 to 350 µinches 1.27 to 8.89 µm
K1 0.008R
Pad Functions:
Pad
Function
Note
1
S1/SDA
Serial Data Clock (optional V control - VCXO)
Serial Data
S2
S1
Input to select 1 of 4
preprogrammed functions of
the outputs (optional)
2
3
S2/SCL
Ground (GND)
Crystal reference frequency divided by 1 through 1023
PLL1 frequency divided by 1 through 1023
4
5
Out (Y3)
VDD
1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the
package pin.
6
VDDOUT
1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass
capacitor required near the package pin.
All unused inputs should be pulled high.
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Reflow Cycle (typical for lead free-processing)
260°C Maximum
10 Seconds Maximum
250
200
150
100
215°C±10°C
175°C±10°C
Approximately 50 Seconds
120 to 160 Seconds
Allowed rate of temperature change
The part may be reflowed 2Mtiamximeusmw4°iCthpoerusetcdonedgradation.
Tape and Reel: available for quantities of 250 to 1000 per reel, cut tape for < 250
Constant Dimensions Table 1
T1
Max
Tape
Size
D1
Min
S1
Min
T
Max
D0
E1
P0
P2
8mm
12mm
16mm
24mm
1.0
1.5
1.5
1.5
2.0
_+0.05
1.75
+_0.1
1.5
4.0
0.6
0.6
0.1
+0.1
-0.0
_+0.1
2.0
+_0.1
Variable Dimensions Table 2
Tape
Size
B1
Max
E2 Min
14.25
F
P1
T2
Max
W
Max
Ao, Bo &
Ko
16 mm
12.1
7.5 +_0.1
8.0 +_0.1
8.0
16.3
Note 1
Note 1: Embossed cavity to conform to EIA-481-B
Not to scale
REEL DIMENSIONS
A
B
inches
mm
7.0
177.8
2.50
63.5
10.0
254.0
13.0
330.2
3.75
95.3
inches
mm
4.00
101.6
Tape
Width
C
D
mm
13.0 +0.5 / -0.2
mm
16.4
+2.0
-0.0
16.4
+2.0
-0.0
16.4
+2.0
-0.0
16.0
Reel dimensions may vary from the above
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
IMPORTANT NOTICE
Pletronics Incorporated (PLE) reserves the right to make corrections, improvements, modifications and
other changes to this product at any time. PLE reserves the right to discontinue any product or service
without notice. Customers are responsible for obtaining the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to
PLE’s terms and conditions of sale supplied at the time of order acknowledgment.
PLE warrants performance of this product to the specifications applicable at the time of sale in accordance
with PLE’s limited warranty. Testing and other quality control techniques are used to the extent PLE
deems necessary to support this warranty. Except where mandated by specific contractual documents,
testing of all parameters of each product is not necessarily performed.
PLE assumes no liability for application assistance or customer product design. Customers are
responsible for their products and applications using PLE components. To minimize the risks associated
with the customer products and applications, customers should provide adequate design and operating
safeguards.
PLE products are not designed, intended, authorized or warranted to be suitable for use in life support
applications, devices or systems or other critical applications that may involve potential risks of death,
personal injury or severe property or environmental damage. Inclusion of PLE products in such
applications is understood to be fully at the risk of the customer. Use of PLE products in such applications
requires the written approval of an appropriate PLE officer. Questions concerning potential risk
applications should be directed to PLE.
PLE does not warrant or represent that any license, either express or implied, is granted under any PLE
patent right, copyright, artwork or other intellectual property right relating to any combination, machine or
process which PLE product or services are used. Information published by PLE regarding third-party
products or services does not constitute a license from PLE to use such products or services or a warranty
or endorsement thereof. Use of such information may require a license from a third party under the
patents or other intellectual property of the third party, or a license from PLE under the patents or other
intellectual property of PLE.
Reproduction of information in PLE data sheets or web site is permissible only if the reproduction is
without alteration and is accompanied by associated warranties, conditions, limitations and notices.
Reproduction of this information with alteration is an unfair and deceptive business practice. PLE is not
responsible or liable for such altered documents.
Resale of PLE products or services with statements different from or beyond the parameters stated by
PLE for that product or service voids all express and implied warranties for the associated PLE product or
service and is an unfair or deceptive business practice. PLE is not responsible for any such statements.
Contacting Pletronics Inc.
Pletronics Inc.
Tel: 425-776-1880
19013 36th Ave. West
Lynnwood, WA 98036-5761 USA
Fax: 425-776-2760
E-mail: ple-sales@pletronics.com
URL: www.pletronics.com
Copyright © 2009 Pletronics Inc.
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相关型号：
FD5110TL-32.768K-T1K
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PLETRONICS
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