SAA2032GP [NXP]
Digital equalization for the tape drive processing of the DCC system; 数字均衡为DCC系统的磁带驱动器的处理
| 型号： | SAA2032GP |
| 厂家： | 
NXP |
| 描述： | Digital equalization for the tape drive processing of the DCC system |
| 文件： | 总28页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA2032
Digital equalization for the tape
drive processing of the DCC system
February 1995
Product specification
Supersedes data of February 1993
File under Integrated Circuits, Miscellaneous
Philips Semiconductors
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
FEATURES
• Analog-to-digital conversion, demultiplexing,
equalization and zero crossing of time multiplexed
analog read amplifier signal
• Microcontroller interface
• Search mode envelope, label and virgin detection of the
AUX channel
GENERAL DESCRIPTION
• Search mode tape speed measurement
• Simplified external biassing
Performing the Digital Equalizing function in the Digital
Compact Cassette (DCC) system, the SAA2032 is
intended for use in conjunction with the SAA2022, read
amplifier TDA1317 or TDA1318.
• Reduced power consumption
• Analog eye output
• 4 V nominal operating voltage capability.
ORDERING INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
PIN POSITION
MATERIAL
CODE
44
QFP 1
plastic
SOT205AG
SAA2032GP
Note
1. When using reflow soldering it is recommended that the Dry Packing instructions in the Quality Reference Pocketbook
are followed. The pocketbook can be ordered using the code 9398 510 34011.
February 1995
2
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
V
V
DD
DDAD
11
12
3
RDCLK
43
CLOCK
GENERATION
f24
2
RDSYNC
LABEL
37
VIRGIN
LABEL
DETECTOR
SAA2032
36
38
VIRGIN
AENV
22
23
24
25
26
27
28
29
30
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AUX
5
VIN
ADC
DEMUX
FILTER
SLICER
1
44
DIGEYE
VAL
15
31
DAC
ANEYE
32
33
34
35
LTENDEQ
LTCNT1
LTCNT0
LTCLK
LT
LTDATA
INTERFACE
8, 14
10
13, 17, 39
MEA663
V
V
V
SS
SSA
SSAD
Fig.1 Block diagram.
February 1995
3
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
PINNING
SYMBOL
DIGEYE
PIN
1
DESCRIPTION
serial data output for eye pattern
RDSYNC
RDCLK
TEST1
VIN
2
SYNC data for Read Amplifier (push-pull output)
data clock for Read Amplifier (push-pull output)
test 1; to be connected to VSS
analog time multiplexed input from Read Amplifier
lower reference voltage (+1 V) for ADC
upper reference voltage (+3.1 V) for ADC
analog ground (0 V)
3
4
5
REFN
REFP
VSSA
6
7
8
BIASA
VSSAD
VDDAD
VDD
9
bias current for ADC (sinks current from VDDAD via 33 kΩ)
supply ground (0 V) for ADC
supply voltage (+5 V) for ADC
supply voltage (+5 V)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
VSS
supply ground (0 V)
VSSA
supply ground (0 V)
ANEYE
n.c.
analog eye voltage output
not connected
VSS
supply ground (0 V)
TEST4
TEST5
TEST6
TEST7
CH0
test 4; do not connect
test 5; do not connect
test 6; do not connect
test 7; do not connect
channel 0 output for SAA2022 (DCC Drive Signal Processing) (push-pull output)
channel 1 output for SAA2022 (push-pull output)
channel 2 output for SAA2022 (push-pull output)
channel 3 output for SAA2022 (push-pull output)
channel 4 output for SAA2022 (push-pull output)
channel 5 output for SAA2022 (push-pull output)
channel 6 output for SAA2022 (push-pull output)
channel 7 output for SAA2022 (push-pull output)
AUX channel output for SAA2022 (push-pull output)
microcontroller I/O data interface (3-state push-pull output and input; CMOS levels)
microcontroller interface enabling (CMOS input levels)
microcontroller interface; mode control 1 (CMOS input levels)
microcontroller interface; mode control 0 (CMOS input levels)
microcontroller bit-clock interface (CMOS input levels)
search mode virgin detection output
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AUX
LTDATA
LTENDEQ
LTCNT1
LTCNT0
LTCLK
VIRGIN
LABEL
AENV
VSS
search mode label detection output
search mode auxiliary detection output
supply ground (0 V)
February 1995
4
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
SYMBOL
TEST8
PIN
40
41
42
43
44
DESCRIPTION
test 8 input; to be connected to VSS
test 9 input; to be connected to VSS
test 10 input; to be connected to VSS
TEST9
TEST10
f24
clock input; typical frequency 24.576 MHz (CMOS input)
synchronization output for DIGEYE
VAL
1
2
LTCNT1
33
DIGEYE
RDSYNC
32 LTENDEQ
31 LTDATA
30 AUX
3
RDCLK
TEST1
VIN
4
5
29 CH7
6
28
27 CH5
26
25 CH3
REFN
REFP
SAA2032
CH6
7
V
8
CH4
SSA
BIASA
9
V
24
23
10
11
CH2
CH1
SSAD
V
DDAD
MEA661
Fig.2 Pin configuration.
February 1995
5
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
EMA69-52
February 1995
6
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
Following A/D conversion the envelope of this signal is
filtered and sliced. This forms the Alternating Envelope
AENV output. The LABEL and VIRGIN outputs are
detected from this and the tape search speed measured.
FUNCTIONAL DESCRIPTION
Operating Modes
DEQ operating modes are programmed via the LT
interface:
OFF
NORMAL
In the OFF mode the RDSYNC and RDCLK signals are
HIGH, the EYE outputs are disabled and the channel and
auxiliary outputs (CH0 to CH7 and AUX) are 3-stated.
• A/D conversion
• Demultiplexing
• Equalization
Read Amplifier interface
• Zero crossing.
The interface between the Read Amplifier and the
SAA2032 consists of three signals:
in this mode the SAA2032 performs the equalization and
slicing of the eight data channels and the auxiliary channel.
The eight data channels have a bit-rate of 96 kbits/s while
the auxiliary channel has a bit-rate of 12 kbits/s.
1. VIN from Read Amplifier to SAA2032; time
multiplexed data.
2. RDSYNC from SAA2032 to Read Amplifier;
synchronization between Read Amplifier multiplexer
and SAA2032 demultiplexer.
The SAA2032 input is a time-multiplexed analog signal
from the Read Amplifier. The signal contains ten time slots,
of which nine are used. The Read Amplifier and the
SAA2032 synchronize with the RDCLK and RDSYNC
signals generated by the SAA2032.
3. RDCLK from SAA2032 to Read Amplifier; data clock
for Read Amplifier multiplexer.
Following A/D conversion and demultiplexing the nine
channels are equalized. The encoding of the equalizing
coefficients (12 per channel) are not fixed and must be
loaded via the LT interface before operation.
The multiplexed VIN output of the Read Amplifier changes
to another channel at the rising edge of RDCLK. RDSYNC
synchronizes the Read Amplifier VIN output: if RDSYNC is
HIGH, the rising edge of the RDCLK will select the AUX
channel.
The nine equalized output signals are up-sampled by a
factor of 10 with the resulting signals fed to the slicer. The
slicer output is applied to the SAA2022.
Figures 4 and 5 show the relationship between the
SAA2032 and the Read Amplifier.
TEST
SAA2022 interface
• A/D conversion
• Demultiplexing
• Equalization
• Zero crossing
• Eye-pattern.
The interface with the SAA2022 consists of the 9 data
output signals CH0 to CH7, AUX.
Table 1 Dependency of Read Amplifier on
operational mode.
OPERATIONAL MODE
RDSYNC
YES
RDCLK
YES
Same as normal mode. In addition the digital and analog
eye-pattern outputs are enabled. The eye-pattern output
corresponds to one of the equalized channel outputs.
Normal
Test
YES
YES
Search
Off
HIGH
HIGH
YES
SEARCH
HIGH
• A/D conversion
• Envelope detection
Label and virgin detection interface
• Tape search and speed measurement.
When the DCC player is in its search mode, the tape is
fast-wound while the head retains tape contact. The
SAA2032 can be made to operate in the search mode and
the information will be read from the auxiliary tape track.
In the search mode the analog input signal from the Read
Amplifier is not the multiplexed signal but only the auxiliary
channel signal.
February 1995
7
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
tape speed must be known. In search mode the SAA2032
assesses the speed of labelled tapes. The microcontroller
obtains this information via the LT-interface.
The following three signals are generated:
1. LABEL: label detection (HIGH if label is detected).
2. VIRGIN: virgin tape detection (HIGH if virgin tape
is detected).
The speed information is encoded in 3 variables:
3. AENV: alternating envelope (sliced envelope).
1. SVF Speed Validation Flag (HIGH if invalid).
2. SC (4..0) Speed counter.
AENV, LABEL and VIRGIN are disabled in normal or off
modes. LABEL, VIRGIN and AENV are LOW.
3. SR (1..0) Speed Range.
AENV, LABEL and VIRGIN are enabled when the
SAA2032 is in search mode.
51.2
SC
Search speed = 2SR
×
-----------
x normal speed.
If SC = 0 then search speed > 51.2.
The device detects the envelope AENV of the auxiliary
track at search speeds between 3 and 50 times normal
speed. If AENV is continuously HIGH (label detection),
LABEL will be HIGH.
With SR = 0, 1, 2 or 3 and SC = 0 to 31.
If SVF = 1 then SR and SC values are invalid.
Appendix 1 gives a table of the search mode speed
control.
When AENV is continuously LOW (virgin tape detection)
VIRGIN will be HIGH.
Microcontroller (LT) Interface
Figures 6, 7 and 8 show the relationship between AENV,
VIRGIN and LABEL.
The SAA2032 is able to exchange information with the
microcontroller via the LT-interface. The microcontroller
performs as master, the SAA2032 as slave.
Labelled tape-speed calculation
When the DCC player is in its search mode, the tape
speed increases. LABEL information is encoded
throughout its length. To examine the length of a label, the
Figure 9 gives the operation of the LT-interface.
RDCLK
VIN
CH7 AUX
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AUX
CH0 CH1
***
***
RDSYNC
MCD477
Fig.4 Signals on interface between Read Amplifier and SAA2032.
February 1995
8
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
RDCLK
VIN
t
su
VIN
stable
MCD478
tsu > 80 ns; set-up time VIN before RDCLOCK HIGH.
Typical frequency for RDCLK = 3.072 MHz.
Typical frequency for RDSYNC = 307.2 kHz.
Fig.5 Timing.
signal
from
tape
t
t
d2
d1
AENV
MCD488 - 1
td1 = td2 = between 0.5 and 1.0 auxiliary block lengths.
Fig.6 Diagram of AENV signal.
February 1995
9
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
AENV
t
t
d3
d4
LABEL
MLA635 - 2
td3 = between 4 and 12 auxiliary blocks.
td4 = between 4 and 12 auxiliary blocks.
Fig.7 AENV and LABEL signals.
AENV
t
t
d6
d5
VIRGIN
MLA634 - 2
td5 = td6 = between 4 and 12 auxiliary blocks.
Fig.8 AENV and VIRGIN signals.
February 1995
10
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
LTENDEQ
LTCNT 0/1
LTCLK
LTDATA
0
1
2
3
4
5
6
7
LSB
MSB
MCD479
Fig.9 Typical operation of the LT-interface.
LTCNT specification
Table 2 Four types of data exchange performed on the interface.
LTCNT1
LTCNT0
LT DATA EXCHANGE MODE
FROM
µC
TO
DEQ
µC
0
0
1
1
0
1
0
1
data
write
read
write
write
data
DEQ
µC
address
DEQ
DEQ
mode settings
µC
February 1995
11
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
Mode Settings Load (LTCNT = 11) (See Fig.10)
Address Information Load (LTCNT = 10) (See Fig.11)
The 8-bits transmitted under ’mode settings load’ control
both the ’operation mode’ and the ’data exchange type’.
A channel/tap combination can be selected through this
type of data exchange.
Table 3 Mode settings; ’operation mode’.
Co-efficient Data Load (LTCNT = 00) (See Fig.12)
This type of data exchange will overwrite the equalizer tap
coefficient of the current selected channel/tap
combination.
a1
0
a0
0
OPERATION MODE
normal
0
1
test
The coefficient data for tap <0000> of the auxiliary channel
should always be zero.
1
0
search
off
1
1
Data Read (LTCNT = 01) (See Fig.13)
Table 4 Mode settings; ’data exchange type’.
This type of data exchange will send information from the
LTDATA register in the SAA2032 to the microcontroller.
Data in the LTDATA register depends upon the current
data exchange type.
b1
0
b0
0
DATA EXCHANGE TYPE
write
read
read
coefficient
coefficient
envelope
data
data
data
0
1
LTDATA interpretation:
1
1
• coefficient data: two’s complement coefficient data
• tape speed data
Remark post condition: after every communication
sequence the data exchange type must be set to “read
coefficient data”.
– d7 = SVF flag
– d6 to d2 = SC4 to SC0
– d1, d0 = SR1, SR0.
Tape speed data format is shown in Fig.14.
MSB
LSB
a0
b1
b0
a1
*
*
*
*
MCD480
data
exchange
type
operation
mode
Fig.10 Mode settings load (LTCNT = 11).
February 1995
12
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
d7
d6
d5
d4
d3
d2
d1
d0
c3
c2
c1
c0
t3
t2
t1
t0
MCD482
MCD481
MSB
LSB
MSB
LSB
c3 to c0 --> channel number <0000 to 0111>
+ auxiliary channel <1000>
t3 to t0 --> tap number <0000 .. 1011>
Fig.11 Address information load (LTCNT = 10).
Fig.12 Coefficient data load (LTCNT = 00).
d7
d0
d7
d6
d5
d4
d3
d2
d1
d0
MCD483
MBC381
MSB
LSB
SVF
SC (h. . .0)
SR (1. . .0)
Fig.13 Read data (LTCNT = 01).
Fig.14 Tape speed data format.
February 1995
13
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
t
Le
LTENDEQ
t
t
t
h2
su1
h1
LTCNT0/1
LTCLK
t
t
t
t
Hc
su2
su4
Lc
t
t
h3
su3
LTDATA
bit
MCD485 - 1
1
0
tLe > 120 ns; minimum LOW time LTENDEQ before transfer.
tsu1 > 20 ns; set-up time LTCNT0/1 before LTENDEQ HIGH.
th1 > 100 ns; hold time LTCNT0/1 after LTENDEQ HIGH.
t
su2 ≥ 0 ns; set-up time LTCNT0/1 before LTCLK LOW.
th2 > 20 ns; hold time LTENDEQ after LTCLK HIGH.
tLc > 120 ns; minimum LOW time LTCLK.
tHc > 120 ns; minimum HIGH time LTCLK.
tsu4 > 200 ns; set-up time LTCLK before LTENDEQ HIGH.
tsu3 > 100 ns; set-up time LTDATA before LTCLK HIGH.
th3 > 20 ns; hold time LTDATA after LTCLK HIGH.
Fig.15 Microcontroller to SAA2032 timing.
February 1995
14
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
t
Le
LTENDEQ
t
t
t
h2
su1
h1
LTCNT0/1
LTCLK
t
t
t
t
Hc
su2
su4
Lc
t
t
t
h5
t
h6
d1
d2
LTDATA
bit
1
0
MCD486 - 1
tLe > 120 ns; minimum LOW time LTENDEQ before transfer.
tsu1 > 20 ns; set-up time LTCNT0/1 before LTENDEQ HIGH.
th1 > 100 ns; hold time LTCNT0/1 after LTENDEQ HIGH.
t
su2 ≥ 0 ns; set-up time LTCNT0/1 before LTCLK LOW.
th2 > 20 ns; hold time LTENDEQ after LTCLK HIGH.
tLc > 120 ns; minimum LOW time LTCLK.
tHc > 120 ns; minimum HIGH time LTCLK.
tsu4 > 200 ns; set-up time LTCLK before LTENDEQ HIGH.
t
d1 > 300 ns; maximum delay LTDATA after LTENDEQ HIGH.
td2 > 400 ns; maximum delay LTDATA after LTCLK HIGH.
th5 > 160 ns; hold time LTDATA after LTCLK HIGH.
th6 > 0 ns; hold time LTDA after LTENDEQ LOW.
Fig.16 SAA2032 to Microcontroller timing.
February 1995
15
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
Eye pattern output
Table 5 Eye outputs.
To test equalization performance it is possible to output the
equalized channels. For this purpose one analog and two
digital output signals are provided. Selection of the EYE
pattern output is determined by the last channel address
sent to the SAA2032.
OPERATION MODE
DIGEYE
LOW
ANEYE
Normal
Test
HIGH
ENABLED ENABLED
Search
Off
LOW
LOW
HIGH
HIGH
• DIGEYE: serial data line for 8-bits output value
• VAL: validation signal for data bits
The internal number representation in the SAA2032 is in
two's complement. The format of the selected 8-bits will be
converted to the off-set-binary format. This means that the
MSB of the two's complement number has been inverted.
This 8-bit number is shifted out via the DIGEYE output.
• ANEYE: analog eye voltage output.
The eye outputs are enabled in test mode.
Figure 17 gives the eye pattern output timing.
t
t
val
eye
VAL
RDCLK
DIGEYE
LSB
MSB
(inverted)
LSB
RDCLK
t
clk
t
t
su
h
DIGEYE
MEA662 - 1
stable
data
tval = 1/4 clock period; pulse width HIGH.
tsu > 60 ns; minimum set-up time data before clock.
th > 5 ns; minimum hold time data after clock.
tclk = 1/fclk.
f
clk = 3.072 MHz; nominal DIGEYE clock frequency.
teye = 1/feye
feye = 307.2 kHz; nominal DIGEYE clock frequency.
.
Fig.17 Timing diagram.
16
February 1995
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
UNIT
VDD
VI
+6.5
VDD + 0.5
−100
100
V
V
input voltage
note 1
−0.5
−
ISS
supply current in VSS
supply current in VDD
input current
mA
mA
mA
mA
mW
°C
°C
V
IDD
II
−
−10
−20
−
10
IO
output current
20
Ptot
Tstg
Tamb
Ves1
Ves2
total power dissipation
storage temperature
operating ambient temperature
electrostatic handling
electrostatic handling
550
−55
−40
−1500
−70
+150
+85
note 2
note 3
+1500
+70
V
Notes
1. Input voltage should not exceed 6.5 V unless otherwise specified.
2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
3. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
DC CHARACTERISTICS
VDD = 3.8 to 5.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
3.8
5.0
5.5
5.5
26
14
13
7
V
V
VDDAD
IDD
supply voltage for ADC
supply current
note 1
3.8
−
5.0
22
12
11
5
VDD = 5 V; note 2
VDD = 3.8 V; note 2
VDDAD = 5 V
mA
−
mA
mA
mA
mA
IDDAD
supply current for ADC
operating current
−
VDDAD = 3.8 V
note 3
−
IOP
1.3
1.9
3.4
Inputs f24, LTCLK, LTCNT0, LTCNT1 and LTENDEQ
VIL
VIH
II
LOW level input voltage
HIGH level input voltage
input current
0
−
−
−
−
0.3VDD
VDD
V
0.7VDD
V
VI = 0 V; Tamb = 25 °C −
VI = VDD; Tamb = 25 °C −
−10
µA
µA
10
Input REFP
Vrefp
reference voltage
reference voltage
2.7
0.7
3.1
1.0
3.4
1.4
V
V
Input REFN
Vrefn
February 1995
17
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Inputs REFP and REFN
∆Vref
reference voltage difference
between REFP and REFN
2
2.1
2.7
V
V
Input VIN
VI(p-p)
input voltage (peak-to-peak)
input current
Vrefn
−
−
Vrefp
100
II
−
µA
Digital outputs
VOL
LOW level output voltage
HIGH level output voltage
note 4
−
−
−
0.4
V
V
VOH
note 4
V
DD − 0.5
−
Output ANEYE
VO
VO
output voltage
note 4
note 4
−
−
−
VDDAD
V
V
output voltage range
1.1
−
Input/output LTDATA
VOL
VOH
IOZ
LOW level output voltage
HIGH level output voltage
IO = −3 mA
−
−
−
−
−
−
−
0.4
−
V
IO = 2 mA
V
DD − 0.5
V
leakage current with outputs VI = 0 V; Tamb = 25 °C −
in 3-state
10
µA
µA
V
VI = VDD; Tamb = 25 °C −
10
VIL
VIH
LOW level input voltage
HIGH level input voltage
−
0.3VDD
−
0.7VDD
V
Notes
1. VDDAD should never be lower than VDD − 0.2 V.
2. For load impedances in a typical application circuit.
3. Operating reference current for the specified range of Vrefp allowing for the tolerance on the internal resistor.
4. For outputs DIGEYE, RDSYNC, RDCLK, CH0 to CH7, AUX and VAL the maximum load current is 1 mA. For ANEYE
output the maximum load current is 10 µA. For VIRGIN, LABEL and AENV the maximum load current is 2 mA.
February 1995
18
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
AC CHARACTERISTICS
VDD = 3.8 to 5.5 V; Tamb = −40 to 85 °C; unless otherwise specified.
SYMBOL
VIN
Ci
All digital inputs
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
input capacitance
−
−
−
−
15
pF
Ci
input capacitance
10
pF
Clock input f24
f
clock frequency
23
10
24.576
26
MHz
ns
tp
pulse width LOW or HIGH
−
−
Inputs LTCLK, LTENDEQ, LTCNT0 and LTCNT1
tsu
set-up time to f24
hold time from f24
note 1
note 1
10
30
−
−
−
−
ns
ns
th
All outputs
Ci
CL
td
input capacitance
load capacitance
−
−
−
−
−
−
10
50
80
pF
pF
ns
propagation delay time from f24 note 1
Input/output LTDATA
Ci
CL
td
input capacitance
−
−
−
−
−
−
10
50
80
−
pF
pF
ns
ns
ns
load capacitance
−
propagation delay time from f24
set-up time to f24
−
tsu
th
note 1
note 1
10
30
hold time from f24
−
Note
1. LOW-to-HIGH transition.
February 1995
19
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
CONVERTER CHARACTERISTICS
VDD = 3.8 to 5.5 V; Tamb = −40 to 85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog-to-Digital Converter; VIN
resolution
−
−
7
−
−
−
bits
conversation data available after
2 × tcy
effective input bandwidth
6-bit resolution
at fs = 3.1 MHz
0.5
−
MHz
±0.99
differential non-linearity
−
−
LSB
V
Vrefn
Vrefp
∆Vref
reference voltage at VREFN
reference voltage at VREFP
note 1
0.7
2.7
2
1.0
3.1
2.1
1.4
3.4
2.7
V
reference voltage difference
between REFP and REFN
V
Vi
input voltage
Vrefn
21
−
−
Vrefp
V
S+THD/N
signal-to-total harmonic
distortion and noise ratio
note 2
note 3
−
dB
Ci
II
input capacitance
input current (DC)
−
−
−
−
15
pF
100
µA
Digital-to-analog converter; output ANEYE
resolution
−
−
−
6
−
bits
V
VO
VO
output voltage
note 4
note 4
−
VDDAD
output voltage range
1.1
−
V
Notes
1. Vrefp is supplied externally.
Vrefn is derived internally and set to /3Vrefp
1
.
Vrefn must be decoupled externally at pin 6 via a 100 nF capacitor.
2. Signal level (fs) −20 dB, at any DC level within the input voltage range.
3. The output impedance of the analog input signal source must be <150 Ω.
4. Load impedance ≥1 MΩ.
February 1995
20
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
APPENDIX 1
Search Mode Speed Control Interface
In search mode the SAA2032 measures the tape speed. The tape speed is encapsulated in the variables:
• SVF Speed Validation Flag; is HIGH if NOT valid
• SC Speed Counter
• SR Speed Range.
The values in Table 6 represent the speed in multiples of the nominal tape speed of 4.76 cm/s.
Table 6 Speed in multiples of nominal tape speed.
SR[1 .. 0]
SC[4 .. 0]
REMARKS
0
1
2
3
0
1
>51.20
51.20
25.60
17.07
12.80
10.24
8.53
>102.40
102.40
51.20
34.13
25.60
20.48
17.07
14.63
12.80
11.38
10.24
9.31
>204.80
204.80
102.40
68.27
51.20
40.96
34.13
29.26
25.60
22.76
20.48
18.62
17.07
15.75
14.63
13.65
12.80
12.05
>409.60
409.60
204.80
136.53
102.40
81.92
68.27
58.51
51.20
45.51
40.96
37.24
34.13
31.51
29.26
27.31
25.60
24.09
2
3
shift to higher speed range
4
5
6
7
7.31
8
6.40
9
5.69
10
11
12
13
14
15
16
17
5.12
4.65
4.27
8.53
normal working area
3.94
7.88
3.66
7.31
3.41
6.83
3.20
6.40
3.01
6.02
February 1995
21
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
SR[1 .. 0]
SC[4 .. 0]
REMARKS
0
1
2
3
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2.84
2.69
2.56
2.44
2.33
2.23
2.13
2.05
1.97
1.90
1.83
1.77
1.71
1.65
5.69
5.39
5.12
4.88
4.65
4.45
4.27
4.10
3.94
3.79
3.66
3.53
4.41
3.30
11.38
10.78
10.24
9.75
9.31
8.90
8.53
8.19
7.88
7.59
7.31
7.06
6.83
6.61
22.76
21.56
20.48
19.50
18.62
17.81
17.07
16.38
15.75
15.17
14.63
14.12
13.65
13.21
shift to lower speed range
February 1995
22
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
PACKAGE OUTLINE
seating plane
S
S
0.15
19.2
18.2
44
34
B
2.4
1.8
(4x)
1
33
pin 1 index
1.0
14.1 19.2
13.9 18.2
23
11
0.50
0.35
22
12
2.4
1.8
(4x)
X
1.0
0.50
0.35
0.15 M
A
14.1
13.9
A
1.2
0.9
2.3
2.1
2.60
2.15
0.25
0.05
0.25
0.14
2.0
1.2
o
0 to 7
detail X
MBC659 - 1
Dimensions in mm.
Fig.18 44-lead quad flat-pack; plastic (SOT205AG).
February 1995
23
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
Several techniques exist for reflowing; for example,
SOLDERING
Quad flat-packs
BY WAVE
thermal conduction by heated belt, infrared, and vapour-
phase reflow. Dwell times vary between 50 and 300 s
according to method. Typical reflow temperatures range
from 215 to 250 °C.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two waves (dual-wave), in which, in a turbulent wave
with high upward pressure is followed by a smooth laminar
wave. Using a mildly-activated flux eliminates the need for
removal of corrosive residues in most applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
February 1995
24
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
Limiting values
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress rating only and operation of
the device at these or at any other conditions above those given in the Characteristics sections of the specification is
not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.
February 1995
25
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
NOTES
February 1995
26
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
NOTES
February 1995
27
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SCD28
© Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
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notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
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Philips Semiconductors
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