DSPC56721CAG_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: DSP56720EC

Rev. 5, 02/2009

DSP56720/DSP56721

DSP56720

Symphony^™

DSP56720/DSP56721

Multi-Core Audio Processors

144-Pin LQFP

20 mm × 20 mm

0.5 mm pitch

DSP56721

80-Pin LQFP

14 mm × 14 mm

0.65 mm pitch

144-Pin LQFP

20 mm × 20 mm

0.5 mm pitch

The Symphony DSP56720/DSP56721 Multi-Core Audio

Processors are part of the DSP5672x family of programmable

CMOS DSPs, designed using multiple DSP56300 24-bit

cores.

Communication (ICC), an External Memory Controller

(EMC) to support SDRAM, and a Sony/Philips Digital

Interface (S/PDIF).

The DSP56720/DSP56721 devices are intended for

automotive, consumer, and professional audio applications

that require high performance for audio processing. In

addition, the DSP56720 is ideally suited for applications that

need the capability to expand memory off-chip or to interface

to external parallel peripherals. Potential applications include

A/V receivers, HD-DVD and Blu-Ray players, car

The DSP56720/DSP56721 offer 200 million instructions per

second (MIPs) per core using an internal 200 MHz clock.

The DSP56720/DSP56721 are high density CMOS devices

with 3.3 V inputs and outputs.

The DSP56720 device is slightly different than the DSP56721

device—the DSP56720 includes an external memory

interface while the DSP56721 device does not. The

DSP56720 block diagram is shown in Figure 1; the

DSP56721 block diagram is shown in Figure 2.

audio/amplifiers, and professional recording equipment.

The DSP56720/DSP56721 devices excel at audio processing

for automotive and consumer audio applications requiring

high MIPs. Higher MIPs and memory requirements are driven

by the new high-definition audio standards (Dolby Digital+,

Dolby TrueHD, DTS-HD, for example) and the desire to

process multiple audio streams.

In addition, DSP56720/DSP56721 devices are optimal for the

professional audio market requiring audio recording, signal

processing, and digital audio synthesis.

The DSP56720/DSP56721 processors provide a wealth of

on-chip audio processing functions, via a plug and play

software architecture system that supports audio decoding

algorithms, various equalization algorithms, compression,

signal generator, tone control, fade/balance, level

meter/spectrum analyzer, among others. The

DSP56720/DSP56721 devices also support various matrix

decoders and sound field processing algorithms.

With two DSP56300 cores, a single DSP56720 or DSP56721

device can replace dual-DSP designs, saving costs while

meeting high MIPs requirements. Legacy peripherals from the

previous DSP5636x/7x families are included, as well as a

variety of new modules. Included among the new modules are

an Asynchronous Sample Rate Converter (ASRC), Inter-Core

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

Table of Contents

1

2

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.12 Programming the SHI I²C Serial Clock . . . . . . 26

2.13 Enhanced Serial Audio Interface (ESAI) Timing27

2.14 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.15 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.16 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.17 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . 35

2.18 Host Data Interface (HDI24) Timing. . . . . . . . . 35

2.19 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.20 EMC Timing (DSP56720 Only) . . . . . . . . . . . . 43

Functional Description and Application Information . . . . . . . 47

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.1 80-Pin Package Outline Drawing. . . . . . . . . . . . . . . . . 49

5.2 144-Pin Package Outline Drawing. . . . . . . . . . . . . . . . 51

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package . .5

1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package . . .6

1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package . .7

1.4 Pin Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.1

2.2

2.3

2.5

2.6

2.7

2.8

2.9

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .8

Thermal Characteristics. . . . . . . . . . . . . . . . . . . .9

Power Requirements . . . . . . . . . . . . . . . . . . . . .10

DC Electrical Characteristics . . . . . . . . . . . . . . .12

AC Electrical Characteristics . . . . . . . . . . . . . . .13

Internal Clocks. . . . . . . . . . . . . . . . . . . . . . . . . .13

External Clock Operation. . . . . . . . . . . . . . . . . .13

Reset, Stop, Mode Select, and Interrupt Timing15

3

4

5

2.10 Serial Host Interface (SHI) SPI Protocol Timing 18

6

7

2.11 Serial Host Interface (SHI) I²C Protocol Timing.24

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

2

Freescale Semiconductor

EXTAL/XTAL

DSP

Core-0

DSP

Core-1

CGM

ASRC

On-Chip

Memory

On-Chip

Memory

Arbiter 9

Arbiter 8

Shared Bus 0

P

X

Y

P

X

Y

Shared Bus 1

Arbiters 0–7

PCU

DMA

OnCE

DMA

/ AGU

/ ALU

/ AGU

/ ALU

Shared Memory 8 Kbytes

Blocks 0–7 (64 Kbytes total)

MODA0, MODB0,

MODC0, MODD0

MODA1, MODB1,

MODC1, MODD1

2 JTAGs

JTAG

Figure 1. DSP56720 Block Diagram

HDI24

EXTAL/XTAL

DSP

Core-0

DSP

Core-1

CGM

ASRC

On-Chip

Memory

On-Chip

Memory

Arbiter 8

Shared Bus 0

Shared Bus 1

P

X

Y

P

X

Y

Arbiters 0–7

PCU

DMA

OnCE

DMA

/ AGU

/ ALU

/ AGU

/ ALU

Shared Memory 8 Kbytes

Blocks 0–7 (64 Kbytes total)

MODA0, MODB0,

MODC0, MODD0

MODA1, MODB1,

MODC1, MODD1

2 JTAGs

JTAG

Figure 2. DSP56721 Block Diagram

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

3

1

Pin Assignments

DSP56720 devices are available in one package type; DSP56721 devices are available in two package types. For the pin

assignments of a specific device in a specific package, refer to Section 1.1, “Pinout for DSP56720 144-Pin Plastic LQFP

Package,” through Section 1.3, “Pinout for DSP56721 144-Pin Plastic LQFP Package.”

Table 1. Pin Assignments by Package

Device

Package

See

DSP56720

DSP56721

144-pin plastic LQFP

80-pin plastic LQFP

144-pin plastic LQFP

Figure 3 on page 5

Figure 4 on page 6

Figure 5 on page 7

For more detailed information about signals, refer to the Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors

Reference Manuall (DSP56720RM).

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

4

Freescale Semiconductor

1.1

Pinout for DSP56720 144-Pin Plastic LQFP Package

Figure 3 shows the pinout of the DSP56720 144-pin plastic LQFP package.

CORE_VDD

CORE_GND

LALE

1

2

108

107

106

105

104

103

102

101

100

99

IO_GND

IO_VDD

WDT

PINIT/NMI

TDO

3

LCS0

4

5

LCS1

LCS2

6

TDI

LCS3

7

TCK

LCS4

8

TMS

LCS5

9

SDO2_1/SDI3_1

SDO3_1/SDI2_1

SDO4_1/SDI1_1

SDO5_1/SDI0_1

CORE_GND

CORE_VDD

FSR

LCS6

LCS7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

98

IO_VDD

IO_GND

CORE_VDD

CORE_GND

LWE

97

96

95

DSP56720

144-Pin

94

93

SCKR

HCKR

LOE

LGPL5

LSDA10

LCKE

LCLK

92

91

SCKT

90

FST

89

HCKT

88

SDO2/SDI3

SDO3/SDI2

SDO4/SDI1

SDO5/SDI0

SPDIFOUT1

SPDIFIN1

IO_GND

LBCTL

87

LSDWE

LSDCAS

LGTA

86

85

84

LA0

83

LA1

82

LA2

81

IO_VDD

EXTAL

XTAL

PLLP_GND

PLLD_GND

PLLD_VDD

PLLA_GND

PLLA_VDD

PLLP_VDD

IO_VDD

IO_GND

PLLP1_GND

PLLP1_VDD

PLLD1_GND

PLLD1_VDD

PLLA1_GND

PLLA1_VDD

80

79

78

77

76

75

74

73

Figure 3. DSP56720 144-Pin Package Pinout

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Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

5

1.2

Pinout for DSP56721 80-Pin Plastic LQFP Package

Figure 4 shows the pinout of the DSP56721 80-pin plastic LQFP package.

SDO2_3/SDI3_3

SDO3_3/SDI2_3

SDO4_3/SDI1_3

SDO5_3/SDI0_3

IO_VDD

1

2

3

4

5

6

7

8

9

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

WDT

PINIT/NMI

TDO

TDI

TCK

IO_GND

TMS

CORE_VDD

CORE_GND

CORE_VDD

SDO4/SDI1

SDO5/SDI0

IO_GND

IO_VDD

EXTAL

CORE_GND

DSP56721

80-Pin

SPDIFIN1/SDO2_2/SDI3_2

SPDIFOUT1/SDO3_2/SDI2_2 10

SDO4_2/SDI1_2

SDO5_2/SDI0_2

FSR_3

11

12

13

14

15

16

17

18

19

20

SCKR_3

SCKT_3

GND

XTAL

PLLP_GND

PLLD_GND

PLLD_VDD

PLLA_GND

PLLA_VDD

PLLP_VDD

GND

Figure 4. DSP56721 80-Pin Package

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

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6

1.3

Pinout for DSP56721 144-Pin Plastic LQFP Package

Figure 5 shows the pinout of the DSP56721 144-pin plastic LQFP package.

TIO0/H15/HAD15

PG18/HDI_SEL

IO_GND

1

2

108

107

106

105

104

103

102

101

100

99

IO_GND

IO_VDD

WDT

PIINT/NMI

TDO

3

TIO0_1/H18/HAD18

CORE_VDD

CORE_GND

SDO2_3/SDI3_3

SDO3_3/SDI2_3

SDO4_3/SDI1_3

SDO5_3/SDI0_3

IO_VDD

4

5

6

TDI

7

TCK

8

TMS

9

SCKR_1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

FSR_1

98

SCKT_1

IO_GND

97

96

FST_1

CORE_VDD

CORE_GND

SDO2_2/SDI3_2

SDO3_2/SDI2_2

SDO4_2/SDI1_2

SDO5_2/SDI0_2

HCKR_3

SDO0_1

95

SDO1_1

DSP56721

144-Pin

94

IO_GND

93

IO_VDD

92

CORE_GND

CORE_VDD

SDO0

91

90

FSR_3

SCKR_3

89

SDO1

88

SDO4/SDI1

SDO5/SDI0

SPDIFOUT1/H12/HAD12

SPDIFIN1/H8/HAD8

HACK/HRRQ

HOREQ/HTRQ

IO_GND

SCKT_3

87

IO_VDD

86

IO_GND

85

H6/HAD6

84

H7/HAD7

83

SPDIFIN2/H9/HAD9

SPDIFIN3/H10/HAD10

SPDIFIN4/H11/HAD11

SPDIFOUT2/H13/HAD13

SPLOCK/H14/HAD14

GND

82

81

IO_VDD

EXTAL

XTAL

PLLP_GND

PLLD_GND

PLLD_VDD

PLLA_GND

PLLA_VDD

PLLP_VDD

80

79

78

77

GND

76

GND

75

GND

74

GND

73

Figure 5. DSP56721 144-Pin Package Pinout

1.4

Pin Multiplexing

Many pins are multiplexed. For more about pin multiplexing, refer to the Symphony™ DSP56720/DSP56721 Multi-Core Audio

Processors Reference Manual (DSP56720RM).

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

7

2

Electrical Characteristics

2.1

Maximum Ratings

Table 2 shows the maximum ratings.

CAUTION

This device contains circuitry protecting against damage due to high static voltage or

electrical fields. However, normal precautions should be taken to avoid exceeding

maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled

to an appropriate logic voltage level (for example, either GND or V ). The suggested

DD

value for a pull-up or pull-down resistor is 4.7 kΩ.

NOTE

In the calculation of timing requirements, adding a maximum value of one specification to

a minimum value of another specification does not yield a reasonable sum. A maximum

specification is calculated using a worst case variation of process parameter values in one

direction. The minimum specification is calculated using the worst case for the same

parameters in the opposite direction. Therefore, a “maximum” value for a specification will

never occur in the same device that has a “minimum” value for another specification;

adding a maximum to a minimum represents a condition that can never exist.

Table 2. Maximum Ratings

1

1, 2

Rating

Symbol

Value

Unit

Supply Voltage

V

–0.3 to + 1.26

V

CORE_VDD,

V

PLLD_VDD

V

PLLP_VDD,

V

–0.3 to + 4.0

V

IO_VDD,

V

,

PLLA_VDD

3

Maximum CORE_VDD power supply ramp time

Input Voltage per pin excluding VDD and GND

Tr

10

GND –0.3 to 5.5 V

12

ms

V

IN

Current drain per pin excluding V and GND

I

mA

DD

(Except for pads listed below)

LSYNC_OUT

I

16

mA

°C

lsync_out

LCLK

I

16

lclk

LALE

I

ale

TDO

I

24

JTAG

Operating temperature range

T

–40 to +100

J

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Table 2. Maximum Ratings (Continued)

Symbol

1

1, 2

Rating

Value

Unit

Storage temperature

T

–65 to +150

2000

°C

V

STG

ESD protected voltage (Human Body Model)

—

ESD protected voltage (Charged Device)

V

• All pins

• Corner pins

500

750

Note:

1. GND = 0 V, T = –40° C to 100° C, CL = 50 pF

J

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress

beyond the maximum rating may affect device reliability or cause permanent damage to the device.

3. If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing

erroneous operation.

2.2

Thermal Characteristics

Table 3 provides the thermal characteristics for the device.

Table 3. Thermal Characteristics

Characteristic

Board Type

Symbol

LQFP Values

Unit

1,2

Natural Convection, Junction-to-ambient thermal resistance

Single layer board

(1s)

57 for 80 QFP

49 for 144 QFP

°C/W

R

or θ

θJA

JA

Four layer board

(2s2p)

44 for 80 QFP

40 for 144 QFP

°C/W

3

Junction-to-case thermal resistance

—

10 for 80 QFP

9 for 144 QFP

θJC

JC

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2, Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1).

The average chip-junction temperature (T_J) in °C can be obtained from:

T = T + (P × θ )

JMA

J

A

D

Where:

•

T_A= Ambient Temperature, °C

_JMA= Package Thermal Resistance, Junction-to-Ambient, °C/W

θ

P_D= P_INT+ P_I/O

P_INT= I_DD× V_DD, Watts – Chip Internal Power

P

_I/O= Power Dissipation on Input and Output Pins—User Determined

For most applications, P_I/O< P_INTand can be ignored. P_Dcan be calculated using the worst-case conditions of 1.1 V and

780 mA. See Table 4 for more information.

To find T_Jat 100° C, using the worst-case conditions and a four-layer board:

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

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9

P_D= 1.1 V × 625 mA

= 0.6875 W

T_J= 70 + (0.6875 × 40)

= 97.5° C

2.3

Power Requirements

To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode

as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins.

IO_VDD

External

Schottky

Diode

Core_VDD

Figure 6. Prevent High Current Conditions by Using External Schottky Diode

If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead

of Core_VDD, as shown in Figure 7.

Core_VDD

IO_VDD

Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD

For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms,

as shown in Figure 8.

There are no power down requirement for the digital 1.0 V (CORE) and 3.3 V (IO). For the analog PLL power, the digital (IO)

3.3 V must be power up before the analog 3.3 V power. Similarly, for power down the digital (IO) 3.3 V must be power down

after the analog power 3.3 V. This requirement is for avoiding possible leakage.

Tr

1.0 V

0 V

Core_VDD

Tr must be < 10 ms

Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD

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Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

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Freescale Semiconductor

2.4

Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are

described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and

discharging the capacitances of the pins and internal nodes.

Current consumption is described by the following formula:

I = C × V × f

Eqn. 1

where

C=node/pin capacitance

V=voltage swing

f=frequency of node/pin toggle

Example 1. Power Consumption Example

For a GPIO address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 150 MHz clock, toggling at

its maximum possible rate (75 MHz), the current consumption is

–12

6

I = 50x10

x3.3x75x10 = 12.375mA

Eqn. 2

The maximum internal current (I max) value reflects the typical possible switching of the internal buses on best-case

CCI

operation conditions, which is not necessarily a real application case. The typical internal current (I

average switching of the internal buses on typical operating conditions.

) value reflects the

CCItyp

For applications that require very low current consumption, do the following:

•

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board

effects (for example, to compensate for measured board current not caused by the DSP). Use the test algorithm, specific test

current measurements, and the following equation to derive the current per MIPS value.

I/MIPS = I/MHz = (I

- I

)/(F2 - F1)

Eqn. 3

typF2 typF1

where :

I

=current at F2

=current at F1

typF2

typF1

F2=high frequency (any specified operating frequency)

F1=low frequency (any specified operating frequency lower than F2)

NOTE

F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be

33 MHz. The degree of difference between F1 and F2 determines the amount of precision

with which the current rating can be determined for an application.

™

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11

2.5

DC Electrical Characteristics

Table 4 shows the DC electrical characteristics.

Table 4. DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Unit

Commercial Supply voltages:

• Core (Core_VDD)

V

0.9

1

1.1

V

DD

• PLL (PLLD_VDD, PLLD1_VDD)

Supply voltages:

V

3.14

3.3

3.46

V

DDIO

• I/O (IO_VDD)

• PLL (PLLP_VDD, PLLP1_VDD)

• PLL (PLLA_VDD, PLLA1_VDD)

Automotive Supply voltages:

V

0.95

3.14

1

1.05

3.46

V

DD

• Core (Core_VDD)

• PLL (PLLD_VDD, PLLD1_VDD)

Supply voltages:

V

3.3

DDIO

• I/O (IO_VDD)

• PLL (PLLP_VDD, PLLP1_VDD)

• PLL (PLLA_VDD, PLLA1_VDD)

Note: To avoid a high current condition and possible system damage, all 3.3 V supplies must rise before the 1.0 V supplies rise.

Input low voltage

V

I

–0.3

—

18

—

0.8

84

V

IL

Input leakage current

μA

pF

μA

V

IN

Clock pin Input Capacitance (EXTAL)

High impedance (off-state) input current (@ 3.3 V or 0 V)

Output high voltage

C

—

10

—

IN

I

–10

2.4

TSI

V

OH

I

= -12 mA

OH

LSYNC_OUT, LALE, LCLK Pins I = -16 mA, TDO Pin I

= -24 mA

OH

Output low voltage

V

—

0.4

V

OL

I

= 12 mA

OL

LSYNC_OUT, LALE, LCLK Pins I = 16 mA, TDO Pins I = 24 mA

OL

Internal pull-up resistor

R

64

57

92

90

142

157

kΩ

PU

PD

Internal pull-down resistor

1

Commercial Internal supply current (core only) at internal clock of

200 MHz

• In Normal mode

I

—

224

121

90

445

353

327

mA

CCI

• In Wait mode

I

CCW

2

• In Stop mode

I

CCS

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Freescale Semiconductor

Table 4. DC Electrical Characteristics (Continued)

Characteristics

Symbol

Min

Typ

Max

Unit

Automotive • In Normal Mode

• In Wait Mode

I

—

242

125

107

—

496

409

376

10

mA

pF

CCI

I

CCW

• In Stop mode

I

CCS

Input capacitance

Notes:

C

IN

1. The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In

order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic

intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this

benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V

= 1.0 V,

CORE_VDD

V

= 3.3 V at T = 25° C. Maximum internal supply current is measured with V

= 1.10 V, V = 3.4 V at

DD_IO

J

CORE_VDD

IO_VDD)

T = 100°C.

J

2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed

to float).

2.6

AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum of 0.8 V and a V

IL

IH

minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in

production with respect to the 50% point of the respective input signal’s transition. DSP56720/DSP56721 output levels are

measured with the production test machine V and V reference levels set at 0.4 V and 2.4 V, respectively.

OL

OH

2.7

Internal Clocks

Internal clock characteristics are listed in Table 5.

Table 5. Internal Clocks

No.

Characteristics

Symbol

Min

Typ

Max

Unit

Condition

1

2

3

4

Comparison Frequency

Input Clock Frequency

PLL VCO Frequency

Fref

Fin

2

—

8

MHz Fref = Fin/NR

Max = 200 MHz

—

Fvco

Fout

200

400

MHz Fvco = (Fin × NF)/NR

[1]

Output Clock Frequency

• with PLL enabled

• with PLL disabled

MHz

—

25

—

200

Fout= Fvco/NO

Fout = Fin

5

Duty Cycle

—

40

50

60

%

Fvco=

200 MHz–400 MHz

Notes:

Fin = External frequency, NF = Multiplication Factor, NR = Predivision Factor, NO = Output Divider

2.8

External Clock Operation

The DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip

oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in Figure 9.

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

13

Suggested component values:

Fosc = 24.576 MHz

EXTAL

XTAL

R = 1 M 10%

C (EXTAL)= 18 pF

C (XTAL) = 18 pF

R

XTAL1

Calculations are for a 5 – 30 MHz crystal with the following parameters:

C

• Shunt capacitance (C ) of 10 pF – 12 pF

0

• Series resistance 40 Ohm

• Drive level of 10 μW

Figure 9. Using the On-Chip Oscillator

If the DSP56720/DSP56721 system clock is an externally supplied square wave voltage source, it is connected to EXTAL

(Figure 10). When the external square wave source is connected to EXTAL, the XTAL pin is not used.

V

IH

Midpoint

EXTAL

ETH

ETL

V

IL

1

2

3

ETC

Note:

The midpoint is 0.5 (V + V ).

IH IL

Figure 10. External Clock Timing

Table 6 lists the clock operation.

Table 6. Clock Operation

No.

Characteristics

Symbol

Min

Max

Units

1

EXTAL input high

(40% to 60% duty cycle)

• Crystal oscillator

• Square wave input

Eth

16.67

2.5

100

inf

ns

1

2

EXTAL input low

(40% to 60% duty cycle)

• Crystal oscillator

• Square wave input

Etl

Etc

Tc

16.67

2.5

100

inf

ns

3

4

EXTAL cycle time

• With PLL disabled

• With PLL enabled

5

33.3

inf

500

Instruction cycle time

• With PLL disabled

• With PLL enabled

5.00

inf

5120

Notes:

1. Measured at 50% of the input transition.

2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time

required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock

frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time

requirements are met.

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

14

Freescale Semiconductor

2.9

Reset, Stop, Mode Select, and Interrupt Timing

Table 7 shows the reset, stop, mode select, and interrupt timing.

Table 7. Reset, Stop, Mode Select, and Interrupt Timing Parameters

No.

Characteristics

Expression

Min

Max

Unit

3

10

11

Delay from RESET assertion to all pins at reset value

—

11

ns

4

Required RESET duration

• Power on, external clock generator, PLL disabled

• Power on, external clock generator, PLL enabled

2 × T

10

—

ns

C

13

Syn reset deassert delay time

• Minimum

2 × T

10

200

10.0

12

7

—

ns

us

ns

C

• Maximum (PLL enabled)

Mode select setup time

Mode select hold time

(2 x T ) + T

C

LOCK

14

15

16

17

18

19

—

Minimum edge-triggered interrupt request assertion width

Minimum edge-triggered interrupt request deassertion width

Delay from interrupt trigger to interrupt code execution

—

4

10 × T

54

C + 4

Duration of level sensitive IRQA assertion to ensure interrupt service

1, 2, 3

(when exiting Stop)

• PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0) (128 Kbytes × T

655

125

—

μs

C)

• PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 =

1)

25 × T

ns

C

• PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = (128 Kbytes × T )+ 855

—

μs

ns

C

0)

T

LOCK

• PLL is not active during Stop and Stop delay is not enabled (OMR Bit (25 × T ) + T

200

—

C

LOCK

6 = 1)

20

21

• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

general-purpose transfer output valid caused by first interrupt

10 × T + 3.8

53.8

C

1

instruction execution

1

Interrupt Requests Rate

• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1

12 × T

8 × T

—

60.0

40.0

60.0

ns

C

• DMA

C

• IRQ, NMI (edge trigger)

• IRQ (level trigger)

8 × T

C

12 × T

C

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

15

Table 7. Reset, Stop, Mode Select, and Interrupt Timing Parameters

No.

Characteristics

Expression

Min

Max

Unit

22

DMA Requests Rate

• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1

• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1

• Timer, Timer_1

6 × T

—

30.0

35.0

10.0

15.0

ns

C

7 × T

C

2 × T

C

• IRQ, NMI (edge trigger)

3 × T

C

Notes:

1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply

to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using

fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined

by the OMR Bit 6 settings.

For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL

to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 μs.

3. Periodically sampled and not 100% tested.

4. RESET duration is measured during the time in which RESET is asserted, V is valid, and the EXTAL input is active and

DD

valid. When V is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

DD

device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should

minimize this state to the shortest possible duration.

Figure 11 shows the reset timing diagram.

V

IH

RESET

All Pins

11

13

10

Reset Value

Figure 11. Reset Timing Diagram

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

16

Figure 12 shows the external fast interrupt timing diagram.

a) First Interrupt Instruction Execution

19

18

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

b) General Purpose I/O

General

Purpose

I/O

20

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

Figure 12. External Fast Interrupt Timing Diagram

Figure 13 shows the negative edge-triggered external interrupt timing diagram.

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

16

IRQA, IRQB,

IRQC, IRQD,

NMI,

17

NMI_1

Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered)

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

17

Figure 14 shows the MODE select set up and hold timing diagram.

V

RESET

IH

14

15

V

IH

IL

MODA, MODB,

MODC, MODD,

PINIT

V

IRQA, IRQB,

IRQC,IRQD, NMI

IL

Figure 14. MODE Select Set Up and Hold Timing Diagram

2.10 Serial Host Interface (SHI) SPI Protocol Timing

Table 8 shows the SHI SPI protocol timing parameters and Figure 15 through Figure 18 show the timing diagrams.

Table 8. Serial Host Interface SPI Protocol Timing Parameters

1,3,4

No.

Characteristics

Mode

Filter Mode

Expression

Min

Max

Unit

23 Minimum serial clock cycle = t

(min)

Master

Bypassed

Very Narrow

Narrow

10 × T + 9

59.0

—

0

ns

SPICC

C

10 × T + 9

C

10 × T + 133

183.0

373.0

59.2

C

Wide

10 × T + 333

C

Slave

Bypassed

Very Narrow

Narrow

2.0 × T + 19.6

C

2.0 × T + 19.6

59.2

C

2.0 × T + 86.6

193.2

C

Wide

2.0 × T + 186.6 393.2

C

XX Tolerable Spike width on data or clock in

—

Bypassed

Very Narrow

Narrow

—

10

50

100

—

Wide

—

24 Serial clock high period

Master

Bypassed

29.5

0.5 × (t

)

SPICC

Very Narrow

Narrow

0.5 × (t

29.5

91.5

186.5

29.6

96.6

—

ns

Wide

Slave

Bypassed

Very Narrow

Narrow

2.0 × T + 19.6

C

2.0 × T + 19.6

C

2.0 × T + 86.6

C

Wide

2.0 × T + 186.6 196.6

C

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Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

18

Freescale Semiconductor

Table 8. Serial Host Interface SPI Protocol Timing Parameters (Continued)

1,3,4

No.

Characteristics

Mode

Filter Mode

Expression

Min

Max

Unit

25 Serial clock low period

Master

Bypassed

29.5

—

ns

0.5 × (t

)

SPICC

Very Narrow

Narrow

)

29.5

91.5

186.5

29.6

96.6

—

ns

0.5 × (t

SPICC

Wide

)

SPICC

Slave

Bypassed

Very Narrow

Narrow

2.0 × T + 19.6

C

2.0 × T + 19.6

C

2.0 × T + 86.6

C

Wide

2.0 × T + 186.6 196.6

C

26 Serial clock rise/fall time

Master

Slave

—

5

ns

27 SS assertion to first SCK edge

CPHA = 0

Slave

Bypassed

25

—

ns

2.0 × TC+15

Very Narrow

Narrow

2.0 × TC+5

15

0

—

9

ns

—

Wide

0

CPHA = 1

Slave

Bypassed

Very Narrow

Narrow

10

0

Wide

0

28 Last SCK edge to SS not asserted

Bypassed

Very Narrow

Narrow

12

22

100

200

0

Wide

29 Data input valid to SCK edge (data input

set-up time)

Master

/Slave

Bypassed

Very Narrow

Narrow

0

Wide

0

30 SCK last sampling edge to data input not

valid

Master

/Slave

Bypassed

Very Narrow

Narrow

3.0 × T

15

40

70

100.0

5

C

3.0 × T + 25

C

3.0 × T + 55

C

Wide

3.0 × T + 85

C

31 SS assertion to data out active

Slave

—

2

32 SS deassertion to data high impedance

—

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

19

Table 8. Serial Host Interface SPI Protocol Timing Parameters (Continued)

1,3,4

No.

Characteristics

Mode

Filter Mode

Expression

Min

Max

Unit

33 SCK edge to data out valid

(data out delay time)

Master

/Slave

Bypassed

Very Narrow

Narrow

3.0 × T + 30

—

45

110

135

225

—

ns

C

3.0 × T + 95

C

3.0 × T + 120

—

C

Wide

3.0 × T + 210

—

C

34 SCK edge to data out not valid

(data out hold time)

Master

/Slave

Bypassed

Very Narrow

Narrow

2.0 × T

10

15

55

105

—

C

2.0 × T + 5

—

C

2.0 × T + 45

—

C

Wide

2.0 × T + 95

—

C

35 SS assertion to data out valid

(CPHA = 0)

Slave

—

14.0

36 First SCK sampling edge to HREQ output

deassertion

Bypassed

Very Narrow

Narrow

3.0 × T + 30

45

55

—

ns

C

3.0 × T + 40

C

3.0 × T + 80

95

C

Wide

3.0 × T + 130

145

50.0

60.0

100.0

150.0

45.0

C

37 Last SCK sampling edge to HREQ output

not deasserted (CPHA = 1)

Slave

Bypassed

Very Narrow

Narrow

4.0 × T + 30

C

4.0 × T + 40

C

4.0 × T + 80

C

Wide

4.0 × T + 130

C

38 SS deassertion to HREQ output not

deasserted (CPHA = 0)

Slave

—

3.0 × T + 30

C

39 SS deassertion pulse width (CPHA = 0)

40 HREQ in assertion to first SCK edge

Slave

—

2.0 × T

10.0

—

ns

C

Master

Bypassed 0.5 × T

+ 3.0 × 49.5

SPICC

T + 5

C

Very Narrow 0.5 × T

+ 3.0 × 49.5

—

ns

SPICC

T + 5

C

Narrow

Wide

0.5 × T

+ 3.0 × 111.5

SPICC

T + 5

C

0.5 × T

+ 3.0 × 206.5

SPICC

T + 5

C

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

20

Freescale Semiconductor

Table 8. Serial Host Interface SPI Protocol Timing Parameters (Continued)

1,3,4

No.

Characteristics

Mode

Filter Mode

Expression

Min

Max

Unit

41 HREQ in deassertion to last SCK sampling

edge (HREQ in set-up time) (CPHA = 1)

Master

—

0

—

ns

42 First SCK edge to HREQ in not asserted

(HREQ in hold time)

Master

—

0

—

ns

43 HREQ assertion width

3.0 × T

15

C

Notes:

1.V

= 1.0 0.10 V; T = –40°C to 100°C; C = 50 pF.

J L

CORE_VDD

2. Pejriodically sampled, not 100% tested.

3. All times assume noise free inputs.

4. All times assume internal clock frequency of 200 MHz.

5. SHI_1 specs match those of SHI.

SS

(Input)

25

23

26

24

26

SCK (CPOL = 0)

(Output)

23

26

24

26

25

SCK (CPOL = 1)

(Output)

29

30

29

30

MISO

MSB

LSB

(Input)

Valid

34

33

MOSI

(Output)

MSB

LSB

40

42

HREQ

(Input)

43

Figure 15. SPI Master Timing Diagram (CPHA = 0)

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

21

SS

(Input)

25

24

23

24

25

26

SCK (CPOL = 0)

(Output)

26

SCK (CPOL = 1)

(Output)

29

30

MISO

(Input)

MSB

Valid

LSB

Valid

33

34

MOSI

(Output)

MSB

LSB

40

41

42

HREQ

(Input)

43

Figure 16. SPI Master Timing Diagram (CPHA = 1)

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

22

Freescale Semiconductor

SS

(Input)

25

23

28

24

26

39

SCK (CPOL = 0)

(Input)

27

24

26

25

SCK (CPOL = 1)

(Input)

35

33

34

32

31

MISO

(Output)

MSB

LSB

29

30

MSB

Valid

LSB

Valid

MOSI

(Input)

36

38

HREQ

(Output)

Figure 17. SPI Slave Timing Diagram (CPHA = 0)

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

23

SS

(Input)

25

23

28

24

26

SCK (CPOL = 0)

(Input)

27

24

26

25

SCK (CPOL = 1)

(Input)

33

34

32

31

MISO

(Output)

MSB

LSB

29

30

MSB

Valid

LSB

Valid

MOSI

(Input)

37

36

HREQ

(Output)

Figure 18. SPI Slave Timing Diagram (CPHA = 1)

2

2.11 Serial Host Interface (SHI) I C Protocol Timing

2

Table 9 lists the SHI I C protocol timing parameters and Figure 19 shows the timing diagram.

2

Table 9. SHI I C Protocol Timing Parameters

2

Standard I C

Standard

Fast-Mode

Symbol/

Expression

1,2,3,4,5

No.

Characteristics

Unit

Min

Max

Min

Max

Tolerable Spike Width on SCL or SDA

Filters Bypassed

Very Narrow Filters enabled

Narrow Filters enabled

—

0

10

50

100

—

0

10

50

100

ns

Wide Filters enabled.

44 SCL clock frequency

44 SCL clock cycle

F

T

—

10

100

—

400

—

kHz

μs

SCL

BUF

2.5

1.3

0.6

45 Bus free time

4.7

4.0

—

μs

46 Start condition set-up time

47 Start condition hold time

T

—

μs

SUSTA

T

—

μs

HD;STA

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

24

2

Table 9. SHI I C Protocol Timing Parameters (Continued)

2

Standard I C

Standard

Fast-Mode

Symbol/

Expression

1,2,3,4,5

No.

Characteristics

Unit

Min

Max

Min

Max

48 SCL low period

T

4.7

4.0

—

1.3

—

μs

ns

μs

LOW

49 SCL high period

50 SCL and SDA rise time

T

HIGH

7

T

1000

5.0

—

300

5.0

—

R

7

51 SCL and SDA fall time

52 Data set-up time

53 Data hold time

T

F

—

T

250

0.0

100

0.0

SU;DAT

—

0.9

HD;DAT

54 DSP clock frequency

• Filters bypassed

F

OSC

10.6

11.8

13.1

—

28.5

39.7

61.0

—

MHz

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

55 SCL low to data out valid

56 Stop condition setup time

T

—

3.4

—

0.9

—

μs

ns

VD;DAT

SU;STO

SU;RQI

T

4.0

0.0

0.6

0.0

57 HREQ in deassertion to last SCL edge

(HREQ in set-up time)

t

—

58 First SCL sampling edge to HREQ output

deassertion²

T

NG;RQO

• Filters bypassed

4 × T + 30

—

50.0

70.0

250.0

150.0

—

50.0

70.0

150.0

250.0

ns

C

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

⁴× T + 50

C

⁴× T + 130

C

⁴× T + 230

C

59 Last SCL edge to HREQ output not

deasserted²

T

AS;RQO

• Filters bypassed

2 × T + 30

40

50

90

—

40

50

90

—

ns

C

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

²× T + 40

C

²× T + 80

C

²× T + 130

140

C

™

Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

25

2

Table 9. SHI I C Protocol Timing Parameters (Continued)

2

Standard I C

Standard

Fast-Mode

Symbol/

Expression

1,2,3,4,5

No.

Characteristics

Unit

Min

Max

Min

Max

60 HREQ in assertion to first SCL edge

• Filters bypassed

T

AS;RQI

4327

4317

4282

4227

—

927

917

877

827

—

ns

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

61 First SCL edge to HREQ is not asserted

(HREQ in hold time.)

t

0.0

—

0.0

—

ns

HO;RQI

Notes:

1. V

= 1.00 0.10 V; T = –40°C to 100°C; C = 50 pF.

CORE_VDD

J

L

2. Pull-up resistor: R

3. Capacitive load: C

P

(min) = 1.5kΩ.

(max) = 50 pF.

b

4. All times assume noise free inputs.

5. All times assume internal clock frequency of 200 MHz.

6. SHI_1 specs match those of SHI.

7. Master Mode

2

2.12 Programming the SHI I C Serial Clock

2

The programmed serial clock cycle, T

control register).

, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock

I CCP

2

The expression for T

is

I CCP

T ²

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 — HRS) + 1)]

Eqn. 4

I CCP

C

where

— HRS is the pre scaler rate select bit. When HRS is cleared, the fixed

divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed.

— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be

selected.

2

In I C mode, the user may select a value for the programmed serial clock cycle from

6 × T (if HDM[7:0] = $02 and HRS = 1)

Eqn. 5

C

to

4096 × T (if HDM[7:0] = $FF and HRS = 0)

Eqn. 6

C

2

The programmed serial clock cycle (T

shown in Equation 4.

) should be chosen in order to achieve the desired SCL serial clock cycle (T

), as

SCL

I CCP

T ²

+ 3 × T + 45ns + T

R

(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)

Eqn. 7

I CCP

C

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Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

26

Freescale Semiconductor

44

46

49

48

SCL

SDA

50

53

51

45

52

MSB

LSB

ACK

Stop

Start

47

60

58

55

56

59

61

57

HREQ

2

Figure 19. I C Timing Diagram

2.13 Enhanced Serial Audio Interface (ESAI) Timing

Table 10 lists the ESAI timing parameters and Figure 20 through Figure 23 show the timing diagrams.

Table 10. Enhanced Serial Audio Interface Timing Parameters

1, 3, 4

5

2

No.

Characteristics

Symbol Expression

Min

Max Condition Unit

5

62 Clock cycle

t

4 × T

20.0

—

i ck

ns

SSICC

c

63 Clock high period

• For internal clock

ns

—

2 × T

10

—

c

• For external clock

64 Clock low period

• For internal clock

ns

—

2 × T

—

10

—

c

• For external clock

65 SCKR rising edge to FSR out (bl) high

66 SCKR rising edge to FSR out (bl) low

67 SCKR rising edge to FSR out (wr) high

—

17.0

7.0

x ck

i ck a

ns

—

17.0

7.0

x ck

i ck a

6

—

19.0

9.0

x ck

i ck a

6

68 SCKR rising edge to FSR out (wr) low

—

19.0

9.0

x ck

i ck a

69 SCKR rising edge to FSR out (wl) high

70 SCKR rising edge to FSR out (wl) low

—

16.0

6.0

x ck

i ck a

—

17.0

7.0

x ck

i ck a

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Table 10. Enhanced Serial Audio Interface Timing Parameters (Continued)

1, 3, 4

5

2

No.

Characteristics

Symbol Expression

Min

Max Condition Unit

71 Data in setup time before SCKR (SCK in synchronous

mode) falling edge

—

5

19.0

—

x ck

i ck

ns

72 Data in hold time after SCKR falling edge

3.5

9.0

—

x ck

i ck

6

73 FSR input (bl, wr) high before SCKR falling edge

2.0

12.0

—

x ck

i ck a

74 FSR input (wl) high before SCKR falling edge

75 FSR input hold time after SCKR falling edge

76 Flags input setup before SCKR falling edge

77 Flags input hold time after SCKR falling edge

78 SCKT rising edge to FST out (bl) high

79 SCKT rising edge to FST out (bl) low

2.0

12.0

—

x ck

i ck a

2.5

8.5

—

x ck

i ck a

0.0

19.0

—

x ck

i ck s

6.0

0.0

—

x ck

i ck s

—

14

8.0

x ck

i ck

—

20.0

10.0

x ck

i ck

6

80 SCKT rising edge to FST out (wr) high

—

20.0

10.0

x ck

i ck

6

81 SCKT rising edge to FST out (wr) low

—

22.0

12.0

x ck

i ck

82 SCKT rising edge to FST out (wl) high

83 SCKT rising edge to FST out (wl) low

—

14

9.0

x ck

i ck

—

14

10.0

x ck

i ck

84 SCKT rising edge to data out enable from high

impedance

—

22.0

17.0

x ck

i ck

85 SCKT rising edge to transmitter #0 drive enable

assertion

—

17.0

11.0

x ck

i ck

86 SCKT rising edge to data out valid

—

13

13.0

x ck

i ck

7

87 SCKT rising edge to data out high impedance

—

13

16.0

x ck

i ck

88 SCKT rising edge to transmitter #0 drive enable

—

14.0

9.0

x ck

i ck

7

deassertion

6

89 FST input (bl, wr) setup time before SCKT falling edge

90 FST input (wl) setup time before SCKT falling edge

91 FST input hold time after SCKT falling edge

2.0

18.0

—

x ck

i ck

2.0

18.0

—

x ck

i ck

4.0

5.0

—

x ck

i ck

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Table 10. Enhanced Serial Audio Interface Timing Parameters (Continued)

1, 3, 4

5

2

No.

Characteristics

Symbol Expression

Min

Max Condition Unit

92 FST input (wl) to data out enable from high impedance

93 FST input (wl) to transmitter #0 drive enable assertion

94 Flag output valid after SCKT rising edge

—

21.0

14.0

—

ns

—

14.0

9.0

x ck

i ck

95 HCKR/HCKT clock cycle

96 HCKT input rising edge to SCKT output

97 HCKR input rising edge to SCKR output

Notes:

—

2 × T

—

10

—

ns

C

18.0

—

1. V

= 1.00 0.10 V; T = –40°C to 100°C; C = 50 pF.

CORE_VDD

J L

2. i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(Asynchronous implies that SCKT and SCKR are two different clocks.)

i ck s = internal clock, synchronous mode

(Synchronous implies that SCKT and SCKR are the same clock.)

3. bl = bit length

wl = word length

wr = word length relative

4. SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.

6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one

before last bit clock of the first word in frame.

7. Periodically sampled and not 100% tested.

8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.

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62

63

64

SCKT

(Input/Output)

78

79

FST (Bit)

Out

82

83

FST (Word)

Out

86

84

86

87

First Bit

Last Bit

Data Out

93

Transmitter #0

Drive Enable

(Internal Signal)

89

85

88

91

FST (Bit) In

92

91

90

FST (Word) In

Flags Out

94

See Note

Note: In network mode, output flag transitions can occur at the start of each time slot within the

frame. In normal mode, the output flag state is asserted for the entire frame period.

Figure 20. ESAI Transmitter Timing Diagram

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62

63

64

SCKR

(Input/Output)

65

66

FSR (Bit)

Out

69

70

FSR (Word)

Out

72

71

Data In

Last Bit

First Bit

75

73

FSR (Bit)

In

74

75

77

FSR (Word)

In

76

Flags In

Figure 21. ESAI Receiver Timing Diagram

HCKT

95

SCKT

(Output)

96

Figure 22. ESAI HCKT Timing Diagram

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HCKR

95

SCKR

(Output)

97

Figure 23. ESAI HCKR Timing

2.14 Timer Timing

Table 11 lists the timer timing parameters and Figure 24 shows the timing diagram.

Table 11. Timer Timing Parameters

No.

Characteristics

Expression

Unit

Min

Max

98

99

TIO Low

TIO High

2 × T + 2.0

12.0

—

ns

C

2 × T + 2.0

C

Notes:

1. V

= 1.00 V 0.10 V; T = –40°C to 100°C, C = 50 pF

J L

CORE_VDD

2. TIMER_1 specs match those of TIMER

TIO

98

99

Figure 24. TIO Timer Event Input Restrictions Diagram

2.15 GPIO Timing

Table 12 lists the general purpose input and output (GPIO) timing and Figure 25 shows the timing diagram.

Table 12. GPIO Timing Parameters

1

No.

Characteristics

Expression

Min

Max

Unit

2

100 Fsys edge to GPIO out valid (GPIO out delay time)

—

2

7

ns

2

101 Fsys edge to GPIO out not valid (GPIO out hold time)

2

102 Fsys In valid to EXTAL edge (GPIO in set-up time)

—

2

103 Fsys edge to GPIO in not valid (GPIO in hold time)

—

0

104 Minimum GPIO pulse high width

2 × TC

10

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Table 12. GPIO Timing (Continued)Parameters (Continued)

1

No.

Characteristics

Expression

Min

Max

Unit

105 Minimum GPIO pulse low width

106 GPIO out rise time

2 × TC

—

10

—

ns

13.0

107 GPIO out fall time

—

Notes:

V

= 1.0 V 0.10 V; T = –40°C to 100°C; C = 50 pF

CORE_VDD

J

L

Fsys

100

101

GPIO

(Output)

102

103

GPIO

Input)

Valid

GPIO

(Output)

105

107

104

106

Figure 25. GPIO Timing Diagram

2.16 JTAG Timing

Table 13 lists the joint test action group (JTAG) timing parameters, and Figure 26 through Figure 28 show the timing diagrams.

Table 13. JTAG Timing Parameters

All Frequencies

No.

Characteristics

Unit

Min

Max

108

109

110

111

112

113

114

115

TCK frequency of operation (1/(T × 3); maximum 10 MHz)

—

100.0

50.0

—

10.0

—

MHz

ns

C

TCK cycle time in Crystal mode

TCK clock pulse width measured at 1.65 V

TCK rise and fall times

—

ns

3.0

—

ns

Boundary scan input data setup time

Boundary scan input data hold time

TCK low to output data valid

15.0

24.0

—

ns

—

ns

40.0

ns

TCK low to output high impedance

—

ns

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Table 13. JTAG Timing Parameters (Continued)

All Frequencies

No.

Characteristics

Unit

Min

Max

116

117

TMS, TDI data setup time

5.0

25.0

—

ns

TMS, TDI data hold time

118

TCK low to TDO data valid

TCK low to TDO high impedance

44.0

119

—

Notes:

1. V

= 1.0 V 0.10 V; T = –40°C to 100°C , C = 50 pF

J L

CORE_VDD

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

109

110

V_M

110

V_M

TCK

(Input)

VIH

VIL

111

Figure 26. Test Clock Input Timing Diagram

VIH

TCK

(Input)

VIL

112

113

Data

Inputs

Input Data Valid

114

115

114

Data

Outputs

Output Data Valid

Data

Outputs

Data

Outputs

Output Data Valid

Figure 27. Debugger Port Timing Diagram

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VIH

117

TCK

(Input)

VIL

116

Input Data Valid

TDI

TMS

(Input)

118

TDO

(Output)

Output Data Valid

119

TDO

(Output)

118

TDO

(Output)

Output Data Valid

Figure 28. Test Access Port Timing Diagram

2.17 Watchdog Timer Timing

Table 14 lists the watchdog timer timing.

Table 14. Watchdog Timer Timing Parameters

No.

Characteristics

Expression

2 × T

Min

Max

Unit

120 Delay from time-out to fall of WDT, WDT_1

121 Delay from timer clear to rise of WDT, WDT_1

10.0

—

ns

c

2 × Tc

2.18 Host Data Interface (HDI24) Timing

The HDI24 module is only on the DSP56721 device; the DSP56720 device does not have a HDI24 module. Also, only 16 bits

of the HDI24 interface are pinned out on the DSP56721 device. Table 15 lists HDI24 timing and Figure 29 through Figure 35

show the timing diagrams.

Table 15. HDI24 Timing Parameters

200 MHz

2

No.

Characteristics

Expression

Unit

Min

Max

3

317 Read data strobe assertion width

HACK read assertion width

T + 9.9

14.9

—

ns

C

3

318 Read data strobe deassertion width

HACK read deassertion width

—

9.9

—

3

4,5

319 Read data strobe deassertion width after “Last Data Register” reads

,

2 × T + 6.6

16.6

C

6

or between two consecutive CVR, ICR, or ISR reads

HACK deassertion width after “Last Data Register” reads

4,5

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Table 15. HDI24 Timing Parameters (Continued)

200 MHz

2

No.

Characteristics

Expression

Unit

Min

Max

7

320 Write data strobe assertion width

HACK write assertion width

—

13.2

16.6

—

ns

7

321 Write data strobe deassertion width

HACK write deassertion width

2 × T + 6.6

—

C

4

• after ICR, CVR and “Last Data Register” writes

• after IVR writes, or

—

16.5

—

• after TXH:TXM writes (with HBE=0), or

• after TXL:TXM writes (with HBE=1)

322 HAS assertion width

323 HAS deassertion to data strobe assertion

—

9.9

0.0

9.9

—

ns

8

7

324 Host data input setup time before write data strobe deassertion

Host data input setup time before HACK write deassertion

7

325 Host data input hold time after write data strobe deassertion

—

3.3

5.9

—

ns

Host data input hold time after HACK write deassertion

3

326 Read data strobe assertion to output data active from high impedance

HACK read assertion to output data active from high impedance

3

327 Read data strobe assertion to output data valid

29.6

9.9

—

HACK read assertion to output data valid

3

328 Read data strobe deassertion to output data high impedance

—

HACK read deassertion to output data high impedance

3

329 Output data hold time after read data strobe deassertion

3.3

Output data hold time after HACK read deassertion

3

330 HCS assertion to read data strobe deassertion

T + 9.9

14.9

9.9

—

ns

C

7

331 HCS assertion to write data strobe deassertion

—

332 HCS assertion to output data valid

19.1

—

8

333 HCS hold time after data strobe deassertion

0.0

4.7

3.3

0

334 Address (AD7—AD0) setup time before HAS deassertion (HMUX=1)

335 Address (AD7—AD0) hold time after HAS deassertion (HMUX=1)

—

336 A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W setup time before data

—

8

strobe assertion

• Read

• Write

—

4.7

3.3

—

337 A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W hold time after data

ns

8

strobe deassertion

338 Delay from read data strobe deassertion to

T

5.0

—

C

3, 4, 9

host request assertion for “Last Data Register” read

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Table 15. HDI24 Timing Parameters (Continued)

200 MHz

2

No.

Characteristics

Expression

Unit

Min

Max

339 Delay from write data strobe deassertion to

host request assertion for “Last Data Register” write

2 × T

10.0

—

ns

C

4, 7, 9

340 Delay from data strobe assertion to

—

19.1

host request deassertion for “Last Data Register” read or write (HROD =

4, 8, 9

0)

341 Delay from data strobe assertion to

—

300.0

ns

host request deassertion for “Last Data Register” read or write (HROD =

4, 8, 9, 10

1, open drain Host Request)

342 Delay from DMA HACK deassertion to HOREQ assertion

4

• For “Last Data Register” read

2 × T + 19.1

29.1

24.1

0.0

—

C

4

• For “Last Data Register” write

1 × T + 19.1

C

• For other cases

—

343 Delay from DMA HACK assertion to HOREQ deassertion

—

20.2

ns

4

• HROD = 0

344 Delay from DMA HACK assertion to HOREQ deassertion for “Last Data

Register” read or write

—

300.0

4, 10

• HROD = 1, open drain Host Request

Notes:

1. In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable.

2. V = 1.0 V 10%; T = —40°C to +100°C; C = 50 pF.

CC

J

L

3. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.

4. The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.

5. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers

without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.

6. This timing is applicable only if two consecutive reads from one of these registers are executed.

7. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

8. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the

single data strobe mode.

9. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.

10. In this calculation, the host request signal is pulled up by a 4.7 kW resistor in the open-drain mode.

11. HDI24_1 specs match those of HDI24.

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317

318

HACK

328

327

329

326

HD23–HD0

HOREQ

Figure 29. HDI24 Host Interrupt Vector Register (IVR) Read Timing Diagram

HA0–HA2

336

337

333

330

HCS

317

HRD, HDS

318

319

328

332

327

329

326

341

HD0–HD23

338

340

HOREQ,

HRRQ,

HTRQ

Figure 30. HDI24 Read Timing Diagram, Non-Multiplexed Bus

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HA0–HA2

337

333

336

331

HCS

320

HWR, HDS

321

325

324

HD0–HD23

340

339

341

HOREQ,

HRRQ,

HTRQ

Figure 31. HDI24 Write Timing Diagram, Non-Multiplexed Bus

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HA8–HA10

336

337

322

HAS

323

317

HRD, HDS

318

319

334

335

327

328

329

HAD0–HAD23

Address

Data

326

338

340

341

HOREQ,

HRRQ,

HTRQ

Figure 32. HDI24 Read Timing Diagram, Multiplexed Bus

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HA8–HA10

336

322

HAS

323

320

HWR, HDS

334

324

321

325

335

HAD0–HAD23

Address

Data

340

339

341

HOREQ,

HRRQ,

HTRQ

Figure 33. HDI24 Write Timing Diagram, Multiplexed Bus

HOREQ

(Output)

342

343

344

320

321

TXH/M/L

Write

HACK

(Input)

324

325

Data

Valid

H0–H23

(Input)

Figure 34. HDI24 Host DMA Write Timing Diagram

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HOREQ

(Output)

343

342

318

317

RXH

Read

HACK

(Input)

327

326

328

329

Data

Valid

H0-H23

(Output)

Figure 35. HDI24 Host DMA Read Timing Diagram

2.19 S/PDIF Timing

Table 16 lists the Sony/Philips Digital Interconnect Format (S/PDIF) timing parameters and Figure 36 and Figure 37 show the

timing diagrams.

Table 16. S/PDIF Timing Parameters

All Frequency

Characteristics

Symbol

Unit

Min

Max

—

0.7

ns

SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew:

asynchronous inputs, no specs apply

SPDIFOUT1,SPDIFOUT2 output (Load = 50 pf)

• Skew

• Transition Risng

—

1.5

24.2

31.3

ns

• Transition Falling

SPDIFOUT1, SPDIFOUT2 output (Load = 30 pf)

• Skew

• Transition Risng

• Transition Falling

—

1.5

13.6

18.0

SRCK period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

ns

SRCK high period

SRCK low period

STCLK period

STCLK high period

STCLK low period

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srckp

srckpl

V_M

srckph

V_M

SRCK

(Output)

Figure 36. S/PDIF SRCK Timing Diagram

stclkp

stclkpl

V_M

stclkph

V_M

STCLK

(Input)

Figure 37. S/PIDF STCLK Timing Diagram

2.20 EMC Timing (DSP56720 Only)

The DSP56721 device does not have an EMC module. For EMC timing parameters in DSP56720 devices, see Table 17, through

Table 19; for timing diagrams, see Figure 38 through Figure 40.

Table 17. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

T

10

—

3

—

160

—

ns

ps

ns

clk

T

clk_skew

LCLK skew to LSYNC_OUT

Input setup to LSYNC_IN (except LGTA/LUPWAIT)

Input hold from LSYNC_IN (except LGTA/LUPWAIT)

LGTA valid time

T

in_s

in_h

2

—

T

12

3

—

gta

LUPWAIT valid time

T

—

upwait

LALE negedge to LAD(address phase) invaild (address latch hold time)

LALE valid time

T

—

ale_h

T

3.8

4

—

ale

Output setup from LSYNC_IN (except LAD[23:0] and LALE)

Output hold from LSYNC_IN (except LAD[23:0] and LALE)

LAD[23:0] output setup from LSYNC_IN

LAD[23:0] output hold from LSYNC_IN

T

—

out_s

T

2

—

out_h

T

3.5

1.5

—

ad_s

T

—

ad_h

LSYNC_IN to output high impedance for LAD[23:0]

T

4.3

ad_z

Chapter 22, “External Memory Controller (EMC),” in the Symphony DSP56720/DSP56721 Multi-Core Audio Processors

Reference Manual explains in detail the interfacing and features of EMC. The applicable sections are as follows:

•

Section 22.4.4.3, “UPM Signal Timing”

Section 22.4.4.7, “Memory System Interface Example Using UPM”

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T_clk

LCLK

T_{clk_skew}

LSYNC_OUT

LSYNC_IN

T_{sync_in_skew}

T_{in_s}

T_{in_h}

LAD[23:0] (data)

LGTA

asynchronous input

T_gta

T_upwait

asynchronous input

LUPWAIT

T_{out_s}

T_{out_h}

Output Signals

LA[2:0]/LBCTL/LCS[7:0]

LOE/LWE

LCKE/LSDA10/LSDDQM

LSDWE/LSDRAS/LSDCAS

LGPL[5:0]

T_{ad_z}

T_{ad_s}

T_{ad_h}

LAD[23:0]

T_{ale_h}

T_ale

LALE

Figure 38. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV] = 2)

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Table 18. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

T

20

8

—

8.1

ns

clk

Input setup to LCLK (except LGTA/LUPWAIT)

Input hold from LCLK (except LGTA/LUPWAIT)

LGTA valid time

T

in_s

in_h

1

T

-1

22

4

T

gta

LUPWAIT valid time

T

upwait

LALE negedge to LAD (address phase) invalid (address latch hold time)

LALE valid time

T

ale_h

T

14

9

ale

Output setup from LCLK (except LAD[23:0] and LALE)

Output hold from LCLK (except LAD[23:0] and LALE)

LAD[23:0] output setup from LCLK

T

out_s

T

8

out_h

T

8

ad_s

LAD[23:0] output hold from LCLK

T

7

ad_h

LCLK to output high impedance for LAD[23:0]

T

—

ad_z

Notes:

1. A negative hold time means that the signal could be invalid before the LCLK rising edge.

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T_clk

LCLK

T_{in_s}

T_{in_h}

LAD[23:0] (data)

LGTA

asynchronous input

T_gta

T_upwait

asynchronous input

LUPWAIT

T_{out_s}

T_{out_h}

Output Signals

LA[2:0]/LBCTL/LCS[7:0]

LOE/LWE

LCKE/LSDA10/LSDDQM

LSDWE/LSDRAS/LSDCAS

LGPL[5:0]

T_{ad_z}

T_{ad_s}

T_{ad_h}

LAD[23:0]

T_{ale_h}

T_ale

LALE

Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4)

Table 19. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

T

40

8

—

ns

clk

Input setup to LCLK (except LGTA/LUPWAIT)

Input hold from LCLK (except LGTA/LUPWAIT)

LGTA valid time

T

in_s

in_h

1

–1

42

5

T

gta

LUPWAIT valid time

T

upwait

LALE negedge to LAD (address phase) invalid (address latch hold time)

LALE valid time

T

ale_h

T

34

19

18

ale

Output setup from LCLK (except LAD[23:0] and LALE)

Output hold from LCLK (except LAD[23:0] and LALE)

T

out_s

T

out_h

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Table 19. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) (Continued)

Parameter

LAD[23:0] output setup from LCLK

Symbol

Min

Max

Unit

T

12

17

—

ns

ad_s

LAD[23:0] output hold from LCLK

LCLK to output high impedance for LAD[23:0]

Notes:

T

ad_h

T

17.1

ad_z

1. A negative hold time means that the signal could be invalid before the LCLK rising edge.

T_clk

LCLK

T_{in_s}

T_{in_h}

LAD[23:0] (data)

asynchronous input

T_gta

LGTA

T_upwait

asynchronous input

LUPWAIT

T_{out_s}

T_{out_h}

Output Signals

LA[2:0]/LBCTL/LCS[7:0]

LOE/LWE

LCKE/LSDA10/LSDDQM

LSDWE/LSDRAS/LSDCAS

LGPL[5:0]

T_{ad_z}

T_{ad_s}

T_{ad_h}

LAD[23:0]

T_{ale_h}

T_ale

LALE

Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8)

3

Functional Description and Application Information

See the Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors Reference Manual (DSP56720RM) for detailed

functional and applications information.

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47

4

Ordering Information

Table 20 provides ordering information for both the DSP56720 and DSP56721.

Table 20. Ordering Information

Device

Device Marking

Ambient Temp.

LQFP Package

DSP56720 Commercial DSPA56720AG

DSPB56720AG

0°C–70°C

20 mm × 20 mm

14 mm × 14 mm

20 mm × 20 mm

14 mm × 14 mm

DSPC56720AG

0°C–70°C

DSP56720 Automotive

DSPA56720CAG

DSPB56720CAG

DSPC56720CAG

–40°C–85°C

0°C–70°C

DSP56721 Commercial DSPA56721AG

DSPB56721AG

0°C–70°C

DSPC56721AG

0°C–70°C

DSPA56721AF

0°C–70°C

DSPB56721AF

0°C–70°C

DSPC56721AF

0°C–70°C

DSP56721 Automotive

DSPA56721CAG

DSPB56721CAG

DSPC56721CAG

DSPA56721CAF

DSPB56721CAF

DSPC56721CAF

–40°C–85°C

5

Package Information

For the outline drawings of available device packages, see Table 21 and sections 5.1–5.2.

Table 21. Package Outline Drawings

Device

Package

See

DSP56720

144-pin plastic LQFP

Figure 43 on page 51 and

Figure 44 on page 52

DSP56721

80-pin plastic LQFP

144-pin plastic LQFP

Figure 43 on page 51 and

Figure 42 on page 50

Figure 43 on page 51 and

Figure 44 on page 52

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48

5.1

80-Pin Package Outline Drawing

Figure 41 and Figure 42 show the 80-pin package outline drawings.

Figure 41. 80-Pin Package Outline Drawing (1 of 2)

™

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49

Figure 42. 80-Pin Package Outline Drawing (2 of 2)

NOTES

1

Dimensioning and tolerancing per asme Y14.5M-1994.

2

3

Controlling dimension: millimeter

Datum plane H is located at the bottom of lead and is coincident with the lead where the lead exits the plastic body at the

bottom of the parting line.

4

5

6

Datum E, F and D to be determined at datum plane H.

Dimensions to be determined at seating plane C.

Dimensions do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions include mold mismatch and

are determined at datum plane H.

7

Dimension does not include dambar protrusion. Dambar protrusion shall not cause the lead width to exceed 0.46 mm.

Minimnum space between protrusion and adjacent lead or protrusion 0.07 mm.

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5.2

144-Pin Package Outline Drawing

Figure 43 and Figure 44 show the 144-pin package drawings.

Figure 43. 144-Pin Package Outline Drawing (1 of 2)

™

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51

Figure 44. 144-Pin Package Outline Drawing (2 of 2)

NOTES

1

All dimensinos are in millimeters

2

3

4

5

Interpret dimensions and tolerances per ASME Y14.5M-1994.

Datums B, C and D to be determined at datum plane H.

The top ppackage body size may be smaller than the bottom package size by a maximum of 0.1 mm.

These dimensions do not include mold protrusions. The maximum allowable protrusion is 0.25 mm per side. These dimensions

are maximum body size dimensions including mold mismatch.

6

This dimension does not include dambar protrusion. Protrusions shall not cause the lead width to exceed 0.35 mm minimum

space between protrusion and an adjacent lead shall be 0.07 mm.

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7

These dimensions are determined at the seating plane, datum A.

6

Product Documentation

This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these

types are available at: http://www.freescale.com. Documentation is available from a local Freescale Semiconductor, Inc.

distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet

(the source for the latest information).

The following documents are required for a complete description of the device and are necessary to design properly with the

parts:

DSP56300 Family Manual (document number DSP56300FM). Detailed description of the 56300-family architecture and the

24-bit core processor and instruction set.

Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors Reference Manual (document number DSP56720RM).

Detailed description of memory, peripherals, and interfaces.

DSP56720 Product Brief (DSP56720PB). Brief description of the DSP56720 device.

DSP56721 Product Brief (DSP56721PB). Brief description of the DSP56721 device.

7

Revision History

Table 22 summarizes revisions to this document.

Table 22. Revision History

Revision

Date

Description

5

02/2009

• Updated values and added Commercial and Automotive columns in Table 4, “DC

Electrical Characteristics.”

• Updated values in the following tables: Table 7, Table 9, Table 10, Table 11, Table 12,

Table 13, Table 15, Table 17, Table 18, and Table 19.

• In Table 10, “Enhanced Serial Audio Interface Timing Parameters,” changed value for 87

to “13”.

• Added Section 2.4, “Power Consumption Considerations.”

• In Section 2.20, “EMC Timing (DSP56720 Only),” added text regarding the EMC chapter

and applicable sections.

• Added automotive information to Table 20, “Ordering Information.”

4

3

04/2008

03/2008

• Added formula for thermal characteristics on page 10.

• Added values for pull-up and pull-down resistors on page 12.

• Updated order information on page 1 to include additional parts with temperature

specification.

2

1

02/2008

12/2007

• Timing updates.

• Initial release

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53

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Document Number: DSP56720EC

Rev. 5

02/2009


型号：	DSPC56721CAG
厂家：	NXP
描述：	24-BIT, 200MHz, OTHER DSP, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144 时钟外围集成电路
文件：	总54页 (文件大小：864K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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