DSPD366DB1_技术文档

Advance Information

DSP56366/D

Rev. 1.5, 11/2003

24-Bit Audio Digital

Signal Processor

Topic

Page

Overview

Overview .....................................i

The DSP56366 supports digital audio applications requiring sound field processing,

acoustic equalization, and other digital audio algorithms. The DSP56366 uses the

high performance, single-clock-per-cycle DSP56300 core family of programmable

CMOS digital signal processors (DSPs) combined with the audio signal processing

capability of the Motorola Symphony™ DSP family, as shown in Figure 1. This

design provides a two-fold performance increase over Motorola’s popular

Symphony family of DSPs while retaining code compatibility. Significant

architectural enhancements include a barrel shifter, 24-bit addressing, instruction

cache, and direct memory access (DMA). The DSP56366 offers 120 million

instructions per second (MIPS) using an internal 120 MHz clock at 3.3 V.

Signal/Connection

Descriptions .......................1-1

Specifications ..........................2-1

Packaging ...............................3-1

Design Considerations ...........4-1

Ordering Information ...............5-1

Power Consumption

Benchmark ....................... A-1

IBIS Model ............................. B-1

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

“asserted”

Used to indicate a signal that is active when pulled low (For

example, the RESET pin is active when low.)

Means that a high true (active high) signal is high or that a low

true (active low) signal is low

“deasserted” Means that a high true (active high) signal is low or that a low

true (active low) signal is high

Examples:

Signal/

Logic State

Signal State

Voltage*

Symbol

True

False

True

Asserted

Deasserted

Asserted

V_IL/ V_OL

V_IH/ V_OH

V_IL/ V_OL

False

Deasserted

Note: *Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product

specifications.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

IMOTOROLA DSP56366 Advance Information

i

Overview

Features

4

8

2

16

5

1

6

MEMORY EXPANSION AREA

X

Y

PROGRA

M RAM

/INSTR.

CACHE

3K x 24

DAX

(SPDIF

Tx.)

TRIPLE

TIMER

HOST

INTER

ESAI

INTER-

FACE

SHI

INTER

MEMOR MEMOR

Y

RAM

13K X

RAM

7K X 24

ESAI_1

PERIPHERAL

EXPANSION AREA

ADDRESS

GENERATI

YAB

EXTERNAL

ADDRESS

BUS

18

XAB

PAB

DAB

ADDRESS

SIX

SWITCH

CHANNEL

24-BIT

DSP563

DRAM &

SRAM

BUS

10

CONTROL

DDB

YDB

XDB

PDB

GDB

EXTERN

AL

DATA

24

INTER

NAL

DATA

POWE

PLL

DATA ALU

->

PROGR PROGR PROGR

AM

AM AM

4

+

24X24 56 56-BIT

JTAG

OnCE

CLOCK

24 BITS BUS

EXTAL

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

PINIT/NMI

Figure 1 DSP56366 Block Diagram

1

Features

1.1

DSP56300 Modular Chassis

•

120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V.

Object Code Compatible with the 56K core.

•

Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic

support.

•

Program Control with position independent code support and instruction cache support.

Six-channel DMA controller.

ii

DSP56366 Advance Information

MOTOROLA

Overview

Features

•

PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1

to 16) and power saving clock divider (2ⁱ: i=0 to 7). Reduces clock noise.

Internal address tracing support and OnCE for Hardware/Software debugging.

JTAG port.

•

Very low-power CMOS design, fully static design with operating frequencies down to DC.

STOP and WAIT low-power standby modes.

1.2

On-chip Memory Configuration

•

7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.

13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.

40Kx24 Bit Program ROM.

3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as

Instruction Cache or for Program ROM patching.

•

2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched to Program RAM

resulting in up to 10Kx24 Bit of Program RAM.

1.3

Off-chip Memory Expansion

•

External Memory Expansion Port.

Off-chip expansion up to two 16M x 24-bit word of Data memory.

Off-chip expansion up to 16M x 24-bit word of Program memory.

Simultaneous glueless interface to SRAM and DRAM.

1.4

Peripheral Modules

•

Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I²S, Sony,

AC97, network and other programmable protocols.

•

Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I²S,

Sony, AC97, network and other programmable protocols

The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and

HCKT (high frequency clocks)

•

Serial Host Interface (SHI): SPI and I²C protocols, multi master capability, 10-word receive FIFO,

support for 8, 16 and 24-bit words.

•

Byte-wide parallel Host Interface (HDI08) with DMA support.

Triple Timer module (TEC).

Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958,

CP-340 and AES/EBU digital audio formats.

•

Pins of unused peripherals (except SHI) may be programmed as GPIO lines.

1.5

Packaging

•

144-pin plastic TQFP package.

MOTOROLA

DSP56366 Advance Information

iii

Overview

Documentation

2

Documentation

Table 1 lists the documents that provide a complete description of the DSP56366 and are required to

design properly with the part. Documentation is available from a local Motorola distributor, a Motorola

semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home

page on the Internet (the source for the latest information).

Table 1 DSP56366 Documentation

Document Name

Description

Order Number

DSP56300 Family Manual

Detailed description of the 56000-family

architecture and the 24-bit core processor

and instruction set

DSP56300FM/AD

DSP56366 User’s Manual

DSP56366 Technical Data Sheet

DSP56366 Product Brief

Detailed description of memory, peripher-

als, and interfaces

DSP56366UM/D

DSP56366/D

Electrical and timing specifications; pin

and package descriptions

Brief description of the chip

DSP56366P/D

iv

DSP56366 Advance Information

MOTOROLA

SECTION 1

SIGNAL/CONNECTION DESCRIPTIONS

1.1

SIGNAL GROUPINGS

The input and output signals of the DSP56366 are organized into functional groups, which are listed in

Table 1-1 and illustrated in Figure 1-1.

The DSP56366 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special

notice for this feature is added to the signal descriptions of those inputs.

Table 1-1 DSP56366 Functional Signal Groupings

Number of

Signals

Detailed

Description

Functional Group

20

18

3

Power (V_CC

)

Figure 1-2

Figure 1-3

Figure 1-4

Figure 1-5

Figure 1-6

Figure 1-7

Figure 1-8

Table 1-9

Ground (GND)

Clock and PLL

Address bus

Data bus

18

24

10

5

Port A¹

Bus control

Interrupt and mode control

HDI08

Port B²

16

SHI

5

Figure 1-10

Table 1-11

Port C³

Port E⁵

Port D⁴

ESAI

12

ESAI_1

6

2

Table 1-12

Table 1-13

Digital audio transmitter (DAX)

Timer

1

4

Table 1-14

Figure 1-15

JTAG/OnCE Port

Notes: 1. Port A is the external memory interface port, including the external address bus, data bus, and control

signals.

2. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.

3. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

4. Port D signals are the GPIO port signals which are multiplexed with the DAX signals.

5. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.

MOTOROLA

DSP56366 Advance Information

1-1

Signal/Connection Descriptions

Signal Groupings

OnCE ON-CHIP EMULATION/

PORT A ADDRESS BUS

JTAG PORT

TDI

DSP56366

A0-A17

VCCA (3)

TCK

TDO

GNDA (4)

TMS

PORT A DATA BUS

PARALLEL HOST PORT (HDI08)

D0-D23

VCCD (4)

HAD(7:0) [PB0-PB7]

HAS/HA0 [PB8]

Port B

GNDD (4)

HA8/HA1 [PB9]

PORT A BUS CONTROL

HA9/HA2 [PB10]

HRW/HRD [PB11]

HDS/HWR [PB12]

HCS/HA10 [PB13]

HOREQ/HTRQ [PB14]

AA0-AA2/RAS0-RAS2

CAS

RD

WR

TA

HACK/HRRQ [PB15]

VCCH

BR

GNDH

BG

BB

SERIAL AUDIO INTERFACE (ESAI)

SCKT[PC3]

VCCC (2)

GNDC (2)

FST [PC4]

Port C

HCKT [PC5]

INTERRUPT AND

MODE CONTROL

SCKR [PC0]

FSR [PC1]

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

HCKR [PC2]

SDO0[PC11] / SDO0_1[PE11]

SDO1[PC10] / SDO1_1[PE10]

SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9]

SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8]

SDO4/SDI1 [PC7]

PLL AND CLOCK

SDO5/SDI0 [PC6]

EXTAL

PINIT/NMI

PCAP

SERIAL AUDIO INTERFACE(ESAI_1)

SCKT_1[PE3]

FS T_1[PE4]

VCCP

GNDP

Port E

SCKR_1[PE0]

FSR_1[PE1]

QUIET POWER

VCCQH (3)

SDO4_1/SDI1_1[PE7]

SDO5_1/SDI0_1[PE6]

VCCS (2)

VCCQL (4)

GNDQ (4)

GNDS (2)

SPDIF TRANSMITTER (DAX)

Port D

SERIAL HOST INTERFACE (SHI)

MOSI/HA0

ADO [PD1]

ACI [PD0]

SS/HA2

MISO/SDA

TIMER 0

TIO0 [TIO0]

SCK/SCL

HREQ

Figure 1-1 Signals Identified by Functional Group

1-2

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Power

1.2

POWER

Table 1-2 Power Inputs

Description

Power

Name

V_CCP

PLL Power—V_CCPis V_CCdedicated for PLL use. The voltage should be well-regulated

and the input should be provided with an extremely low impedance path to the V_CC

power rail. There is one V_CCPinput.

V

_CCQL(4)

Quiet Core (Low) Power—V_CCQLis an isolated power for the internal processing logic.

This input must be tied externally to all other chip power inputs. The user must provide

adequate external decoupling capacitors. There are four V_CCQLinputs.

_CCQH(3)

Quiet External (High) Power—V_CCQHis a quiet power source for I/O lines. This input

must be tied externally to all other chip power inputs. The user must provide adequate

decoupling capacitors. There are three V_CCQHinputs.

V

_CCA(3)

Address Bus Power—V_CCAis an isolated power for sections of the address bus I/O

drivers. This input must be tied externally to all other chip power inputs. The user must

provide adequate external decoupling capacitors. There are three V_CCAinputs.

V_CCD(4)

Data Bus Power—V_CCDis an isolated power for sections of the data bus I/O drivers.

This input must be tied externally to all other chip power inputs. The user must provide

adequate external decoupling capacitors. There are four V_CCDinputs.

V

_CCC(2)

Bus Control Power—V_CCCis an isolated power for the bus control I/O drivers. This

input must be tied externally to all other chip power inputs. The user must provide ade-

quate external decoupling capacitors. There are two V_CCCinputs.

V_CCH

Host Power—V_CCHis an isolated power for the HDI08 I/O drivers. This input must be

tied externally to all other chip power inputs. The user must provide adequate external

decoupling capacitors. There is one V_CCHinput.

V_CCS(2)

SHI, ESAI, ESAI_1, DAX and Timer Power —V_CCSis an isolated power for the SHI,

ESAI, ESAI_1, DAX and Timer. This input must be tied externally to all other chip

power inputs. The user must provide adequate external decoupling capacitors. There

are two V_CCSinputs.

MOTOROLA

DSP56366 Advance Information

1-3

Signal/Connection Descriptions

Ground

1.3

GROUND

Table 1-3 Grounds

Description

Ground

Name

GND_P

PLL Ground—GND_Pis a ground dedicated for PLL use. The connection should be

provided with an extremely low-impedance path to ground. V_CCPshould be bypassed

to GND_Pby a 0.47 µF capacitor located as close as possible to the chip package.

There is one GND_Pconnection.

GND_Q(4)

GND_A(4)

Quiet Ground—GND_Qis an isolated ground for the internal processing logic. This con-

nection must be tied externally to all other chip ground connections. The user must pro-

vide adequate external decoupling capacitors. There are four GND_Qconnections.

Address Bus Ground—GND_Ais an isolated ground for sections of the address bus

I/O drivers. This connection must be tied externally to all other chip ground connec-

tions. The user must provide adequate external decoupling capacitors. There are four

GND_Aconnections.

GND_D(4)

Data Bus Ground—GND_Dis an isolated ground for sections of the data bus I/O driv-

ers. This connection must be tied externally to all other chip ground connections. The

user must provide adequate external decoupling capacitors. There are four GND_Dcon-

nections.

GND_C(2)

GND_H

Bus Control Ground—GND_Cis an isolated ground for the bus control I/O drivers. This

connection must be tied externally to all other chip ground connections. The user must

provide adequate external decoupling capacitors. There are two GND_Cconnections.

Host Ground—GND_his an isolated ground for the HD08 I/O drivers. This connection

must be tied externally to all other chip ground connections. The user must provide

adequate external decoupling capacitors. There is one GND_Hconnection.

GND_S(2)

SHI, ESAI, ESAI_1, DAX and Timer Ground—GND_Sis an isolated ground for the SHI,

ESAI, ESAI_1, DAX and Timer. This connection must be tied externally to all other chip

ground connections. The user must provide adequate external decoupling capacitors.

There are two GND_Sconnections.

1-4

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Clock and PLL

1.4

CLOCK AND PLL

Table 1-4 Clock and PLL Signals

State

during

Reset

Signal

Name

Type

Signal Description

EXTAL

Input

External Clock Input—An external clock source must be connected

to EXTAL in order to supply the clock to the internal clock generator

and PLL.

This input cannot tolerate 5 V.

PCAP

Input

PLL Capacitor—PCAP is an input connecting an off-chip capacitor

to the PLL filter. Connect one capacitor terminal to PCAP and the

other terminal to V_CCP

.

If the PLL is not used, PCAP may be tied to V_CC, GND, or left float-

ing.

PINIT/N

MI

Input

PLL Initial/Nonmaskable Interrupt—During assertion of RESET,

the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the

PLL control register, determining whether the PLL is enabled or dis-

abled. After RESET de assertion and during normal instruction pro-

cessing, the PINIT/NMI Schmitt-trigger input is a

negative-edge-triggered nonmaskable interrupt (NMI) request inter-

nally synchronized to internal system clock.

This input cannot tolerate 5 V.

MOTOROLA

DSP56366 Advance Information

1-5

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

1.5

EXTERNAL MEMORY EXPANSION PORT (PORT A)

When the DSP56366 enters a low-power standby mode (stop or wait), it releases bus mastership and

tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.

1.5.1

External Address Bus

Table 1-5 External Address Bus Signals

State

during

Reset

Signal

Name

Type

Signal Description

A0–A17

Output

Tri-stated Address Bus—When the DSP is the bus master, A0–A17 are

active-high outputs that specify the address for external program

and data memory accesses. Otherwise, the signals are tri-stated.

To minimize power dissipation, A0–A17 do not change state when

external memory spaces are not being accessed.

1.5.2

External Data Bus

Table 1-6 External Data Bus Signals

State

during

Reset

Signal

Name

Type

Signal Description

D0–D23

Input/Output Tri-stated Data Bus—When the DSP is the bus master, D0–D23 are

active-high, bidirectional input/outputs that provide the bidirec-

tional data bus for external program and data memory

accesses. Otherwise, D0–D23 are tri-stated.

1-6

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

1.5.3

External Bus Control

Table 1-7 External Bus Control Signals

State

during

Reset

Signal

Name

Type

Signal Description

AA0–AA2/

Output

Tri-stated

Address Attribute or Row Address Strobe—When

defined as AA, these signals can be used as chip

selects or additional address lines. When defined as

RAS, these signals can be used as RAS for DRAM

interface. These signals are tri-statable outputs with

programmable polarity.

RAS0–RAS2

CAS

Output

Column Address Strobe— When the DSP is the bus

master, CAS is an active-low output used by DRAM to

strobe the column address. Otherwise, if the bus mas-

tership enable (BME) bit in the DRAM control register

is cleared, the signal is tri-stated.

RD

Output

Tri-stated

Read Enable—When the DSP is the bus master, RD

is an active-low output that is asserted to read external

memory on the data bus (D0-D23). Otherwise, RD is

tri-stated.

WR

Write Enable—When the DSP is the bus master, WR

is an active-low output that is asserted to write exter-

nal memory on the data bus (D0-D23). Otherwise, WR

is tri-stated.

MOTOROLA

DSP56366 Advance Information

1-7

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Table 1-7 External Bus Control Signals (continued)

State

during

Reset

Signal

Name

Type

Signal Description

TA

Input

Ignored

Input

Transfer Acknowledge—If the DSP is the bus master

and there is no external bus activity, or the DSP is not

the bus master, the TA input is ignored. The TA input

is a data transfer acknowledge (DTACK) function that

can extend an external bus cycle indefinitely. Any

number of wait states (1, 2. . .infinity) may be added to

the wait states inserted by the BCR by keeping TA

deasserted. In typical operation, TA is deasserted at

the start of a bus cycle, is asserted to enable comple-

tion of the bus cycle, and is deasserted before the next

bus cycle. The current bus cycle completes one clock

period after TA is asserted synchronous to the internal

system clock. The number of wait states is determined

by the TA input or by the bus control register (BCR),

whichever is longer. The BCR can be used to set the

minimum number of wait states in external bus cycles.

In order to use the TA functionality, the BCR must be

programmed to at least one wait state. A zero wait

state access cannot be extended by TA deassertion,

otherwise improper operation may result. TA can oper-

ate synchronously or asynchronously, depending on

the setting of the TAS bit in the operating mode regis-

ter (OMR).

TA functionality may not be used while performing

DRAM type accesses, otherwise improper operation

may result.

1-8

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Table 1-7 External Bus Control Signals (continued)

State

during

Reset

Signal

Name

Type

Signal Description

BR

Output

Bus Request—BR is an active-low output, never

(deasserted) tri-stated. BR is asserted when the DSP requests bus

mastership. BR is deasserted when the DSP no longer

needs the bus. BR may be asserted or deasserted

independent of whether the DSP56366 is a bus mas-

ter or a bus slave. Bus “parking” allows BR to be deas-

serted even though the DSP56366 is the bus master.

(See the description of bus “parking” in the BB signal

description.) The bus request hold (BRH) bit in the

BCR allows BR to be asserted under software control

even though the DSP does not need the bus. BR is

typically sent to an external bus arbitrator that controls

the priority, parking, and tenure of each master on the

same external bus. BR is only affected by DSP

requests for the external bus, never for the internal

bus. During hardware reset, BR is deasserted and the

arbitration is reset to the bus slave state.

BG

Input

Ignored

Input

Bus Grant—BG is an active-low input. BG is asserted

by an external bus arbitration circuit when the

DSP56366 becomes the next bus master. When BG is

asserted, the DSP56366 must wait until BB is deas-

serted before taking bus mastership. When BG is

deasserted, bus mastership is typically given up at the

end of the current bus cycle. This may occur in the

middle of an instruction that requires more than one

external bus cycle for execution.

For proper BG operation, the asynchronous bus arbi-

tration enable bit (ABE) in the OMR register must be

set.

MOTOROLA

DSP56366 Advance Information

1-9

Signal/Connection Descriptions

Interrupt and Mode Control

Table 1-7 External Bus Control Signals (continued)

State

during

Reset

Signal

Name

Type

Signal Description

BB

Input/Output

Input

Bus Busy—BB is a bidirectional active-low input/out-

put. BB indicates that the bus is active. Only after BB

is deasserted can the pending bus master become the

bus master (and then assert the signal again). The bus

master may keep BB asserted after ceasing bus activ-

ity regardless of whether BR is asserted or deas-

serted. This is called “bus parking” and allows the

current bus master to reuse the bus without rearbitra-

tion until another device requires the bus. The deas-

sertion of BB is done by an “active pull-up” method

(i.e., BB is driven high and then released and held high

by an external pull-up resistor).

For proper BB operation, the asynchronous bus arbi-

tration enable bit (ABE) in the OMR register must be

set.

BB requires an external pull-up resistor.

1.6

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.

After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-8 Interrupt and Mode Control

State

during

Reset

Signal

Name

Type

Signal Description

MODA/IRQA

Input

Mode Select A/External Interrupt Request A—MODA/IRQA is

an active-low Schmitt-trigger input, internally synchronized to the

DSP clock. MODA/IRQA selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or nega-

tive-edge-triggered, maskable interrupt request input during nor-

mal instruction processing. MODA, MODB, MODC, and MODD

select one of 16 initial chip operating modes, latched into the

OMR when the RESET signal is deasserted. If the processor is in

the stop standby state and the MODA/IRQA pin is pulled to GND,

the processor will exit the stop state.

This input is 5 V tolerant.

1-10

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Interrupt and Mode Control

Table 1-8 Interrupt and Mode Control (continued)

State

during

Reset

Signal

Name

Type

Signal Description

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

Input

Mode Select B/External Interrupt Request B—MODB/IRQB is

an active-low Schmitt-trigger input, internally synchronized to the

DSP clock. MODB/IRQB selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or nega-

tive-edge-triggered, maskable interrupt request input during nor-

mal instruction processing. MODA, MODB, MODC, and MODD

select one of 16 initial chip operating modes, latched into OMR

when the RESET signal is deasserted.

This input is 5 V tolerant.

Input

Mode Select C/External Interrupt Request C—MODC/IRQC is

an active-low Schmitt-trigger input, internally synchronized to the

DSP clock. MODC/IRQC selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or nega-

tive-edge-triggered, maskable interrupt request input during nor-

mal instruction processing. MODA, MODB, MODC, and MODD

select one of 16 initial chip operating modes, latched into OMR

when the RESET signal is deasserted.

This input is 5 V tolerant.

Mode Select D/External Interrupt Request D—MODD/IRQD is

an active-low Schmitt-trigger input, internally synchronized to the

DSP clock. MODD/IRQD selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or nega-

tive-edge-triggered, maskable interrupt request input during nor-

mal instruction processing. MODA, MODB, MODC, and MODD

select one of 16 initial chip operating modes, latched into OMR

when the RESET signal is deasserted.

This input is 5 V tolerant.

Reset—RESET is an active-low, Schmitt-trigger input. When

asserted, the chip is placed in the Reset state and the internal

phase generator is reset. The Schmitt-trigger input allows a slowly

rising input (such as a capacitor charging) to reset the chip reli-

ably. When the RESET signal is deasserted, the initial chip oper-

ating mode is latched from the MODA, MODB, MODC, and

MODD inputs. The RESET signal must be asserted during power

up. A stable EXTAL signal must be supplied while RESET is being

asserted.

This input is 5 V tolerant.

MOTOROLA

DSP56366 Advance Information

1-11

Signal/Connection Descriptions

PARALLEL HOST INTERFACE (HDI08)

1.7

PARALLEL HOST INTERFACE (HDI08)

The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The

HDI08 supports a variety of standard buses and can be directly connected to a number of industry

standard microcomputers, microprocessors, DSPs, and DMA hardware.

Table 1-9 Host Interface

State during

Signal Name

Type

Signal Description

Reset

H0–H7

Input/

GPIO

Host Data—When HDI08 is programmed to interface a

output

disconnected nonmultiplexed host bus and the HI function is selected,

these signals are lines 0–7 of the bidirectional, tri-state

data bus.

HAD0–HAD7

PB0–PB7

Input/

output

GPIO

Host Address/Data—When HDI08 is programmed to

disconnected interface a multiplexed host bus and the HI function is

selected, these signals are lines 0–7 of the address/data

bidirectional, multiplexed, tri-state bus.

Input, output,

or

GPIO

Port B 0–7—When the HDI08 is configured as GPIO,

disconnected these signals are individually programmable as input, out-

disconnected

put, or internally disconnected.

The default state after reset for these signals is GPIO dis-

connected.

These inputs are 5 V tolerant.

HA0

Input

GPIO

Host Address Input 0—When the HDI08 is programmed

disconnected to interface a nonmultiplexed host bus and the HI function

is selected, this signal is line 0 of the host address input

bus.

HAS/HAS

GPIO

Host Address Strobe—When HDI08 is programmed to

disconnected interface a multiplexed host bus and the HI function is

selected, this signal is the host address strobe (HAS)

Schmitt-trigger input. The polarity of the address strobe is

programmable, but is configured active-low (HAS) follow-

ing reset.

PB8

Input, output,

or

disconnected

GPIO

Port B 8—When the HDI08 is configured as GPIO, this

disconnected signal is individually programmed as input, output, or

internally disconnected.

The default state after reset for this signal is GPIO dis-

connected.

This input is 5 V tolerant.

1-12

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

PARALLEL HOST INTERFACE (HDI08)

Table 1-9 Host Interface (continued)

State during

Reset

Signal Name

Type

Signal Description

HA1

Input

GPIO

Host Address Input 1—When the HDI08 is programmed

disconnected to interface a nonmultiplexed host bus and the HI function

is selected, this signal is line 1 of the host address (HA1)

input bus.

HA8

PB9

Input

GPIO

Host Address 8—When HDI08 is programmed to inter-

disconnected face a multiplexed host bus and the HI function is

selected, this signal is line 8 of the host address (HA8)

input bus.

Input, output,

or

GPIO

Port B 9—When the HDI08 is configured as GPIO, this

disconnected signal is individually programmed as input, output, or

disconnected

internally disconnected.

The default state after reset for this signal is GPIO dis-

connected.

This input is 5 V tolerant.

HA2

HA9

Input

GPIO

Host Address Input 2—When the HDI08 is programmed

disconnected to interface a non-multiplexed host bus and the HI func-

tion is selected, this signal is line 2 of the host address

(HA2) input bus.

GPIO

Host Address 9—When HDI08 is programmed to inter-

disconnected face a multiplexed host bus and the HI function is

selected, this signal is line 9 of the host address (HA9)

input bus.

PB10

Input, Output,

or

GPIO

Port B 10—When the HDI08 is configured as GPIO, this

disconnected signal is individually programmed as input, output, or

Disconnected

internally disconnected.

The default state after reset for this signal is GPIO dis-

connected.

This input is 5 V tolerant.

MOTOROLA

DSP56366 Advance Information

1-13

Signal/Connection Descriptions

PARALLEL HOST INTERFACE (HDI08)

Table 1-9 Host Interface (continued)

State during

Reset

Signal Name

Type

Signal Description

HRW

Input

GPIO

Host Read/Write—When HDI08 is programmed to inter-

disconnected face a single-data-strobe host bus and the HI function is

selected, this signal is the Host Read/Write (HRW) input.

HRD/

HRD

Input

GPIO

Host Read Data—When HDI08 is programmed to inter-

disconnected face a double-data-strobe host bus and the HI function is

selected, this signal is the host read data strobe (HRD)

Schmitt-trigger input. The polarity of the data strobe is

programmable, but is configured as active-low (HRD)

after reset.

PB11

Input, Output,

or

GPIO

Port B 11—When the HDI08 is configured as GPIO, this

disconnected signal is individually programmed as input, output, or

Disconnected

internally disconnected.

The default state after reset for this signal is GPIO dis-

connected.

This input is 5 V tolerant.

HDS/

HDS

Input

GPIO

Host Data Strobe—When HDI08 is programmed to inter-

disconnected face a single-data-strobe host bus and the HI function is

selected, this signal is the host data strobe (HDS)

Schmitt-trigger input. The polarity of the data strobe is

programmable, but is configured as active-low (HDS) fol-

lowing reset.

HWR/

HWR

GPIO

Host Write Data—When HDI08 is programmed to inter-

disconnected face a double-data-strobe host bus and the HI function is

selected, this signal is the host write data strobe (HWR)

Schmitt-trigger input. The polarity of the data strobe is

programmable, but is configured as active-low (HWR) fol-

lowing reset.

PB12

Input, output,

or

GPIO

Port B 12—When the HDI08 is configured as GPIO, this

disconnected signal is individually programmed as input, output, or

disconnected

internally disconnected.

The default state after reset for this signal is GPIO dis-

connected.

This input is 5 V tolerant.

1-14

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

PARALLEL HOST INTERFACE (HDI08)

Table 1-9 Host Interface (continued)

State during

Reset

Signal Name

Type

Signal Description

HCS

Input

GPIO

Host Chip Select—When HDI08 is programmed to inter-

disconnected face a nonmultiplexed host bus and the HI function is

selected, this signal is the host chip select (HCS) input.

The polarity of the chip select is programmable, but is

configured active-low (HCS) after reset.

HA10

PB13

Input

GPIO

Host Address 10—When HDI08 is programmed to inter-

disconnected face a multiplexed host bus and the HI function is

selected, this signal is line 10 of the host address (HA10)

input bus.

Input, output,

or

GPIO

Port B 13—When the HDI08 is configured as GPIO, this

disconnected signal is individually programmed as input, output, or

disconnected

internally disconnected.

The default state after reset for this signal is GPIO dis-

connected.

This input is 5 V tolerant.

HOREQ/

HOREQ

Output

GPIO

Host Request—When HDI08 is programmed to interface

disconnected a single host request host bus and the HI function is

selected, this signal is the host request (HOREQ) output.

The polarity of the host request is programmable, but is

configured as active-low (HOREQ) following reset. The

host request may be programmed as a driven or

open-drain output.

HTRQ/

HTRQ

GPIO

Transmit Host Request—When HDI08 is programmed

disconnected to interface a double host request host bus and the HI

function is selected, this signal is the transmit host

request (HTRQ) output. The polarity of the host request is

programmable, but is configured as active-low (HTRQ)

following reset. The host request may be programmed as

a driven or open-drain output.

PB14

Input, output,

or

disconnected

GPIO

Port B 14—When the HDI08 is configured as GPIO, this

disconnected signal is individually programmed as input, output, or

internally disconnected.

The default state after reset for this signal is GPIO dis-

connected.

This input is 5 V tolerant.

MOTOROLA

DSP56366 Advance Information

1-15

Signal/Connection Descriptions

PARALLEL HOST INTERFACE (HDI08)

Table 1-9 Host Interface (continued)

State during

Reset

Signal Name

Type

Signal Description

HACK/

HACK

Input

GPIO

Host Acknowledge—When HDI08 is programmed to

disconnected interface a single host request host bus and the HI func-

tion is selected, this signal is the host acknowledge

(HACK) Schmitt-trigger input. The polarity of the host

acknowledge is programmable, but is configured as

active-low (HACK) after reset.

HRRQ/

HRRQ

Output

GPIO

Receive Host Request—When HDI08 is programmed to

disconnected interface a double host request host bus and the HI func-

tion is selected, this signal is the receive host request

(HRRQ) output. The polarity of the host request is pro-

grammable, but is configured as active-low (HRRQ) after

reset. The host request may be programmed as a driven

or open-drain output.

PB15

Input, output,

or

GPIO

Port B 15—When the HDI08 is configured as GPIO, this

disconnected signal is individually programmed as input, output, or

disconnected

internally disconnected.

The default state after reset for this signal is GPIO dis-

connected.

This input is 5 V tolerant.

1-16

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Serial Host Interface

1.8

SERIAL HOST INTERFACE

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I²C mode.

Table 1-10 Serial Host Interface Signals

Signal

Name

Signal State during

Signal Description

Type

Reset

SCK

Input or

output

Tri-stated

SPI Serial Clock—The SCK signal is an output when the SPI is config-

ured as a master and a Schmitt-trigger input when the SPI is configured

as a slave. When the SPI is configured as a master, the SCK signal is

derived from the internal SHI clock generator. When the SPI is config-

ured as a slave, the SCK signal is an input, and the clock signal from

the external master synchronizes the data transfer. The SCK signal is

ignored by the SPI if it is defined as a slave and the slave select (SS)

signal is not asserted. In both the master and slave SPI devices, data is

shifted on one edge of the SCK signal and is sampled on the opposite

edge where data is stable. Edge polarity is determined by the SPI

transfer protocol.

SCL

Input or

output

Tri-stated

I²C Serial Clock—SCL carries the clock for I²C bus transactions in the

I²C mode. SCL is a Schmitt-trigger input when configured as a slave

and an open-drain output when configured as a master. SCL should be

connected to V_CCthrough a pull-up resistor.

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

MISO

SDA

Input or

output

Tri-stated

SPI Master-In-Slave-Out—When the SPI is configured as a master,

MISO is the master data input line. The MISO signal is used in conjunc-

tion with the MOSI signal for transmitting and receiving serial data. This

signal is a Schmitt-trigger input when configured for the SPI Master

mode, an output when configured for the SPI Slave mode, and tri-stated

if configured for the SPI Slave mode when SS is deasserted. An external

pull-up resistor is not required for SPI operation.

Input or

open-drain

output

I²C Data and Acknowledge—In I²C mode, SDA is a Schmitt-trigger

input when receiving and an open-drain output when transmitting. SDA

should be connected to V_CCthrough a pull-up resistor. SDA carries the

data for I²C transactions. The data in SDA must be stable during the

high period of SCL. The data in SDA is only allowed to change when

SCL is low. When the bus is free, SDA is high. The SDA line is only

allowed to change during the time SCL is high in the case of start and

stop events. A high-to-low transition of the SDA line while SCL is high is

a unique situation, and is defined as the start event. A low-to-high tran-

sition of SDA while SCL is high is a unique situation defined as the stop

event.

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

MOTOROLA

DSP56366 Advance Information

1-17

Signal/Connection Descriptions

Serial Host Interface

Table 1-10 Serial Host Interface Signals (continued)

Signal

Name

Signal State during

Signal Description

Type

Reset

MOSI

Input or

output

Tri-stated

SPI Master-Out-Slave-In—When the SPI is configured as a master,

MOSI is the master data output line. The MOSI signal is used in conjunc-

tion with the MISO signal for transmitting and receiving serial data. MOSI

is the slave data input line when the SPI is configured as a slave. This

signal is a Schmitt-trigger input when configured for the SPI Slave mode.

HA0

Input

I²C Slave Address 0—This signal uses a Schmitt-trigger input when

configured for the I²C mode. When configured for I²C slave mode, the

HA0 signal is used to form the slave device address. HA0 is ignored

when configured for the I²C master mode.

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

SS

Input

Tri-stated

SPI Slave Select—This signal is an active low Schmitt-trigger input

when configured for the SPI mode. When configured for the SPI Slave

mode, this signal is used to enable the SPI slave for transfer. When

configured for the SPI master mode, this signal should be kept deas-

serted (pulled high). If it is asserted while configured as SPI master, a

bus error condition is flagged. If SS is deasserted, the SHI ignores SCK

clocks and keeps the MISO output signal in the high-impedance state.

HA2

I²C Slave Address 2—This signal uses a Schmitt-trigger input when

configured for the I²C mode. When configured for the I²C Slave mode,

the HA2 signal is used to form the slave device address. HA2 is ignored

in the I²C master mode.

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This input is 5 V tolerant.

HREQ

Input or

Output

Tri-stated

Host Request—This signal is an active low Schmitt-trigger input when

configured for the master mode but an active low output when config-

ured for the slave mode.

When configured for the slave mode, HREQ is asserted to indicate that

the SHI is ready for the next data word transfer and deasserted at the

first clock pulse of the new data word transfer. When configured for the

master mode, HREQ is an input. When asserted by the external slave

device, it will trigger the start of the data word transfer by the master.

After finishing the data word transfer, the master will await the next

assertion of HREQ to proceed to the next transfer.

This signal is tri-stated during hardware, software, personal reset, or

when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no

need for external pull-up in this state.

This input is 5 V tolerant.

1-18

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

1.9

ENHANCED SERIAL AUDIO INTERFACE

Table 1-11 Enhanced Serial Audio Interface Signals

Signal

Name

Stateduring

Signal Type

Signal Description

Reset

HCKR

Input or output

GPIO

High Frequency Clock for Receiver—When programmed as an

disconnected input, this signal provides a high frequency clock source for the

ESAI receiver as an alternate to the DSP core clock. When pro-

grammed as an output, this signal can serve as a high-frequency

sample clock (e.g., for external digital to analog converters

[DACs]) or as an additional system clock.

PC2

Input, output,

or

GPIO

Port C 2—When the ESAI is configured as GPIO, this signal is

disconnected individually programmable as input, output, or internally discon-

disconnected

nected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

HCKT

Input or output

GPIO

High Frequency Clock for Transmitter—When pro-

disconnected grammed as an input, this signal provides a high frequency

clock source for the ESAI transmitter as an alternate to the

DSP core clock. When programmed as an output, this signal

can serve as a high frequency sample clock (e.g., for external

DACs) or as an additional system clock.

PC5

Input, output,

or

GPIO

Port C 5—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally dis-

disconnected

connected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA

DSP56366 Advance Information

1-19

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (continued)

Signal

Name

Stateduring

Reset

Signal Type

Signal Description

FSR

Input or output

GPIO

Frame Sync for Receiver—This is the receiver frame sync

disconnected input/output signal. In the asynchronous mode (SYN=0), the

FSR pin operates as the frame sync input or output used by

all the enabled receivers. In the synchronous mode (SYN=1),

it operates as either the serial flag 1 pin (TEBE=0), or as the

transmitter external buffer enable control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is

determined by the RFSD bit in the RCCR register. When con-

figured as the output flag OF1, this pin will reflect the value of

the OF1 bit in the SAICR register, and the data in the OF1 bit

will show up at the pin synchronized to the frame sync in nor-

mal mode or the slot in network mode. When configured as

the input flag IF1, the data value at the pin will be stored in the

IF1 bit in the SAISR register, synchronized by the frame sync

in normal mode or the slot in network mode.

PC1

FST

Input, output,

or

disconnected

GPIO

Port C 1—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally dis-

connected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Input or output

GPIO

Frame Sync for Transmitter—This is the transmitter frame

disconnected sync input/output signal. For synchronous mode, this signal is

the frame sync for both transmitters and receivers. For asyn-

chronous mode, FST is the frame sync for the transmitters

only. The direction is determined by the transmitter frame

sync direction (TFSD) bit in the ESAI transmit clock control

register (TCCR).

PC4

Input, output,

or

disconnected

Port C 4—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally dis-

connected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

1-20

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (continued)

Signal

Name

Stateduring

Reset

Signal Type

Signal Description

SCKR

Input or output

GPIO

Receiver Serial Clock—SCKR provides the receiver serial

disconnected bit clock for the ESAI. The SCKR operates as a clock input or

output used by all the enabled receivers in the asynchronous

mode (SYN=0), or as serial flag 0 pin in the synchronous

mode (SYN=1).

When this pin is configured as serial flag pin, its direction is

determined by the RCKD bit in the RCCR register. When con-

figured as the output flag OF0, this pin will reflect the value of

the OF0 bit in the SAICR register, and the data in the OF0 bit

will show up at the pin synchronized to the frame sync in nor-

mal mode or the slot in network mode. When configured as

the input flag IF0, the data value at the pin will be stored in the

IF0 bit in the SAISR register, synchronized by the frame sync

in normal mode or the slot in network mode.

PC0

Input, output,

or

GPIO

Port C 0—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally dis-

disconnected

connected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SCKT

PC3

Input or output

GPIO

Transmitter Serial Clock—This signal provides the serial bit

disconnected rate clock for the ESAI. SCKT is a clock input or output used

by all enabled transmitters and receivers in synchronous

mode, or by all enabled transmitters in asynchronous mode.

Input, output,

or

GPIO

Port C 3—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally dis-

disconnected

connected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO5

Output

Input

GPIO

Serial Data Output 5—When programmed as a transmitter,

disconnected SDO5 is used to transmit data from the TX5 serial transmit

shift register.

SDI0

PC6

GPIO

Serial Data Input 0—When programmed as a receiver, SDI0 is

disconnected used to receive serial data into the RX0 serial receive shift register.

Input, output,

or

disconnected

GPIO

Port C 6—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally dis-

connected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA

DSP56366 Advance Information

1-21

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (continued)

Signal

Name

Stateduring

Reset

Signal Type

Signal Description

SDO4

SDI1

PC7

Output

GPIO

Serial Data Output 4—When programmed as a transmitter,

disconnected SDO4 is used to transmit data from the TX4 serial transmit

shift register.

Input

GPIO

Serial Data Input 1—When programmed as a receiver, SDI1

disconnected is used to receive serial data into the RX1 serial receive shift

register.

Input, output,

or

GPIO

Port C 7—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally dis-

disconnected

connected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO3/S

DO3_1

Output

Input

GPIO

Serial Data Output 3—When programmed as a transmitter,

disconnected SDO3 is used to transmit data from the TX3 serial transmit

shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial

Data Output 3.

SDI2/

GPIO

Serial Data Input 2—When programmed as a receiver, SDI2

SDI2_1

disconnected is used to receive serial data into the RX2 serial receive shift

register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial

Data Input 2.

PC8/PE8 Input, output,

GPIO

Port C 8—When the ESAI is configured as GPIO, this signal

or

disconnected is individually programmable as input, output, or internally dis-

disconnected

connected.

When enabled for ESAI_1 GPIO, this is the Port E 8 signal.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

1-22

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (continued)

Signal

Name

Stateduring

Reset

Signal Type

Signal Description

SDO2/

Output

GPIO

Serial Data Output 2—When programmed as a transmitter,

SDO2_1

disconnected SDO2 is used to transmit data from the TX2 serial transmit

shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial

Data Output 2.

SDI3/SDI

3_1

Input

GPIO

Serial Data Input 3—When programmed as a receiver, SDI3

disconnected is used to receive serial data into the RX3 serial receive shift

register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial

Data Input 3.

PC9/PE9 Input, output,

GPIO

Port C 9—When the ESAI is configured as GPIO, this signal

or

disconnected is individually programmable as input, output, or internally dis-

disconnected

connected.

When enabled for ESAI_1 GPIO, this is the Port E 9 signal.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO1/

SDO1_1

Output

GPIO

disconnected the TX1 serial transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial

Serial Data Output 1—SDO1 is used to transmit data from

Data Output 1.

PC10/

PE10

Input, output,

or

GPIO

Port C 10—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally dis-

disconnected

connected.

When enabled for ESAI_1 GPIO, this is the Port E 10 signal.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO0/S

DO0_1

Output

GPIO

disconnected the TX0 serial transmit shift register.

When enabled for ESAI_1 operation, this is the ESAI_1 Serial

Serial Data Output 0—SDO0 is used to transmit data from

Data Output 0.

PC11/

PE11

Input, output,

or

disconnected

GPIO

Port C 11—When the ESAI is configured as GPIO, this signal

disconnected is individually programmable as input, output, or internally dis-

connected.

When enabled for ESAI_1 GPIO, this is the Port E 11 signal.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA

DSP56366 Advance Information

1-23

Signal/Connection Descriptions

Enhanced Serial Audio Interface_1

ENHANCED SERIAL AUDIO INTERFACE_1

Table 1-12 Enhanced Serial Audio Interface_1 Signals

Signal

Name

State during

Signal Type

Signal Description

Reset

FSR_1 Input or output

GPIO

Frame Sync for Receiver_1—This is the receiver frame sync

disconnected input/output signal. In the asynchronous mode (SYN=0), the

FSR pin operates as the frame sync input or output used by all

the enabled receivers. In the synchronous mode (SYN=1), it

operates as either the serial flag 1 pin (TEBE=0), or as the

transmitter external buffer enable control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is

determined by the RFSD bit in the RCCR register. When con-

figured as the output flag OF1, this pin will reflect the value of

the OF1 bit in the SAICR register, and the data in the OF1 bit

will show up at the pin synchronized to the frame sync in nor-

mal mode or the slot in network mode. When configured as the

input flag IF1, the data value at the pin will be stored in the IF1

bit in the SAISR register, synchronized by the frame sync in

normal mode or the slot in network mode.

PE1

Input, output,

or

GPIO

Port E 1—When the ESAI is configured as GPIO, this signal is

disconnected individually programmable as input, output, or internally discon-

disconnected

nected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

FST_1 Input or output

GPIO

Frame Sync for Transmitter_1—This is the transmitter frame

disconnected sync input/output signal. For synchronous mode, this signal is

the frame sync for both transmitters and receivers. For asyn-

chronous mode, FST is the frame sync for the transmitters

only. The direction is determined by the transmitter frame sync

direction (TFSD) bit in the ESAI transmit clock control register

(TCCR).

PE4

Input, output,

or

disconnected

GPIO

Port E 4—When the ESAI is configured as GPIO, this signal is

disconnected individually programmable as input, output, or internally discon-

nected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

1-24

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface_1

Table 1-12 Enhanced Serial Audio Interface_1 Signals

Signal

Name

State during

Reset

Signal Type

Signal Description

SCKR_1 Input or output

GPIO

Receiver Serial Clock_1—SCKR provides the receiver serial

disconnected bit clock for the ESAI. The SCKR operates as a clock input or

output used by all the enabled receivers in the asynchronous

mode (SYN=0), or as serial flag 0 pin in the synchronous mode

(SYN=1).

When this pin is configured as serial flag pin, its direction is

determined by the RCKD bit in the RCCR register. When con-

figured as the output flag OF0, this pin will reflect the value of

the OF0 bit in the SAICR register, and the data in the OF0 bit

will show up at the pin synchronized to the frame sync in nor-

mal mode or the slot in network mode. When configured as the

input flag IF0, the data value at the pin will be stored in the IF0

bit in the SAISR register, synchronized by the frame sync in

normal mode or the slot in network mode.

PE0

Input, output,

or

GPIO

Port E 0—When the ESAI is configured as GPIO, this signal is

disconnected individually programmable as input, output, or internally discon-

disconnected

nected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

SCKT_1 Input or output

GPIO

Transmitter Serial Clock_1—This signal provides the serial

disconnected bit rate clock for the ESAI. SCKT is a clock input or output used

by all enabled transmitters and receivers in synchronous mode,

or by all enabled transmitters in asynchronous mode.

PE3

Input, output,

or

GPIO

Port E 3—When the ESAI is configured as GPIO, this signal is

disconnected individually programmable as input, output, or internally discon-

disconnected

nected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

SDO5_1

Output

Input

GPIO

Serial Data Output 5_1—When programmed as a transmitter,

disconnected SDO5 is used to transmit data from the TX5 serial transmit shift reg-

ister.

SDI0_1

PE6

GPIO

Serial Data Input 0_1—When programmed as a receiver, SDI0 is

disconnected used to receive serial data into the RX0 serial receive shift register.

Input, output,

or

disconnected

GPIO

Port E 6—When the ESAI is configured as GPIO, this signal is indi-

disconnected vidually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input cannot tolerate 5 V.

MOTOROLA

DSP56366 Advance Information

1-25

Signal/Connection Descriptions

spdif tRANSMITTER Digital Audio Interface

Table 1-12 Enhanced Serial Audio Interface_1 Signals

Signal

Name

State during

Signal Type

Signal Description

Reset

SDO4_1

SDI1_1

PE7

Output

GPIO

Serial Data Output 4_1—When programmed as a transmitter,

disconnected SDO4 is used to transmit data from the TX4 serial transmit shift

register.

Input

GPIO

Serial Data Input 1_1—When programmed as a receiver,

disconnected SDI1 is used to receive serial data into the RX1 serial receive

shift register.

Input, output,

or

GPIO

Port E 7—When the ESAI is configured as GPIO, this signal is

disconnected individually programmable as input, output, or internally discon-

disconnected

nected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

1.10 SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE

Table 1-13 Digital Audio Interface (DAX) Signals

Signal

Name

State During

Reset

Type

Signal Description

ACI

Input

GPIO

Audio Clock Input—This is the DAX clock input. When pro-

Disconnected grammed to use an external clock, this input supplies the DAX

clock. The external clock frequency must be 256, 384, or 512

times the audio sampling frequency (256 × Fs, 384 × Fs or 512

× Fs, respectively).

PD0

Input,

GPIO

Port D 0—When the DAX is configured as GPIO, this signal is

output, or

disconnected

Disconnected individually programmable as input, output, or internally discon-

nected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

ADO

PD1

Output

GPIO

Disconnected

Digital Audio Data Output—This signal is an audio and

non-audio output in the form of AES/EBU, CP340 and IEC958

data in a biphase mark format.

Input,

output, or

GPIO

Disconnected

Port D 1—When the DAX is configured as GPIO, this signal is indi-

vidually programmable as input, output, or internally disconnected.

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

1-26

DSP56366 Advance Information

MOTOROLA

Signal/Connection Descriptions

Timer

1.11 TIMER

Table 1-14 Timer Signal

State

during

Reset

Signal

Name

Type

Signal Description

TIO0

Input or

Output

Input

Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions

as an external event counter or in measurement mode, TIO0 is

used as input. When timer 0 functions in watchdog, timer, or pulse

modulation mode, TIO0 is used as output.

The default mode after reset is GPIO input. This can be changed to

output or configured as a timer input/output through the timer 0

control/status register (TCSR0). If TIO0 is not being used, it is rec-

ommended to either define it as GPIO output immediately at the

beginning of operation or leave it defined as GPIO input but con-

nected to Vcc through a pull-up resistor in order to ensure a stable

logic level at this input.

This input is 5 V tolerant.

1.12 JTAG/OnCE INTERFACE

Table 1-15 JTAG/OnCE Interface

State

during

Reset

Signal Signal

Signal Description

Name

Type

TCK

Input

Input Test Clock—TCK is a test clock input signal used to synchronize the

JTAG test logic. It has an internal pull-up resistor.

This input is 5 V tolerant.

TDI

Input

Input Test Data Input—TDI is a test data serial input signal used for test

instructions and data. TDI is sampled on the rising edge of TCK and has

an internal pull-up resistor.

This input is 5 V tolerant.

TDO

TMS

Output Tri-stated Test Data Output—TDO is a test data serial output signal used for test

instructions and data. TDO is tri-statable and is actively driven in the shift-IR

and shift-DR controller states. TDO changes on the falling edge of TCK.

Input

Input Test Mode Select—TMS is an input signal used to sequence the test con-

troller’s state machine. TMS is sampled on the rising edge of TCK and has

an internal pull-up resistor.

This input is 5 V tolerant.

MOTOROLA

DSP56366 Advance Information

1-27

THIS PAGE INTENTIONALLY LEFT BLANK

SECTION 2

SPECIFICATIONS

2.1

INTRODUCTION

The DSP56366 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs

and outputs. The DSP56366 specifications are preliminary and are from design simulations, and may not

be fully tested or guaranteed. Finalized specifications will be published after full characterization and

device qualifications are complete.

2.2

MAXIMUM RATINGS

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields. However, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability of operation is

enhanced if unused inputs are pulled to an

appropriate logic voltage level (e.g., either

GND or V ). The suggested value for a

CC

pullup or pulldown resistor is 10 kΩ.

Note: In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a

reasonable sum. A maximum specification is calculated using a worst case

variation of process parameter values in one direction. The minimum

specification is calculated using the worst case for the same parameters in

the opposite direction. Therefore, a “maximum” value for a specification will

never occur in the same device that has a “minimum” value for another

specification; adding a maximum to a minimum represents a condition that

can never exist.

MOTOROLA

DSP56366 Advance Information

2-1

Specifications

Thermal Characteristics

Table 2-1 Maximum Ratings

1

1, 2

Symbol

Unit

Rating

Value

Supply Voltage

V_CC

−0.3 to +4.0

GND -0.3 to V_CC+ 0.3

GND − 0.3 to V_CC+ 3.95

10

V

All input voltages excluding “5 V tolerant” inputs³

All “5 V tolerant” input voltages³

V_IN

V_IN5

I

V

Current drain per pin excluding V_CCand GND

Operating temperature range

mA

°C

T_J

−40 to +110

Storage temperature

T_STG

−55 to +125

Notes: 1. GND = 0 V, V_CC= 3.3 V ± 0.16 V, T_J= –40°C to +110°C, CL = 50 pF

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not

guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent

damage to the device.

3. CAUTION: All “5 V Tolerant” input voltages must not be more than 3.95 V greater than the supply

voltage; this restriction applies to “power on”, as well as during normal operation. In any case, the

input voltages cannot be more than 5.75 V. “5 V Tolerant” inputs are inputs that tolerate 5 V.

2.3

THERMAL CHARACTERISTICS

Table 2-2 Thermal Characteristics

Characteristic

SymbolTQFP

uVeal Unit

Junction-to-ambient thermal resistance^{1, 2}Natural Convection

Junction-to-case thermal resistance³

R

_θJAor θ_JA

_θJCor θ_JC

Ψ_JT

37

7

°C/W

R

°C/W

Thermal characterization parameter⁴Natural Convection

2.0

Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance,

mounting site (board) temperature, ambient temperature, air flow, power dissipation of other

components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1).

4. Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JT.

2-2

DSP56366 Advance Information

MOTOROLA

Specifications

DC Electrical Characteristics

2.4

DC ELECTRICAL CHARACTERISTICS

6

Table 2-3 DC Electrical Characteristics

Characteristics

SymbolMin

Typ

Max

Unit

3.46

Supply voltage

V_CC

3.14

3.3

V

Input high voltage

V_IH

2.0

—

V_CC

• D(0:23), BG, BB, TA, ESAI_1_{(except SDO4_1)}

• MOD¹/IRQ¹, RESET, PINIT/NMI and all

JTAG/ESAI/Timer/HDI08/DAX/ESAI_1_(only

_{SDO4_1)}/SHI_{(SPI mode)}

V_IHP

V_CC+ 3.95

• SHI_{(I2C mode)}

• EXTAL⁸

V_IHP

1.5

—

V_CC+ 3.95

V_CC

V_IHX

0.8 × V_CC

Input low voltage

V

V_IL

–0.3

—

0.8

• D(0:23), BG, BB, TA, ESAI_1_{(except SDO4_1)}

• MOD¹/IRQ¹, RESET, PINIT/NMI and all

JTAG/ESAI/Timer/HDI08/DAX/ESAI_1_(only

_{SDO4_1)}/SHI_{(SPI mode)}

V_ILP

–0.3

• SHI_{(I2C mode)}

• EXTAL⁸

V_ILP

V_ILX

I_IN

–0.3

–10

—

0.3 x V_CC

0.2 x V_CC

10

Input leakage current

µA

High impedance (off-state) input current

(@ 2.4 V / 0.4 V)

I_TSI

10

Output high voltage

V_OH

2.4

—

V

• TTL (I_OH= –0.4 mA)^5,7

• CMOS (I_OH= –10 µA)⁵

V_CC– 0.01

V

Output low voltage

V_OL

—

0.4

• TTL (I_OL= 3.0 mA, open-drain pins I_OL= 6.7

mA)^5,7

• CMOS (I_OL= 10 µA)⁵

—

0.01

200

Internal supply current²at internal clock of

120MHz

I_CCI

116

mA

• In Normal mode

MOTOROLA

DSP56366 Advance Information

2-3

Specifications

AC Electrical Characteristics

6

Table 2-3 DC Electrical Characteristics (continued)

Characteristics

• In Wait mode

SymbolMin

Typ

Max

Unit

I_CCW

I_CCS

—

7.3

1

25

10

mA

pF

• In Stop mode⁴

PLL supply current

Input capacitance⁵

1

2.5

10

C_IN

—

Notes: 1. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins

2. Appendix A, Power Consumption Benchmark provides a formula to compute the estimated current

requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not

allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power

consumption numbers in this specification are 90% of the measured results of this benchmark. This

reflects typical DSP applications. Typical internal supply current is measured with V_CC= 3.3 V at T_J=

105°C. Maximum internal supply current is measured with V_CC= 3.46 V at T_J= 105°C.

3. Deleted.

4. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be

terminated (i.e., not allowed to float).

5. Periodically sampled and not 100% tested

6. V_CC= 3.3 V ± .16 V; T_J= – 40°C to +105°C, C_L= 50 pF

7. This characteristic does not apply to PCAP.

8. Driving EXTAL to the low V_IHXor the high V_ILXvalue may cause additional power consumption (DC

current). To minimize power consumption, the minimum V_IHXshould be no lower than

0.9 × V_CCand the maximum V_ILXshould be no higher than 0.1 × V_CC

.

2.5

AC ELECTRICAL CHARACTERISTICS

The timing waveforms shown in the AC electrical characteristics section are tested with a V_ILmaximum of

0.3 V and a V_IHminimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown

in Note 8 of the previous table. AC timing specifications, which are referenced to a device input signal, are

measured in production with respect to the 50% point of the respective input signal’s transition. DSP56366

output levels are measured with the production test machine V_OLand V_OHreference levels set at 0.4 V

and 2.4 V, respectively.

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device

AC test conditions are 15 MHz and rated speed.

2-4

DSP56366 Advance Information

MOTOROLA

Specifications

Internal Clocks

2.6

INTERNAL CLOCKS

Table 2-4 Internal Clocks

1, 2

Expression

Characteristics

Symbol

Min

Typ

Max

Internal operation frequency with

PLL enabled

f

—

(Ef × MF)/

(PDF × DF)

—

Internal operation frequency with

PLL disabled

—

Ef/2

—

Internal clock high period

T_H

• With PLL disabled

—

ET_C

—

• With PLL enabled and

0.49 × ET_C×

PDF × DF/MF

0.51 × ET_C×

PDF × DF/MF

MF ≤ 4

• With PLL enabled and

MF > 4

0.47 × ET_C×

PDF × DF/MF

—

0.53 × ET_C×

PDF × DF/MF

Internal clock low period

• With PLL disabled

—

ET_C

—

T_L

• With PLL enabled and

0.49 × ET_C×

PDF × DF/MF

0.51 × ET_C×

PDF × DF/MF

MF ≤ 4

• With PLL enabled and

MF > 4

0.47 × ET_C×

PDF × DF/MF

—

0.53 × ET_C×

PDF × DF/MF

Internal clock cycle time with PLL

enabled

T_C

—

ET_C× PDF ×

—

DF/MF

Internal clock cycle time with PLL

disabled

2 × ET_C

Instruction cycle time

I_CYC

T_C

Notes: 1. DF = Division Factor

Ef = External frequency

ET_C= External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

T_C= internal clock cycle

2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion

of the PLL.

MOTOROLA

DSP56366 Advance Information

2-5

Specifications

EXTERNAL CLOCK OPERATION

2.7

EXTERNAL CLOCK OPERATION

The DSP56366 system clock is an externally supplied square wave voltage source connected to EXTAL

(See Figure 2-1).

V_IHC

Midpoint

EXTAL

ETH

ETL

V_ILC

2

3

4

ETC

Note: The midpoint is 0.5 (V_IHC+ V_ILC).

Figure 2-1 External Clock Timing

Table 2-5 Clock Operation

No.

Characteristics

SymbolMin

Max

1

Frequency of EXTAL (EXTAL Pin Frequency)

Ef

0

120.0

The rise and fall time of this external clock should

be 3 ns maximum.

2

3

4

7

EXTAL input high^{1, 2}

• With PLL disabled (46.7%–53.3% duty cycle⁴)

ET_H

ET_L

ET_C

3.89 ns

3.54 ns

∞

• With PLL enabled (42.5%–57.5% duty cycle⁴)

157.0 µs

EXTAL input low^{1, 2}

• With PLL disabled (46.7%–53.3% duty cycle⁴)

3.89 ns

3.54 ns

∞

• With PLL enabled (42.5%–57.5% duty cycle⁴)

157.0 µs

EXTAL cycle time²

• With PLL disabled

8.33 ns

∞

• With PLL enabled

273.1 µs

32

Instruction cycle time = I_CYC= T_C

I_CYC

16.66 ns

8.33 ns

∞

• With PLL disabled

• With PLL enabled

8.53 µs

2-6

DSP56366 Advance Information

MOTOROLA

Specifications

EXTERNAL CLOCK OPERATION

Table 2-5 Clock Operation (continued)

Characteristics SymbolMin

No.

Max

Notes: 1. Measured at 50% of the input transition

2. The maximum value for PLL enabled is given for minimum V_COand maximum MF.

3. The maximum value for PLL enabled is given for minimum VCO and maximum DF.

4. The indicated duty cycle is for the specified maximum frequency for which a part is rated.

The minimum clock high or low time required for correct operation, however, remains the

same at lower operating frequencies; therefore, when a lower clock frequency is used, the

signal symmetry may vary from the specified duty cycle as long as the minimum high time

and low time requirements are met.

MOTOROLA

DSP56366 Advance Information

2-7

Specifications

Phase Lock Loop (PLL) Characteristics

2.8

PHASE LOCK LOOP (PLL) CHARACTERISTICS

Table 2-6 PLL Characteristics

Characteristics

Min

Max

Unit

V_COfrequency when PLL enabled

30

240

MHz

(MF × E_f× 2/PDF)

1)

PLL external capacitor (PCAP pin to V_CCP) (C_PCAP

pF

• @ MF ≤ 4

(MF × 580) − 100 (MF × 780) − 140

MF × 830 MF × 1470

• @ MF > 4

Notes: 1. C_PCAPis the value of the PLL capacitor (connected between the PCAP pin and V_CCP). The

recommended value in pF for C_PCAPcan be computed from one of the following equations:

(MF x 680)-120, for MF ≤ 4, or

MF x 1100, for MF > 4.

2.9

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing

No.

Characteristics

Expression

Min Max Unit

8

Delay from RESET assertion to all pins at reset

value³

—

26.0

ns

9

Required RESET duration⁴

50 × ET_C

416.7

—

ns

• Power on, external clock generator, PLL

disabled

• Power on, external clock generator, PLL

enabled

1000 × ET_C

2.5 × T_C

8.3

—

µs

• During normal operation

20.8

ns

10 Delay from asynchronous RESET deassertion

to first external address output (internal reset

deassertion)⁵

29.1

—

ns

• Minimum

3.25 × T_C+ 2.0

• Maximum

20.25 T_C+ 7.50

—

176.2 ns

ns

13 Mode select setup time

30.0

—

2-8

DSP56366 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)

No.

Characteristics

Expression

Min Max Unit

14 Mode select hold time

0.0

5.5

—

ns

15 Minimum edge-triggered interrupt request

assertion width

16 Minimum edge-triggered interrupt request deas-

sertion width

5.5

—

ns

17 Delay from IRQA, IRQB, IRQC, IRQD, NMI

assertion to external memory access address

out valid

4.25 × T_C+ 2.0

37.4

—

ns

• Caused by first interrupt instruction fetch

• Caused by first interrupt instruction execution

7.25 × T_C+ 2.0

10 × T_C+ 5.0

62.4

88.3

—

ns

18 Delay from IRQA, IRQB, IRQC, IRQD, NMI

assertion to general-purpose transfer output valid

caused by first interrupt instruction execution

19 Delay from address output valid caused by first 3.75 × T_C+ WS × T_C– 10.94

interrupt instruction execute to interrupt request

—

Note 7 ns

deassertion for level sensitive fast interrupts¹

20 Delay from RD assertion to interrupt request

deassertion for level sensitive fast interrupts¹

3.25 × T_C+ WS × T_C– 10.94

Note 7 ns

ns

21 Delay from WR assertion to interrupt request

deassertion for level sensitive fast interrupts¹

• DRAM for all WS

(WS + 3.5) × T_C– 10.94

—

Note 7

• SRAM WS = 1

• SRAM WS = 2, 3

• SRAM WS ≥ 4

(WS + 3.5) × T_C– 10.94

(WS + 3) × T_C– 10.94

(WS + 2.5) × T_C– 10.94

—

Note 7

—

24 Duration for IRQA assertion to recover from

Stop state

4.9

MOTOROLA

DSP56366 Advance Information

2-9

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)

No.

Characteristics

Expression

Min Max Unit

25 Delay from IRQA assertion to fetch of first

instruction (when exiting Stop)^{2, 3}

—

ms

• PLL is not active during Stop (PCTL Bit 17 =

0) and Stop delay is enabled

(OMR Bit 6 = 0)

PLC × ET_C× PDF + (128 K −

PLC/2) × T_C

• PLL is not active during Stop (PCTL Bit 17 = PLC × ET_C× PDF + (23.75 ±

—

ms

ns

0) and Stop delay is not enabled (OMR Bit 6 = 0.5) × T_C

1)

• PLL is active during Stop (PCTL Bit 17 = 1) (8.25 ± 0.5) × T_C

64.6

72.9

(Implies No Stop Delay)

26 Duration of level sensitive IRQA assertion to

ensure interrupt service (when exiting Stop)^{2, 3}

• PLL is not active during Stop (PCTL Bit 17 =

0) and Stop delay is enabled

—

ms

PLC × ET_C× PDF + (128K −

PLC/2) × T_C

(OMR Bit 6 = 0)

• PLL is not active during Stop (PCTL Bit 17 = PLC × ET_C× PDF + (20.5 ±

—

45.8

—

ms

ns

0) and Stop delay is not enabled

(OMR Bit 6 = 1)

0.5) × T_C

• PLL is active during Stop (PCTL Bit 17 = 1)

(implies no Stop delay)

5.5 × T_C

27 Interrupt Requests Rate

12T_C

100.0 ns

• HDI08, ESAI, ESAI_1, SHI, DAX, Timer

• DMA

8T_C

—

66.7

ns

• IRQ, NMI (edge trigger)

• IRQ (level trigger)

28 DMA Requests Rate

12T_C

100.0 ns

6T_C

—

50.0

ns

• Data read from HDI08, ESAI, ESAI_1, SHI,

DAX

• Data write to HDI08, ESAI, ESAI_1, SHI, DAX

• Timer

7T_C

2T_C

3T_C

58.0

16.7

25.0

• IRQ, NMI (edge trigger)

—

ns

2-10

DSP56366 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (continued)

No.

Characteristics

Expression

Min Max Unit

37.4 ns

29 Delay from IRQA, IRQB, IRQC, IRQD, NMI

assertion to external memory (DMA source)

access address out valid

4.25 × T_C+ 2.0

—

Notes: 1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19

through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted

Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended

when using Level-sensitive mode.

2. This timing depends on several settings:

For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery

time will be defined by the PCTL Bit 17 and OMR Bit 6 settings.

For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the

PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to

1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end

when the last of these two events occurs: the stop delay counter completes count or PLL lock procedure

completion.

PLC value for PLL disable is 0.

The maximum value for ET_Cis 4096 (maximum MF) divided by the desired internal frequency (i.e., for

120 MHz it is 4096/120 MHz = 34.1 µs). During the stabilization period, T_C, T_H,and T_Lwill not be

constant, and their width may vary, so timing may vary as well.

3. Periodically sampled and not 100% tested

4. RESET duration is measured during the time in which RESET is asserted, V_CCis valid, and the EXTAL

input is active and valid. When the V_CCis valid, but the other “required RESET duration” conditions (as

specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result

in significant power consumption and heat-up. Designs should minimize this state to the shortest

possible duration.

5. If PLL does not lose lock

6. V_CC= 3.3 V ± 0.16 V; T_J= –40°C to + 105°C, C_L= 50 pF

7. WS = number of wait states (measured in clock cycles, number of T_C). Use expression to compute

maximum value.

MOTOROLA

DSP56366 Advance Information

2-11

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

V_IH

RESET

9

10

8

All Pins

A0–A17

Reset Value

First Fetch

AA0460

Figure 2-2 Reset Timing

First Interrupt Instruction

A0–A17

Execution/Fetch

RD

20

WR

21

19

17

IRQA, IRQB,

IRQC, IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA, IRQB,

IRQC, IRQD,

NMI

b) General Purpose I/O

Figure 2-3 External Fast Interrupt Timing

2-12

DSP56366 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

IRQA, IRQB,

IRQC, IRQD,

NMI

15

IRQA, IRQB,

IRQC, IRQD,

NMI

16

AA0463

Figure 2-4 External Interrupt Timing (Negative Edge-Triggered)

V_IH

RESET

13

14

V_IH

V_IL

V_IH

V_IL

IRQA, IRQB,

IRQD, NMI

MODA, MODB,

MODC, MODD,

PINIT

AA0465

Figure 2-5 Operating Mode Select Timing

24

IRQA

25

First Instruction Fetch

A0–A17

AA0466

Figure 2-6 Recovery from Stop State Using IRQA

MOTOROLA

DSP56366 Advance Information

2-13

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

26

IRQA

25

First IRQA Interrupt

Instruction Fetch

A0–A17

AA0467

Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A0–A17

RD

WR

29

IRQA, IRQB,

IRQC, IRQD,

NMI

First Interrupt Instruction Execution

AA1104

Figure 2-8 External Memory Access (DMA Source) Timing

2-14

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

2.10 EXTERNAL MEMORY EXPANSION PORT (PORT A)

2.10.1 SRAM Timing

3

Table 2-8 SRAM Read and Write Accesses

1

No.

Characteristics

Symbol

Min Max Unit

Expression

100 Address valid and AA assertion pulse width t_RC, t_WC

(WS + 1) × T_C− 4.0

[1 ≤ WS ≤ 3]

12.0

46.0

87.0

0.1

—

ns

(WS + 2) × T_C− 4.0

[4 ≤ WS ≤ 7]

(WS + 3) × T_C− 4.0

[WS ≥ 8]

101 Address and AA valid to WR assertion

102 WR assertion pulse width

t_AS

0.25 × T_C− 2.0

[WS = 1]

1.25 × T_C− 2.0

[WS ≥ 4]

8.4

t_WP

1.5 × T_C− 4.0 [WS = 1] 8.5

—

ns

All frequencies:

WS × T_C− 4.0

[2 ≤ WS ≤ 3]

12.7

(WS − 0.5) × T_C− 4.0 25.2

[WS ≥ 4]

—

ns

103 WR deassertion to address not valid

t_WR

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

0.1

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

8.4

2.25 × T_C− 2.0

[WS ≥ 8]

16.7

6.4

All frequencies:

1.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

2.25 × T_C− 4.0

[WS ≥ 8]

14.7

—

ns

104 Address and AA valid to input data valid

t_AA, t_AC(WS + 0.75) × T_C− 7.0

[WS ≥ 1]

7.6

MOTOROLA

DSP56366 Advance Information

2-15

Specifications

External Memory Expansion Port (Port A)

3

Table 2-8 SRAM Read and Write Accesses (continued)

1

No.

Characteristics

Symbol

Min Max Unit

Expression

105 RD assertion to input data valid

t_OE

(WS + 0.25) × T_C− 7.0

[WS ≥ 1]

—

3.4

—

ns

106 RD deassertion to data not valid (data hold

time)

t_OHZ

0.0

107 Address valid to WR deassertion²

t_AW

(WS + 0.75) × T_C− 4.0 10.6

[WS ≥ 1]

—

108 Data valid to WR deassertion (data setup

time)

t_DS(t_DW) (WS − 0.25) × T_C− 3.0 3.2

[WS ≥ 1]

—

109

110

Data hold time from WR deassertion

t_DH

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

0.1

8.4

16.7

2.5

0.0

—

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

—

2.25 × T_C− 2.0

[WS ≥ 8]

—

WR assertion to data active

—

0.75 × T_C− 3.7

—

[WS = 1]

0.25 × T_C− 3.7

[2 ≤ WS ≤ 3]

—

−0.25 × T_C− 3.7

[WS ≥ 4]

—

111 WR deassertion to data high impedance

—

0.25 × T_C+ 0.2

[1 ≤ WS ≤ 3]

2.3

10.6

18.9

—

ns

1.25 × T_C+ 0.2

[4 ≤ WS ≤ 7]

—

2.25 × T_C+ 0.2

[WS ≥ 8]

—

112

Previous RD deassertion to data active

(write)

—

1.25 × T_C− 4.0

[1 ≤ WS ≤ 3]

6.4

14.7

23.1

2.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

—

3.25 × T_C− 4.0

[WS ≥ 8]

—

2-16

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

3

Table 2-8 SRAM Read and Write Accesses (continued)

1

No.

Characteristics

Symbol

Min Max Unit

Expression

113 RD deassertion time

0.75 × T_C− 4.0

[1 ≤ WS ≤ 3]

2.2

10.6

18.9

0.2

—

ns

1.75 × T_C− 4.0

[4 ≤ WS ≤ 7]

2.75 × T_C− 4.0

[WS ≥ 8]

114 WR deassertion time

0.5 × T_C− 4.0

[WS = 1]

T_C− 2.0

[2 ≤ WS ≤ 3]

6.3

2.5 × T_C− 4.0

[4 ≤ WS ≤ 7]

16.8

25.2

0.2

3.5 × T_C− 4.0

[WS ≥ 8]

115 Address valid to RD assertion

116 RD assertion pulse width

0.5 × T_C− 4.0

—

ns

(WS + 0.25) × T_C−4.0 6.4

117 RD deassertion to address not valid

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

0.1

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

8.4

—

ns

2.25 × T_C− 2.0

[WS ≥ 8]

16.7

118 TA setup before RD or WR deassertion⁴

119 TA hold after RD or WR deassertion

0.25 × T_C+ 2.0

4.1

0.0

—

ns

Notes: 1. WS is the number of wait states specified in the BCR.

2. Timings 100, 107 are guaranteed by design, not tested.

3. All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc

4. In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to

remain active

MOTOROLA

DSP56366 Advance Information

2-17

Specifications

External Memory Expansion Port (Port A)

100

A0–A17

AA0–AA2

117

106

113

116

RD

115

105

WR

104

119

118

TA

Data

In

D0–D23

AA0468

Figure 2-9 SRAM Read Access

100

A0–A17

AA0–AA2

107

101

102

103

WR

114

RD

TA

118

119

108

109

Data

Out

D0–D23

Figure 2-10 SRAM Write Access

DSP56366 Advance Information

2-18

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

2.10.2 DRAM Timing

The selection guides provided in Figure 2-11 and Figure 2-14 should be used for primary selection only.

Final selection should be based on the timing provided in the following tables. As an example, the

selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode

DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate

whether fewer wait states might be used by determining which timing prevents operation at 100 MHz,

running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available),

and control factors such as capacitive and resistive load to improve overall system performance.

DRAM Type

(tRAC ns)

Note: This figure should be use for primary selection.

For exact and detailed timings see the

following tables.

100

80

70

60

50

Chip Frequency

(MHz)

120

40

66

80

100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

AA047

Figure 2-11 DRAM Page Mode Wait States Selection Guide

MOTOROLA

DSP56366 Advance Information

2-19

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)

6

20 MHz

30 MHz

No.

Characteristics

SymbolExpression

Unit

Min Max Min Max

131 Page mode cycle time for

two consecutive accesses

of the same direction

t_PC

2 × T_C

100.0

62.5

—

66.7

41.7

—

ns

Page mode cycle time for

mixed (read and write)

accesses

1.25 × T_C

132 CAS assertion to data valid

(read)

t_CAC

T_C− 7.5

—

42.5

67.5

—

25.8

42.5

—

ns

133 Column address valid to

data valid (read)

t_AA

1.5 × T_C− 7.5

134 CAS deassertion to data not

valid (read hold time)

t_OFF

t_RSH

t_RHCP

0.0

135 Last CAS assertion to RAS

deassertion

0.75 × T_C− 4.0 33.5

—

21.0

62.7

—

136 Previous CAS deassertion

to RAS deassertion

2 × T_C− 4.0

96.0

—

137 CAS assertion pulse width

t_CAS

t_CRP

0.75 × T_C− 4.0 33.5

1.75 × T_C− 6.0 81.5

—

21.0

52.3

—

ns

138 Last CAS deassertion to

RAS deassertion⁴

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

3.25 × T_C− 6.0 156.5

4.25 × T_C− 6.0 206.5

6.25 × T_C– 6.0 306.5

102.2

135.5

202.1

12.7

—

ns

—

139 CAS deassertion pulse

width

t_CP

0.5 × T_C− 4.0

21.0

140 Column address valid to

CAS assertion

t_ASC

0.5 × T_C− 4.0

21.0

—

12.7

21.0

—

ns

141 CAS assertion to column

address not valid

t_CAH

0.75 × T_C− 4.0 33.5

2-20

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)

6

20 MHz

30 MHz

No.

Characteristics

SymbolExpression

Unit

Min Max Min Max

142 Last column address valid

to RAS deassertion

t_RAL

t_RCS

t_RCH

t_WCH

2 × T_C− 4.0

96.0

—

62.7

21.2

4.6

—

ns

143 WR deassertion to CAS

assertion

0.75 × T_C− 3.8 33.7

144 CAS deassertion to WR

assertion

0.25 × T_C− 3.7

0.5 × T_C− 4.2

1.5 × T_C− 4.5

8.8

145 CAS assertion to WR deas-

sertion

20.8

12.5

146 WR assertion pulse width

t_WP

70.5

—

45.5

54.0

—

ns

147 Last WR assertion to RAS

deassertion

t_RWL

1.75 × T_C− 4.3 83.2

148 WR assertion to CAS deas-

sertion

t_CWL

1.75 × T_C− 4.3 83.2

—

54.0

4.3

—

ns

149 Data valid to CAS assertion

(Write)

t_DS

0.25 × T_C− 4.0

8.5

150 CAS assertion to data not

valid (write)

t_DH

0.75 × T_C− 4.0 33.5

21.0

29.0

46.0

151 WR assertion to CAS asser-

tion

t_WCS

T_C− 4.3

1.5 × T_C− 4.0

T_C− 7.5

45.7

71.0

152 Last RD assertion to RAS

deassertion

t_ROH

153 RD assertion to data valid

t_GA

t_GZ

—

42.5

—

25.8

—

ns

154 RD deassertion to data not

valid ⁵

0.0

155 WR assertion to data active

0.75 × T_C− 0.3 37.2

0.25 × T_C

—

24.7

—

ns

156 WR deassertion to data high

impedance

—

12.5

8.3

MOTOROLA

DSP56366 Advance Information

2-21

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)

6

20 MHz

30 MHz

No.

Characteristics

SymbolExpression

Unit

Min Max Min Max

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,

t_PCequals 2 × T_Cfor read-after-read or write-after-write sequences).

4. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of-page access.

5. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ

.

6. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 2-14.).

1, 2, 3, 7

Table 2-10 DRAM Page Mode Timings, Two Wait States

66 MHz

80 MHz

No.

Characteristics

SymbolExpression

Unit

Min Max Min Max

131 Page mode cycle time for

two consecutive accesses

of the same direction

t_PC

2 × T_C

45.4

41.1

—

37.5

34.4

—

ns

Page mode cycle time for

mixed (read and write)

accesses

1.25 × T_C

132 CAS assertion to data valid

(read)

t_CAC

1.5 × T_C− 7.5

1.5 × T_C− 6.5

2.5 × T_C− 7.5

2.5 × T_C− 6.5

—

15.2

—

12.3

—

ns

133 Column address valid to

data valid (read)

t_AA

—

30.4

—

24.8

—

134 CAS deassertion to data

not valid (read hold time)

t_OFF

0.0

—

0.0

135 Last CAS assertion to RAS

deassertion

t_RSH

1.75 × T_C− 4.0

3.25 × T_C− 4.0

1.5 × T_C− 4.0

22.5

45.2

18.7

—

17.9

36.6

14.8

—

ns

136 Previous CAS deassertion

to RAS deassertion

t_RHCP

137 CAS assertion pulse width

t_CAS

2-22

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2, 3, 7

Table 2-10 DRAM Page Mode Timings, Two Wait States

(continued)

80 MHz

66 MHz

No.

Characteristics

SymbolExpression

Unit

Min Max Min Max

138 Last CAS deassertion to

RAS deassertion⁵

t_CRP

2.0 × T_C− 6.0

24.4

—

19.0

—

ns

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

3.5 × T_C− 6.0

4.5 × T_C− 6.0

6.5 × T_C− 6.0

1.25 × T_C− 4.0

47.2

62.4

92.8

14.9

—

37.8

50.3

75.3

11.6

—

ns

139 CAS deassertion pulse

width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

140 Column address valid to

CAS assertion

T_C− 4.0

11.2

22.5

41.5

15.1

3.9

—

8.5

17.9

33.5

11.8

2.6

—

ns

141 CAS assertion to column

address not valid

1.75 × T_C− 4.0

3 × T_C− 4.0

142 Last column address valid

to RAS deassertion

143 WR deassertion to CAS

assertion

1.25 × T_C− 3.8

0.5 × T_C− 3.7

1.5 × T_C− 4.2

144 CAS deassertion to WR

assertion

145 CAS assertion to WR deas-

sertion

18.5

14.6

146 WR assertion pulse width

t_WP

2.5 × T_C− 4.5

2.75 × T_C− 4.3

33.5

33.4

—

26.8

—

ns

147 Last WR assertion to RAS

deassertion

t_RWL

148 WR assertion to CAS deas-

sertion

t_CWL

2.5 × T_C− 4.3

33.6

—

27.0

—

ns

149 Data valid to CAS assertion

(write)

t_DS

0.25 × T_C− 3.7

0.25 × T_C− 3.0

1.75 × T_C− 4.0

0.1

—

0.1

—

ns

150 CAS assertion to data not

valid (write)

t_DH

22.5

17.9

MOTOROLA

DSP56366 Advance Information

2-23

Specifications

External Memory Expansion Port (Port A)

1, 2, 3, 7

Table 2-10 DRAM Page Mode Timings, Two Wait States

(continued)

80 MHz

66 MHz

No.

Characteristics

SymbolExpression

Unit

Min Max Min Max

151 WR assertion to CAS

assertion

t_WCS

t_ROH

t_GA

T_C− 4.3

10.9

—

8.2

—

ns

152 Last RD assertion to RAS

deassertion

2.5 × T_C− 4.0

33.9

—

27.3

—

153 RD assertion to data valid

1.75 × T_C− 7.5

1.75 × T_C− 6.5

—

19.0

—

15.4

—

ns

154 RD deassertion to data not

valid⁶

t_GZ

0.0

—

0.0

155 WR assertion to data active

0.75 × T_C− 0.3

0.25 × T_C

11.1

—

9.1

—

ns

156 WR deassertion to data

high impedance

3.8

3.1

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56366.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,

t_PCequals 3 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in

each DRAM out-of-page access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ.

7. There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Figure 2-11)

2-24

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-11 DRAM Page Mode Timings, Three Wait States

No.

Characteristics

SymbolExpression Min Max Unit

131 Page mode cycle time for two consecutive

accesses of the same direction

t_PC

2 × T_C

40.0

—

ns

Page mode cycle time for mixed (read and write)

accesses

1.25 × T_C

35.0

—

132 CAS assertion to data valid (read)

t_CAC

t_AA

2 × T_C− 7.0

3 × T_C− 7.0

—

13.0

23.0

—

ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t_OFF

t_RSH

t_RHCP

t_CAS

t_CRP

0.0

2.5 × T_C− 4.0 21.0

4.5 × T_C− 4.0 41.0

2 × T_C− 4.0 16.0

—

138 Last CAS deassertion to RAS assertion⁵

• BRW[1:0] = 00

2.25 × T_C− 6.0

—

• BRW[1:0] = 01

3.75 × T_C− 6.0

—

ns

• BRW[1:0] = 10

4.75 × T_C− 6.0 41.5

6.75 × T_C− 6.0 61.5

1.5 × T_C− 4.0 11.0

• BRW[1:0] = 11

139 CAS deassertion pulse width

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

T_C− 4.0

6.0

2.5 × T_C− 4.0 21.0

4 × T_C− 4.0 36.0

1.25 × T_C− 4.0 8.5

0.75 × T_C− 4.0 3.5

2.25 × T_C− 4.2 18.3

3.5 × T_C− 4.5 30.5

3.75 × T_C− 4.3 33.2

3.25 × T_C− 4.3 28.2

0.5 × T_C− 4.0 1.0

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

t_RWL

t_CWL

t_DS

MOTOROLA

DSP56366 Advance Information

2-25

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-11 DRAM Page Mode Timings, Three Wait States

(continued)

No.

Characteristics

SymbolExpression Min Max Unit

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_DH

t_WCS

t_ROH

t_GA

2.5 × T_C− 4.0 21.0

1.25 × T_C− 4.3 8.2

3.5 × T_C− 4.0 31.0

—

ns

—

2.5 × T_C− 7.0

—

18.0

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3 7.2

0.25 × T_C

—

156 WR deassertion to data high impedance

—

2.5

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56366.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,

t_PCequals 4 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in

each DRAM out-of page-access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

2-26

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-12 DRAM Page Mode Timings, Four Wait States

No.

Characteristics

SymbolExpression Min Max Unit

131 Page mode cycle time for two consecutive

accesses of the same direction.

t_PC

5 × T_C

41.7

—

ns

Page mode cycle time for mixed (read and write)

accesses

4.5 × T_C

37.5

—

132 CAS assertion to data valid (read)

t_CAC

t_AA

2.75 × T_C− 7.0

3.75 × T_C− 7.0

—

15.9

24.2

—

ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t_OFF

t_RSH

t_RHCP

t_CAS

t_CRP

0.0

3.5 × T_C− 4.0 25.2

6 × T_C− 4.0 46.0

2.5 × T_C− 4.0 16.8

—

138 Last CAS deassertion to RAS assertion⁵

• BRW[1:0] = 00

2.75 × T_C− 6.0

—

• BRW[1:0] = 01

4.25 × T_C− 6.0

—

• BRW[1:0] = 10

5.25 × T_C− 6.0 37.7

7.25 × T_C− 6.0 54.4

• BRW[1:0] = 11

139 CAS deassertion pulse width

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

2 × T_C− 4.0

T_C− 4.0

12.7

4.3

ns

3.5 × T_C− 4.0 25.2

5 × T_C− 4.0 37.7

1.25 × T_C− 4.0 6.4

3.25 × T_C− 4.2 22.9

4.5 × T_C− 4.5 33.0

4.75 × T_C− 4.3 35.3

3.75 × T_C− 4.3 26.9

0.5 × T_C− 4.0 0.2

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

t_RWL

t_CWL

t_DS

MOTOROLA

DSP56366 Advance Information

2-27

Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-12 DRAM Page Mode Timings, Four Wait States

(continued)

No.

Characteristics

SymbolExpression Min Max Unit

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_DH

t_WCS

t_ROH

t_GA

3.5 × T_C− 4.0 25.2

1.25 × T_C− 4.3 6.1

4.5 × T_C− 4.0 33.5

—

ns

—

3.25 × T_C− 7.0

—

20.1

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3 5.9

0.25 × T_C

—

156 WR deassertion to data high impedance

—

2.1

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56366.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,

t_PCequals 3 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of-page access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ

.

2-28

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

RAS

CAS

136

131

135

137

139

141

138

140

151

142

Column

Address

Last Column

Address

Column

Address

Row

Add

A0–A17

144

143

145

147

WR

RD

146

148

155

149

156

150

D0–D23

Data Out

AA0473

Figure 2-12 DRAM Page Mode Write Accesses

MOTOROLA

DSP56366 Advance Information

2-29

Specifications

External Memory Expansion Port (Port A)

RAS

136

135

131

CAS

137

140

139

141

138

142

Row

Add

Last Column

Address

Column

Address

Column

Address

A0–A17

WR

143

132

133

153

152

RD

134

154

D0–D23

Data In

AA0474

Figure 2-13 DRAM Page Mode Read Accesses

2-30

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

DRAM Type

(tRAC ns)

Note: This figure should be use for primary selection. For

exact and detailed timings see the following tables.

100

80

70

60

Chip Frequency

(MHz)

50

120

40 66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

AA0475

Figure 2-14 DRAM Out-of-Page Wait States Selection Guide

1, 2

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

4

20 MHz

30 MHz

3

No.

SymbolExpression

Unit

Characteristics

Min Max Min Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

t_RC

t_RAC

t_CAC

t_AA

5 × T_C

250.0

—

166.7

—

ns

2.75 × T_C− 7.5

1.25 × T_C− 7.5

1.5 × T_C− 7.5

130.0

55.0

67.5

84.2

34.2

42.5

—

160 Column address valid to data valid

(read)

—

161 CAS deassertion to data not valid

(read hold time)

t_OFF

0.0

—

0.0

—

ns

162 RAS deassertion to RAS assertion

t_RP

1.75 × T_C− 4.0

83.5

54.3

MOTOROLA

DSP56366 Advance Information

2-31

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

(continued)

4

20 MHz

30 MHz

3

No.

SymbolExpression

Unit

Characteristics

Min Max Min Max

163 RAS assertion pulse width

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

3.25 × T_C− 4.0 158.5

1.75 × T_C− 4.0 83.5

2.75 × T_C− 4.0 133.5

—

104.3

54.3

87.7

37.7

48.0

39.7

—

ns

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

1.25 × T_C− 4.0

1.5 × T_C± 2

58.5

73.0

60.5

—

167 RAS assertion to CAS assertion

77.0

64.5

52.0

43.7

168 RAS assertion to column address

valid

1.25 × T_C± 2

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

t_CRP

t_CP

2.25 × T_C− 4.0 108.5

—

71.0

54.3

—

ns

1.75 × T_C− 4.0

83.5

171 Row address valid to RAS asser-

tion

t_ASR

172 RAS assertion to row address not

valid

t_RAH

t_ASC

t_CAH

t_AR

1.25 × T_C− 4.0

0.25 × T_C− 4.0

1.75 × T_C− 4.0

58.5

8.5

—

37.7

4.3

—

ns

173 Column address valid to CAS

assertion

174 CAS assertion to column address

not valid

83.5

54.3

104.3

62.7

175 RAS assertion to column address

not valid

3.25 × T_C− 4.0 158.5

176 Column address valid to RAS

deassertion

t_RAL

2 × T_C− 4.0

96.0

177 WR deassertion to CAS assertion

178 CAS deassertion to WR assertion

179 RAS deassertion to WR assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

1.5 × T_C− 3.8

0.75 × T_C− 3.7

0.25 × T_C− 3.7

1.5 × T_C− 4.2

3 × T_C− 4.2

71.2

33.8

8.8

—

46.2

21.3

4.6

—

ns

70.8

145.8

220.5

45.8

95.8

145.5

4.5 × T_C− 4.5

2-32

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

(continued)

4

20 MHz

30 MHz

3

No.

SymbolExpression

Unit

Characteristics

Min Max Min Max

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

t_RWL

t_CWL

t_DS

4.75 × T_C− 4.3 233.2

—

154.0

137.4

71.0

—

ns

4.25 × T_C− 4.3 208.2

2.25 × T_C− 4.0 108.5

186 CAS assertion to data not valid

(write)

t_DH

1.75 × T_C− 4.0

83.5

54.3

187 RAS assertion to data not valid

(write)

t_DHR

3.25 × T_C− 4.0 158.5

—

104.3

—

ns

188 WR assertion to CAS assertion

t_WCS

t_CSR

3 × T_C− 4.3

145.7

21.0

—

95.7

12.7

—

ns

189 CAS assertion to RAS assertion

(refresh)

0.5 × T_C− 4.0

190 RAS deassertion to CAS assertion

(refresh)

t_RPC

1.25 × T_C− 4.0

58.5

—

37.7

—

ns

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t_ROH

t_GA

4.5 × T_C− 4.0

4 × T_C− 7.5

221.0

—

192.5

—

146.0

—

125.8

—

ns

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3

0.25 × T_C

37.2

—

24.7

—

195 WR deassertion to data high

impedance

12.5

8.3

Notes: 1. The number of wait states for out of page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

4. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See

Figure 2-17.).

MOTOROLA

DSP56366 Advance Information

2-33

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

80 MHz

Min Max Min Max

66 MHz

4

3

No.

Symbol

Unit

Characteristics

Expression

157 Random read or write cycle time

t_RC

9 × T_C

136.4

—

64.5

—

112.5

—

ns

158 RAS assertion to data valid

(read)

t_RAC

4.75 × T_C− 7.5

4.75 × T_C− 6.5

2.25 × T_C− 7.5

2.25 × T_C− 6.5

3 × T_C− 7.5

—

52.9

—

159 CAS assertion to data valid

(read)

t_CAC

—

26.6

—

21.6

—

160 Column address valid to data

valid (read)

t_AA

—

40.0

—

3 × T_C− 6.5

—

31.0

—

161 CAS deassertion to data not

valid (read hold time)

t_OFF

0.0

—

0.0

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

3.25 × T_C− 4.0 45.2

5.75 × T_C− 4.0 83.1

3.25 × T_C− 4.0 45.2

4.75 × T_C− 4.0 68.0

2.25 × T_C− 4.0 30.1

—

36.6

67.9

36.6

55.5

24.1

29.3

19.9

—

ns

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

2.5 × T_C± 2

35.9

24.5

39.9

28.5

33.3

23.9

168 RAS assertion to column

address valid

1.75 × T_C± 2

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

t_CRP

t_CP

4.25 × T_C− 4.0 59.8

2.75 × T_C− 4.0 37.7

3.25 × T_C− 4.0 45.2

—

49.1

30.4

36.6

—

ns

171 Row address valid to RAS

assertion

t_ASR

172 RAS assertion to row address

not valid

t_RAH

1.75 × T_C− 4.0 22.5

—

17.9

5.4

—

ns

173 Column address valid to CAS

assertion

t_ASC

0.75 × T_C− 4.0

7.4

2-34

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

66 MHz

(continued)

80 MHz

4

3

No.

Symbol

Unit

Characteristics

Expression

Min Max Min Max

174 CAS assertion to column

address not valid

t_CAH

3.25 × T_C− 4.0 45.2

—

36.6

67.9

46.0

—

ns

175 RAS assertion to column

address not valid

t_AR

5.75 × T_C− 4.0 83.1

176 Column address valid to RAS

deassertion

t_RAL

4 × T_C− 4.0

2 × T_C− 3.8

56.6

26.5

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁵assertion

179 RAS deassertion to WR⁵assertion

t_RCS

t_RCH

t_RRH

—

21.2

11.9

—

ns

1.25 × T_C− 3.7 15.2

0.25 × T_C− 3.7

0.25 × T_C− 3.0

3 × T_C− 4.2

0.1

—

0.1

180 CAS assertion to WR deasser-

tion

t_WCH

41.3

33.3

181 RAS assertion to WR deasser-

tion

t_WCR

5.5 × T_C− 4.2

79.1

—

64.6

—

ns

182 WR assertion pulse width

t_WP

8.5 × T_C− 4.5 124.3

8.75 × T_C− 4.3 128.3

—

101.8

105.1

—

ns

183 WR assertion to RAS deasser-

tion

t_RWL

184 WR assertion to CAS deasser-

tion

t_CWL

7.75 × T_C− 4.3 113.1

4.75 × T_C− 4.0 68.0

3.25 × T_C− 4.0 45.2

5.75 × T_C− 4.0 83.1

—

92.6

55.4

36.6

67.9

—

ns

185 Data valid to CAS assertion

(write)

t_DS

186 CAS assertion to data not valid

(write)

t_DH

187 RAS assertion to data not valid

(write)

t_DHR

188 WR assertion to CAS assertion

t_WCS

t_CSR

5.5 × T_C− 4.3

1.5 × T_C− 4.0

79.0

18.7

—

64.5

14.8

—

ns

189 CAS assertion to RAS assertion

(refresh)

190 RAS deassertion to CAS assertion

(refresh)

t_RPC

1.75 × T_C− 4.0 22.5

—

17.9

—

ns

MOTOROLA

DSP56366 Advance Information

2-35

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

(continued)

66 MHz

80 MHz

4

3

No.

Symbol

Unit

Characteristics

Expression

Min Max Min Max

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t_ROH

t_GA

8.5 × T_C− 4.0 124.8

—

106.1

—

102.3

—

ns

7.5 × T_C− 7.5

7.5 × T_C− 6.5

0.0

—

87.3

—

193 RD deassertion to data not

valid⁴

t_GZ

0.0

—

0.0

194 WR assertion to data active

0.75 × T_C− 0.3 11.1

0.25 × T_C

—

9.1

—

ns

195 WR deassertion to data high

impedance

—

3.8

3.1

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56366.

4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

5. Either t_RCHor t_RRHmust be satisfied for read cycles.

.

1, 2

Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States

4

3

No.

Symbol

Min Max Unit

Characteristics

Expression

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

t_RC

t_RAC

t_CAC

t_AA

12 × T_C

120.0

—

ns

6.25 × T_C− 7.0

3.75 × T_C− 7.0

4.5 × T_C− 7.0

55.5

30.5

38.0

—

161 CAS deassertion to data not valid (read hold

time)

t_OFF

0.0

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

4.25 × T_C− 4.0 38.5

7.75 × T_C− 4.0 73.5

5.25 × T_C− 4.0 48.5

6.25 × T_C− 4.0 58.5

3.75 × T_C− 4.0 33.5

—

ns

t_RAS

t_RSH

t_CSH

t_CAS

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

2-36

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States

(continued)

4

3

No.

167 RAS assertion to CAS assertion

Symbol

Min Max Unit

Characteristics

Expression

t_RCD

t_RAD

t_CRP

t_CP

2.5 × T_C± 4.0

21.0

29.0

21.5

—

ns

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

1.75 × T_C± 4.0 13.5

5.75 × T_C− 4.0 53.5

4.25 × T_C− 4.0 38.5

1.75 × T_C− 4.0 13.5

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁵assertion

179 RAS deassertion to WR⁵assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

0.75 × T_C− 4.0

3.5

5.25 × T_C− 4.0 48.5

7.75 × T_C− 4.0 73.5

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

6 × T_C− 4.0

56.0

26.0

3.0 × T_C− 4.0

1.75 × T_C− 4.0 13.5

0.25 × T_C− 2.0

5 × T_C− 4.2

0.5

45.8

70.8

7.5 × T_C− 4.2

11.5 × T_C− 4.5 110.5

11.75 × T_C− 4.3 113.2

10.25 × T_C− 4.3 103.2

5.75 × T_C− 4.0 53.5

5.25 × T_C− 4.0 48.5

7.75 × T_C− 4.0 73.5

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

t_DH

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

6.5 × T_C− 4.3

1.5 × T_C− 4.0

60.7

11.0

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

2.75 × T_C− 4.0 23.5

11.5 × T_C− 4.0 111.0

MOTOROLA

DSP56366 Advance Information

2-37

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States

(continued)

4

3

No.

192 RD assertion to data valid

Symbol

Min Max Unit

Characteristics

Expression

t_GA

t_GZ

10 × T_C− 7.0

—

0.0

7.2

—

93.0

—

ns

193 RD deassertion to data not valid⁴

194 WR assertion to data active

0.75 × T_C− 0.3

0.25 × T_C

—

195 WR deassertion to data high impedance

2.5

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56366.

4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

5. Either t_RCHor t_RRHmust be satisfied for read cycles.

.

1, 2

Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

3

No.

SymbolExpression

Min Max Unit

Characteristics

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

t_RC

t_RAC

t_CAC

t_AA

16 × T_C

133.3

—

ns

8.25 × T_C− 5.7

4.75 × T_C− 5.7

5.5 × T_C− 5.7

0.0

63.0

33.9

40.1

—

161 CAS deassertion to data not valid (read hold

time)

t_OFF

0.0

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RP

6.25 × T_C− 4.0

9.75 × T_C− 4.0

6.25 × T_C− 4.0

8.25 × T_C− 4.0

4.75 × T_C− 4.0

3.5 × T_C± 2

48.1

77.2

48.1

64.7

35.6

27.2

20.9

60.6

48.1

18.9

—

ns

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

31.2

24.9

—

2.75 × T_C± 2

7.75 × T_C− 4.0

6.25 × T_C− 4.0

2.75 × T_C− 4.0

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

t_ASR

t_RAH

—

2-38

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

(continued)

3

No.

SymbolExpression

Min Max Unit

Characteristics

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁵assertion

179 RAS deassertion to WR⁵assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASC

t_CAH

t_AR

0.75 × T_C− 4.0

2.2

48.1

77.2

54.3

37.9

10.9

0.1

—

ns

6.25 × T_C− 4.0

9.75 × T_C− 4.0

7 × T_C− 4.0

—

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

—

5 × T_C− 3.8

—

1.75 × T_C− 3.7

0.25 × T_C− 2.0

6 × T_C− 4.2

—

45.8

75.0

124.7

—

9.5 × T_C− 4.2

15.5 × T_C− 4.5

—

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

15.75 × T_C− 4.3 126.9

14.25 × T_C− 4.3 114.4

—

8.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

9.5 × T_C− 4.3

1.5 × T_C− 4.0

4.75 × T_C− 4.0

15.5 × T_C− 4.0

14 × T_C− 5.7

68.9

48.1

77.2

74.9

8.5

—

t_DH

—

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

—

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

—

35.6

125.2

—

111.0

—

193 RD deassertion to data not valid³

194 WR assertion to data active

t_GZ

0.0

0.75 × T_C− 0.3

0.25 × T_C

5.9

—

195 WR deassertion to data high impedance

—

2.1

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not

t_GZ

4. Either t_RCHor t_RRHmust be satisfied for read cycles.

.

MOTOROLA

DSP56366 Advance Information

2-39

Specifications

External Memory Expansion Port (Port A)

157

164

162

163

165

162

RAS

167

168

169

170

166

CAS

171

173

174

175

Row Address

Column Address

A0–A17

172

176

177

179

191

WR

RD

168

160

159

193

161

158

192

Data

In

D0–D23

AA0476

Figure 2-15 DRAM Out-of-Page Read Access

2-40

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

157

162

163

165

162

RAS

167

168

164

169

166

170

CAS

171

173

172

174

176

Row Address

Column Address

A0–A17

181

175

188

180

182

WR

RD

184

183

187

186

185

195

194

Data Out

D0–D23

AA0477

Figure 2-16 DRAM Out-of-Page Write Access

MOTOROLA

DSP56366 Advance Information

2-41

Specifications

External Memory Expansion Port (Port A)

157

162

163

165

162

RAS

190

170

CAS

189

177

WR

AA0478

Figure 2-17 DRAM Refresh Access

2.10.3 Arbitration Timings

Table 2-17 Asynchronous Bus Arbitration timing

120 MHz

No.

Characteristics

Expression

Unit

Min

Max

250

251

BB assertion window from BG input negation.

Delay from BB assertion to BG assertion

2 .5* Tc + 5

2 * Tc + 5

—

25.8

—

ns

21.7

Comments:

1. Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode

2. If Asynchronous Arbitration mode is active, none of the timings in Table 2-17 is required.

3. In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300

devices (on the same bus) in a non overlap manner as shown in Figure 2-18.

2-42

DSP56366 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

BG1

BB

250

BG2

251

Figure 2-18 Asynchronous Bus Arbitration Timing

BG1

BG2

250+251

Figure 2-19 Asynchronous Bus Arbitration Timing

Background explanation for Asynchronous Bus Arbitration:

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs.

These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a

result of this delay, a 56300 part may assume mastership and assert BB for some time after BG is

negated. This is the reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is

exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted

before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to

assume mastership at the same time. Therefore some non-overlap period between one BG input active to

another BG input active is required. Timing 251 ensures that such a situation is avoided.

MOTOROLA

DSP56366 Advance Information

2-43

Specifications

Parallel Host Interface (HDI08) Timing

2.11 PARALLEL HOST INTERFACE (HDI08) TIMING

1, 2

Table 2-18 Host Interface (HDI08) Timing

120 MHz

3

No.

Expression

T_C+ 9.9

—

Unit

ns

Characteristics

Min Max

4

317 Read data strobe assertion width

HACK read assertion width

18.3

—

4

318 Read data strobe deassertion width

HACK read deassertion width

9.9

ns

4

319 Read data strobe deassertion width after “Last Data Regis- 2.5 × T_C+ 6.6 27.4

ns

5,6

ter” reads , or between two consecutive CVR, ICR, or ISR

7

reads

5,6

HACK deassertion width after “Last Data Register” reads

8

320 Write data strobe assertion width

HACK write assertion width

—

13.2

—

ns

321 Write data strobe deassertion width⁸

HACK write deassertion width

2.5 × T_C+ 6.6 27.4

5

• after ICR, CVR and “Last Data Register” writes

• after IVR writes, or

16.5

—

• after TXH:TXM writes (with HBE=0), or

• after TXL:TXM writes (with HBE=1)

322 HAS assertion width

—

9.9

0.0

9.9

—

ns

9

323 HAS deassertion to data strobe assertion

324 Host data input setup time before write data strobe

8

deassertion

Host data input setup time before HACK write deassertion

325 Host data input hold time after write data strobe

—

3.3

—

ns

8

deassertion

Host data input hold time after HACK write deassertion

326 Read data strobe assertion to output data active from high

4

impedance

HACK read assertion to output data active from high imped-

ance

2-44

DSP56366 Advance Information

MOTOROLA

Specifications

Parallel Host Interface (HDI08) Timing

1, 2

Table 2-18 Host Interface (HDI08) Timing

(continued)

120 MHz

3

No.

Expression

Unit

ns

Characteristics

Min Max

4

327 Read data strobe assertion to output data valid

HACK read assertion to output data valid

—

24.2

328 Read data strobe deassertion to output data high

—

9.9

ns

4

impedance

HACK read deassertion to output data high impedance

4

329 Output data hold time after read data strobe deassertion

Output data hold time after HACK read deassertion

—

3.3

—

ns

4

330 HCS assertion to read data strobe deassertion

T_C+9.9

—

18.2

9.9

—

ns

8

331 HCS assertion to write data strobe deassertion

332 HCS assertion to output data valid

—

19.1

—

9

333 HCS hold time after data strobe deassertion

—

0.0

4.7

334 Address (AD7–AD0) setup time before HAS deassertion

(HMUX=1)

—

335 Address (AD7–AD0) hold time after HAS deassertion

(HMUX=1)

—

3.3

0

—

ns

336 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time

9

before data strobe assertion

• Read

• Write

4.7

3.3

—

337 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time

—

T_C

ns

9

after data strobe deassertion

338 Delay from read data strobe deassertion to host request

8.3

16.7

—

4, 5, 10

assertion for “Last Data Register” read

339 Delay from write data strobe deassertion to host request

2 × T_C

—

5, 8, 10

assertion for “Last Data Register” write

340 Delay from data strobe assertion to host request deasser-

19.1

5, 9, 10

tion for “Last Data Register” read or write (HROD = 0)

341 Delay from data strobe assertion to host request deasser-

tion for “Last Data Register” read or write (HROD = 1, open

—

300.0 ns

5, 9, 10, 11

drain Host Request)

MOTOROLA

DSP56366 Advance Information

2-45

Specifications

Parallel Host Interface (HDI08) Timing

1, 2

Table 2-18 Host Interface (HDI08) Timing

(continued)

120 MHz

3

No.

Expression

Unit

Characteristics

Min Max

342 Delay from DMA HACK deassertion to HOREQ assertion

ns

5

• For “Last Data Register” read

2 × T_C+ 19.1 35.8

1.5 × T_C+ 19.1 31.6

0.0

—

5

• For “Last Data Register” write

• For other cases

—

343 Delay from DMA HACK assertion to HOREQ deassertion

—

20.2

ns

5

• HROD = 0

344 Delay from DMA HACK assertion to HOREQ deassertion

for “Last Data Register” read or write

—

300.0 ns

5, 11

• HROD = 1, open drain Host Request

Notes: 1. See Host Port Usage Considerations in the DSP56366 User’s Manual.

2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is

programmable.

3. V_CC= 3.3 V ± 0.16 V; T_J= –40°C to +105°C, C_L= 50 pF

4. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.

5. The “last data register” is the register at address $7, which is the last location to be read or written in

data transfers.

6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL,

RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the

HOREQ signal.

7. This timing is applicable only if two consecutive reads from one of these registers are executed.

8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

9. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data

strobe (HDS) in the single data strobe mode.

10. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host

request mode.

11. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the open-drain mode.

2-46

DSP56366 Advance Information

MOTOROLA

Specifications

Parallel Host Interface (HDI08) Timing

317

318

HACK

328

329

327

326

HD7–HD0

HOREQ

AA1105

Figure 2-20 Host Interrupt Vector Register (IVR) Read Timing Diagram

HA0–HA2

336

337

333

330

HCS

317

HRD, HDS

318

319

328

332

327

329

326

341

HD0–HD7

338

340

HOREQ,

HRRQ,

HTRQ

AA0484

Figure 2-21 Read Timing Diagram, Non-Multiplexed Bus

MOTOROLA

DSP56366 Advance Information

2-47

Specifications

Parallel Host Interface (HDI08) Timing

HA0–HA2

336

337

333

331

HCS

320

HWR, HDS

321

325

324

HD0–HD7

340

339

341

HOREQ, HRRQ, HTRQ

AA0485

Figure 2-22 Write Timing Diagram, Non-Multiplexed Bus

2-48

DSP56366 Advance Information

MOTOROLA

Specifications

Parallel Host Interface (HDI08) Timing

HA8–HA10

336

337

322

HAS

323

317

HRD, HDS

334

318

335

327

319

328

329

HAD0–HAD7

Address

Data

326

338

340

341

HOREQ, HRRQ, HTRQ

AA0486

Figure 2-23 Read Timing Diagram, Multiplexed Bus

MOTOROLA

DSP56366 Advance Information

2-49

Specifications

Parallel Host Interface (HDI08) Timing

HA8–HA10

336

322

HAS

323

320

HWR, HDS

334

324

321

325

335

HAD0–HAD7

Address

Data

340

339

341

HOREQ, HRRQ, HTRQ

AA0487

Figure 2-24 Write Timing Diagram, Multiplexed Bus

HOREQ

(Output)

342

343

344

320

321

TXH/M/L

Write

HACK

(Input)

324

325

Data

Valid

H0–H7

(Input)

Figure 2-25 Host DMA Write Timing Diagram

DSP56366 Advance Information

2-50

MOTOROLA

Specifications

Parallel Host Interface (HDI08) Timing

HOREQ

(Output)

343

342

318

317

HACK

(Input)

RXH

Read

327

326

328

329

H0-H7

(Output)

Data

Valid

Figure 2-26 Host DMA Read Timing Diagram

MOTOROLA

DSP56366 Advance Information

2-51

Specifications

Serial Host Interface SPI Protocol Timing

2.12 SERIAL HOST INTERFACE SPI PROTOCOL TIMING

Table 2-19 Serial Host Interface SPI Protocol Timing

Filter

Mode

1

No.

Mode

Expression

Min Max Unit

Characteristics

140 Tolerable spike width on clock or

data in

—

Bypassed

Narrow

Wide

—

0

50

100

—

ns

—

141 Minimum serial clock cycle =

Master Bypassed

Narrow

6×T_C+46

6×T_C+152

6×T_C+223

96

t

_SPICC(min)

202

273

38

—

Wide

—

142 Serial clock high period

143 Serial clock low period

144 Serial clock rise/fall time

Master Bypassed 0.5×t_SPICC–10

—

Narrow

Wide

0.5×t_SPICC–10

91

—

0.5×t_SPICC–10 126.5

—

Slave Bypassed

Narrow

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

32.8

122.8

209.8

38

—

Wide

—

Master Bypassed 0.5×t_SPICC–10

—

Narrow

Wide

0.5×t_SPICC–10

91

—

0.5×t_SPICC–10 126.5

—

Slave Bypassed

Narrow

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

—

32.8

122.8

209.8

—

Wide

—

Master

Slave

—

10

2000

—

2-52

DSP56366 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

Table 2-19 Serial Host Interface SPI Protocol Timing (continued)

Filter

Mode

1

No.

Mode

Expression

Min Max Unit

Characteristics

146 SS assertion to first SCK edge

CPHA = 0

Slave Bypassed

Narrow

3.5×T_C+15

44.2

0

—

ns

0

Wide

0

CPHA = 1

Slave Bypassed

Narrow

10

0

10

0

—

9

ns

Wide

0

147 Last SCK edge to SS not asserted

Slave Bypassed

Narrow

12

102

189

0

12

102

189

0

Wide

148 Data input valid to SCK edge (data Master/ Bypassed

input set-up time)

Slave

Narrow MAX{(20-T_C), 0} 11.7

Wide MAX{(40-T_C), 0} 31.7

149 SCK last sampling edge to data

input not valid

Master/ Bypassed

2.5×T_C+10

30.8

50.8

70.8

2

Slave

Narrow

2.5×T_C+30

Wide

2.5×T_C+50

150 SS assertion to data out active

Slave

—

2

9

151 SS deassertion to data high

impedance²

—

152 SCK edge to data out valid

(data out delay time)

Master/ Bypassed

2×T_C+33

2×T_C+123

2×T_C+210

T_C+5

—

49.7

139.7

226.7

—

ns

Slave

Narrow

Wide

—

153 SCK edge to data out not valid

(data out hold time)

Master/ Bypassed

13.3

63.3

114.3

Slave

Narrow

T_C+55

—

Wide

T_C+106

—

MOTOROLA

DSP56366 Advance Information

2-53

Specifications

Serial Host Interface SPI Protocol Timing

Table 2-19 Serial Host Interface SPI Protocol Timing (continued)

Filter

Mode

1

No.

Mode

Expression

Min Max Unit

Characteristics

154 SS assertion to data out valid

(CPHA = 0)

Slave

—

T_C+33

—

41.3

ns

157 First SCK sampling edge to HREQ

output deassertion

Slave Bypassed

Narrow

2.5×T_C+30

2.5×T_C+120

2.5×T_C+217

2.5×T_C+30

2.5×T_C+80

2.5×T_C+136

2.5×T_C+30

—

50.8

140.8

237.8

—

ns

Wide

—

158 Last SCK sampling edge to HREQ

output not deasserted (CPHA = 1)

Slave Bypassed

Narrow

50.8

100.8

156.8

50.8

—

Wide

—

159 SS deassertion to HREQ output

not deasserted (CPHA = 0)

Slave

—

160 SS deassertion pulse width (CPHA Slave

= 0)

—

T_C+6

14.3

111.8

164.8

200.3

0

—

ns

161 HREQ in assertion to first SCK

edge

Master Bypassed 0.5 × t_SPICC

2.5×T_C+43

+

Narrow

Wide

—

0.5 ×t_SPICC

2.5×T_C+43

+

0.5 ×t_SPICC

2.5×T_C+43

+

162 HREQ in deassertion to last SCK

sampling edge (HREQ in set-up

time) (CPHA = 1)

Master

0

163 First SCK edge to HREQ in not

asserted

—

0

—

ns

(HREQ in hold time)

Notes: 1. V_CC= 3.16 V ± 0.16 V; T_J= –40°C to +105°C, C_L= 50 pF

2. Periodically sampled, not 100% tested

2-54

DSP56366 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

142

143

144

SCK (CPOL = 0)

(Output)

141

142

SCK (CPOL = 1)

(Output)

148

149

148

149

MISO

(Input)

MSB

Valid

LSB

Valid

153

152

MSB

MOSI

(Output)

LSB

161

163

HREQ

(Input)

AA0271

Figure 2-27 SPI Master Timing (CPHA = 0)

MOTOROLA

DSP56366 Advance Information

2-55

Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

142

141

144

SCK (CPOL = 0)

(Output)

142

143

SCK (CPOL = 1)

(Output)

148

149

MISO

(Input)

MSB

Valid

LSB

Valid

152

153

MOSI

(Output)

MSB

LSB

161

162

163

HREQ

(Input)

AA0272

Figure 2-28 SPI Master Timing (CPHA = 1)

2-56

DSP56366 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

147

142

144

160

SCK (CPOL = 0)

(Input)

146

142

143

SCK (CPOL = 1)

(Input)

154

152

153

151

LSB

150

MISO

(Output)

MSB

148

149

MSB

Valid

MOSI

(Input)

LSB

Valid

157

159

HREQ

(Output)

AA0273

Figure 2-29 SPI Slave Timing (CPHA = 0)

MOTOROLA

DSP56366 Advance Information

2-57

Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

142

141

147

144

SCK (CPOL = 0)

(Input)

146

142

144

143

SCK (CPOL = 1)

(Input)

152

153

151

150

MISO

(Output)

MSB

LSB

148

149

MSB

Valid

LSB

Valid

MOSI

(Input)

157

158

HREQ

(Output)

AA0274

Figure 2-30 SPI Slave Timing (CPHA = 1)

2-58

DSP56366 Advance Information

MOTOROLA

Specifications

2

Serial Host Interface (SHI) I C Protocol Timing

2

2.13 SERIAL HOST INTERFACE (SHI) I C PROTOCOL TIMING

2

Table 2-20 SHI I C Protocol Timing

Standard

5

Unit

Fast Mode

Min

4

Symbol/

Expression

Mode

1,2,3

No.

Characteristics

Min Max

Max

Tolerable spike width on SCL

or SDA

Filters bypassed

—

0

50

—

0

ns

kHz

µs

ns

µs

Narrow filters enabled

Wide filters enabled

—

50

—

100

—

100

400

—

171 SCL clock frequency

171 SCL clock cycle

F_SCL

T_SCL

—

10

2.5

172 Bus free time

T_BUF

4.7

4.0

4.7

4.0

—

1.3

—

173 Start condition set-up time

174 Start condition hold time

175 SCL low period

T_SU;STA

T_HD;STA

T_LOW

—

0.6

—

0.6

1.3

—

176 SCL high period

T_HIGH

—

1.3

—

177 SCL and SDA rise time

178 SCL and SDA fall time

179 Data set-up time

T

1000

300

—

20 + 0.1 × C_b

100

300

—

R

T

—

F

T_SU;DAT

T_HD;DAT

F_DSP

250

0.0

180 Data hold time

—

0.0

0.9

181 DSP clock frequency

Filters bypassed

10.6

11.8

13.1

—

28.5

39.7

61.0

—

MHz

µs

Narrow filters enabled

Wide filters enabled

—

182 SCL low to data out valid

T_VD;DAT

T_SU;STO

3.4

—

0.9

—

183 Stop condition set-up time

4.0

0.6

µs

MOTOROLA

DSP56366 Advance Information

2-59

Specifications

2

Serial Host Interface (SHI) I C Protocol Timing

2

Table 2-20 SHI I C Protocol Timing (continued)

Standard

5

Unit

Fast Mode

4

Symbol/

Expression

Mode

1,2,3

No.

Characteristics

Min Max

Min

Max

184 HREQ in deassertion to last

SCL edge (HREQ in set-up

time)

t_SU;RQI

0.0

—

0.0

—

ns

186 First SCL sampling edge to

HREQ output deassertion

T_NG;RQO

Filters bypassed 2 × T_C+ 30

Narrow filters enabled 2 × T_C+ 120

Wide filters enabled 2 × T_C+ 208

—

46.7

136.7

224.7

—

46.7

136.7

224.7

187 Last SCL edge to HREQ out-

put not deasserted

T_AS;RQO

ns

Filters bypassed 2 × T_C+ 30

46.7

96.7

—

46.7

96.7

—

Narrow filters enabled 2 × T_C+ 80

Wide filters enabled 2 × T_C+ 135 151.6

151.6

188 HREQ in assertion to first SCL

edge

T_AS;RQI

0.5 × T_I2_CCP

0.5 × T_C- 21

-

Filters bypassed

Narrow filters enabled

Wide filters enabled

4440

4373

0.0

—

1041

999

958

0.0

—

189 First SCL edge to HREQ in not

asserted (HREQ in hold time)

t_HO;RQI

Notes: 1. V_CC= 3.16 V ± 0.16 V; T_J= –40°C to +105°C

2. Pull-up resistor: R_P(min) = 1.5 kOhm

3. Capacitive load: C_b(max) = 400 pF

4. It is recommended to enable the wide filters when operating in the I²C Standard Mode.

5. It is recommended to enable the narrow filters when operating in the I²C Fast Mode.

2-60

DSP56366 Advance Information

MOTOROLA

Specifications

Serial Host Interface (SHI) I C Protocol Timing

2

2.13.1 Programming the Serial Clock

2

The programmed serial clock cycle, T_{I CCP}, is specified by the value of the HDM[7:0] and HRS bits of the

HCKR (SHI clock control register).

2

The expression for T_{I CCP}is

T

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

C

I²CCP

where

— HRS is the prescaler rate select bit. When HRS is cleared, the fixed

divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.

— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to

$FF) may be selected.

In I²C mode, the user may select a value for the programmed serial clock cycle from

6 × T

(if HDM[7:0] = $02 and HRS = 1)

C

to

4096 × T

(if HDM[7:0] = $FF and HRS = 0)

C

2

The programmed serial clock cycle (T_{I CCP}), SCL rise time (T_R), and the filters selected should be chosen

in order to achieve the desired SCL serial clock cycle (T_SCL), as shown in Table 2-21.

Table 2-21 SCL Serial Clock Cycle (T

) generated as Master

SCL

2

Filters bypassed

T

+ 2.5 × T_C+ 45ns + T

I CCP

R

2

Narrow filters enabled T

+ 2.5 × T_C+ 135ns + T

+ 2.5 × T_C+ 223ns + T

I CCP

R

2

Wide filters enabled

T

I CCP

EXAMPLE:

For DSP clock frequency of 120 MHz (i.e. T_C= 8.33ns), operating in a standard mode I²C environment

(F_SCL= 100 kHz (i.e. T_SCL= 10µs), T_R= 1000ns), with wide filters enabled:

T

= 10µs - 2.5×8.33ns - 223ns - 1000ns = 8756ns

I²CCP

Choosing HRS = 0 gives

HDM[7:0] = 8756ns / (2 × 8.33ns × 8) - 1 = 64.67

Thus the HDM[7:0] value should be programmed to $41 (=65).

2

The resulting T_{I CCP}will be:

T

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

I²CCP

C

= [8.33ns × 2 × (65 + 1) × (7 × (1 – 0) + 1)]

= [8.33ns × 2 × 66 × 8] = 8796.48ns

MOTOROLA

DSP56366 Advance Information

2-61

Specifications

Enhanced Serial Audio Interface Timing

171

173

176

175

SCL

SDA

177

180

178

172

179

MSB

LSB

ACK

Stop

Start

174

188

186

182

183

187

189

184

HREQ

AA0275

2

Figure 2-31 I C Timing

2.14 ENHANCED SERIAL AUDIO INTERFACE TIMING

Table 2-22 Enhanced Serial Audio Interface Timing

1, 2, 3

4

No.

SymbolExpression

Min Max

Unit

Characteristics

Condition

430 Clock cycle⁵

t_SSICC

4 × T

3 × T

33.3

25.0

27.2

—

i ck

x ck

ns

C

TXC:max[3*tc;

t454]

431 Clock high period

• For internal clock

—

2 × T − 10.0

6.7

—

ns

C

• For external clock

1.5 × T

12.5

6.7

—

C

432 Clock low period

• For internal clock

2 × T − 10.0

C

• For external clock

1.5 × T

12.5

—

C

433 RXC rising edge to FSR out

(bl) high

—

37.0

22.0

x ck

i ck a

2-62

DSP56366 Advance Information

MOTOROLA

Specifications

Enhanced Serial Audio Interface Timing

Table 2-22 Enhanced Serial Audio Interface Timing (continued)

1, 2, 3

4

No.

SymbolExpression

Min Max

Unit

Characteristics

Condition

434 RXC rising edge to FSR out

(bl) low

—

37.0

22.0

x ck

i ck a

ns

435 RXC rising edge to FSR out

(wr) high⁶

—

39.0

24.0

x ck

i ck a

ns

436 RXC rising edge to FSR out

(wr) low⁶

—

39.0

24.0

x ck

i ck a

437 RXC rising edge to FSR out

(wl) high

—

36.0

21.0

x ck

i ck a

438 RXC rising edge to FSR out

(wl) low

—

37.0

22.0

x ck

i ck a

439 Data in setup time before RXC

(SCK in synchronous mode)

falling edge

0.0

19.0

—

x ck

i ck

440 Data in hold time after RXC

falling edge

—

5.0

3.0

—

x ck

i ck

ns

441 FSR input (bl, wr) high before

RXC falling edge ⁶

23.0

1.0

—

x ck

i ck a

442 FSR input (wl) high before

RXC falling edge

1.0

23.0

—

x ck

i ck a

443 FSR input hold time after RXC

falling edge

3.0

0.0

—

x ck

i ck a

444 Flags input setup before RXC

falling edge

0.0

19.0

—

x ck

i ck s

445 Flags input hold time after RXC

falling edge

—

6.0

0.0

—

x ck

i ck s

446 TXC rising edge to FST out (bl)

high

—

29.0

15.0

x ck

i ck

447 TXC rising edge to FST out (bl)

low

—

31.0

17.0

x ck

i ck

448 TXC rising edge to FST out

(wr) high⁶

—

31.0

17.0

x ck

i ck

449 TXC rising edge to FST out

(wr) low⁶

—

33.0

19.0

x ck

i ck

MOTOROLA

DSP56366 Advance Information

2-63

Specifications

Enhanced Serial Audio Interface Timing

Table 2-22 Enhanced Serial Audio Interface Timing (continued)

1, 2, 3

4

No.

SymbolExpression

Min Max

Unit

Characteristics

Condition

450 TXC rising edge to FST out

(wl) high

—

30.0

16.0

x ck

i ck

ns

451 TXC rising edge to FST out

(wl) low

—

31.0

17.0

x ck

i ck

ns

452 TXC rising edge to data out

enable from high impedance

—

31.0

17.0

x ck

i ck

453 TXC rising edge to transmitter

#0 drive enable assertion

—

34.0

20.0

x ck

i ck

454 TXC rising edge to data out

valid

23 + 0.5 × T

—

27.2

21.0

x ck

i ck

C

21.0

455 TXC rising edge to data out

high impedance⁷

—

31.0

16.0

x ck

i ck

456 TXC rising edge to transmitter

#0 drive enable deassertion⁷

—

34.0

20.0

x ck

i ck

457 FST input (bl, wr) setup time

before TXC falling edge⁶

2.0

21.0

—

x ck

i ck

458 FST input (wl) to data out

enable from high impedance

—

27.0

—

459 FST input (wl) to transmitter #0

drive enable assertion

—

31.0

—

460 FST input (wl) setup time

before TXC falling edge

2.0

21.0

—

x ck

i ck

461 FST input hold time after TXC

falling edge

4.0

0.0

—

x ck

i ck

462 Flag output valid after TXC ris-

ing edge

—

32.0

18.0

x ck

i ck

463 HCKR/HCKT clock cycle

—

40.0

—

ns

464 HCKT input rising edge to TXC

output

27.5

465 HCKR input rising edge to

RXC output

—

27.5

ns

2-64

DSP56366 Advance Information

MOTOROLA

Specifications

Enhanced Serial Audio Interface Timing

Table 2-22 Enhanced Serial Audio Interface Timing (continued)

1, 2, 3

4

No.

SymbolExpression

Min Max

Unit

Characteristics

Condition

Notes: 1. V_CC= 3.16 V ± 0.16 V; T_J= –40°C to +105°C, C_L= 50 pF

2. i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that TXC and RXC are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that TXC and RXC are the same clock)

3. bl = bit length

wl = word length

wr = word length relative

4. TXC(SCKT pin) = transmit clock

RXC(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the

bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit

length frame sync signal), until the one before last bit clock of the first word in frame.

7. Periodically sampled and not 100% tested

MOTOROLA

DSP56366 Advance Information

2-65

Specifications

Enhanced Serial Audio Interface Timing

430

431

432

TXC

(Input/Output

)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

455

First Bit

Last Bit

Data Out

459

Transmitter

#0 Drive

Enable

457

453

456

461

460

FST (Bit) In

458

461

FST (Word)

In

462

See Note

Flags Out

Note: In network mode, output flag transitions can occur at the start of each time slot

within the frame. In normal mode, the output flag state is asserted for the entire

frame period.

AA0490

Figure 2-32 ESAI Transmitter Timing

2-66

DSP56366 Advance Information

MOTOROLA

Specifications

Enhanced Serial Audio Interface Timing

430

431

432

RXC

(Input/Output)

433

434

FSR (Bit)

Out

437

438

FSR (Word)

Out

440

439

443

Data In

Last Bit

First Bit

441

FSR (Bit)

In

442

443

445

FSR (Word)

In

444

Flags In

AA0491

Figure 2-33 ESAI Receiver Timing

HCKT

463

SCKT(output)

464

Figure 2-34 ESAI HCKT Timing

MOTOROLA

DSP56366 Advance Information

2-67

Specifications

Digital Audio Transmitter Timing

HCKR

463

SCKR (output)

465

Figure 2-35 ESAI HCKR Timing

2.15 DIGITAL AUDIO TRANSMITTER TIMING

Table 2-23 Digital Audio Transmitter Timing

120 MHz

No.

Characteristic

Expression

Unit

Min Max

ACI frequency (see note)

1 / (2 x T_C)

2 × T_C

—

16.7

4.2

—

60

—

MHz

ns

220 ACI period

221 ACI high duration

222 ACI low duration

223 ACI rising edge to ADO valid

0.5 × T_C

1.5 × T_C

—

ns

—

ns

12.5

ns

Note:

In order to assure proper operation of the DAX, the ACI frequency should be

less than 1/2 of the DSP56366 internal clock frequency. For example, if the

DSP56366 is running at 120 MHz internally, the ACI frequency should be less

than 60 MHz.

ACI

220

221

222

223

ADO

AA1280

Figure 2-36 Digital Audio Transmitter Timing

2-68

DSP56366 Advance Information

MOTOROLA

Specifications

Timer Timing

2.16 TIMER TIMING

Table 2-24 Timer Timing

120 MHz

No.

Characteristics

Expression

Unit

Min Max

480 TIO Low

481 TIO High

2 × T_C+ 2.0

18.7

—

ns

Note:

V_CC= 3.3 V ± 0.16 V; T_J= –40°C to +105°C, C_L= 50 pF

TIO

480

481

AA0492

Figure 2-37 TIO Timer Event Input Restrictions

MOTOROLA

DSP56366 Advance Information

2-69

Specifications

GPIO Timing

2.17 GPIO TIMING

Table 2-25 GPIO Timing

1

No.

Expression Min Max Unit

Characteristics

490²EXTAL edge to GPIO out valid (GPIO out delay time)

491 EXTAL edge to GPIO out not valid (GPIO out hold time)

492 GPIO In valid to EXTAL edge (GPIO in set-up time)

493 EXTAL edge to GPIO in not valid (GPIO in hold time)

494²Fetch to EXTAL edge before GPIO change

495 GPIO out rise time

—

32.8

—

ns

4.8

10.2

1.8

—

6.75 × T_C-1.8 54.5

—

13

496 GPIO out fall time

Notes: 1. V_CC= 3.3 V ± 0.16 V; T_J= –40°C to +105°C, C_L= 50 pF

2. Valid only when PLL enabled with multiplication factor equal to one.

EXTAL

(Input)

490

491

GPIO

(Output)

492

493

GPIO

(Input)

Valid

A0–A17

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of GPIO data register.

GPIO

(Output)

495

496

Figure 2-38 GPIO Timing

2-70

DSP56366 Advance Information

MOTOROLA

Specifications

JTAG Timing

2.18 JTAG TIMING

Table 2-26 JTAG Timing

All frequencies

No.

Characteristics

Unit

Min

Max

500 TCK frequency of operation (1/(T_C× 3); maximum 22 MHz)

501 TCK cycle time in Crystal mode

502 TCK clock pulse width measured at 1.5 V

503 TCK rise and fall times

0.0

45.0

20.0

0.0

22.0

—

MHz

ns

—

3.0

—

504 Boundary scan input data setup time

505 Boundary scan input data hold time

506 TCK low to output data valid

5.0

24.0

0.0

—

40.0

—

507 TCK low to output high impedance

508 TMS, TDI data setup time

0.0

5.0

509 TMS, TDI data hold time

25.0

0.0

—

510 TCK low to TDO data valid

44.0

511 TCK low to TDO high impedance

Notes: 1. V_CC= 3.3 V ± 0.16 V; T_J= –40°C to +105°C, C_L= 50 pF

0.0

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

501

502

VM

VIH

TCK

(Input)

VIL

503

AA0496

Figure 2-39 Test Clock Input Timing Diagram

MOTOROLA

DSP56366 Advance Information

2-71

Specifications

JTAG Timing

VIH

505

TCK

(Input)

VIL

504

Data

Inputs

Input Data Valid

506

507

506

Data

Output Data Valid

Outputs

Data

Outputs

Data

Outputs

Output Data Valid

AA0497

Figure 2-40 Boundary Scan (JTAG) Timing Diagram

VIH

509

Input Data Valid

TCK

VIL

(Input)

508

TDI

TMS

(Input)

510

TDO

(Output)

Output Data Valid

511

TDO

(Output)

510

TDO

(Output)

Output Data Valid

Figure 2-41 Test Access Port Timing Diagram

AA0498

2-72

DSP56366 Advance Information

MOTOROLA

SECTION 3

PACKAGING

3.1

PIN-OUT AND PACKAGE INFORMATION

This section provides information about the available package for this product, including diagrams of the

package pinouts and tables describing how the signals described in Section 1 are allocated for the

package. The DSP56366 is available in a 144-pin LQFP package. Figure 3-1 and Figure 3-2 show the

pin/name assignments for the packages.

3.1.1

LQFP Package Description

Top view of the 144-pin LQFP package is shown in Figure 3-1 with its pin-outs. The package drawing is

shown in Figure 3-2.

MOTOROLA

DSP56366 Advance Information

3-1

Packaging

Pin-out and Package Information

SCK/SCL

SS#/HA2

HREQ#

1

2

108

107

106

105

104

103

102

101

100

99

D6

D5

3

D4

D3

SDO0/SDO0_1

SDO1/SDO1_1

SDO2/SDI3/SDO2_1/SDI3_1

SDO3/SDI2/SDO3_1/SDI2_1

VCCS

4

5

GNDD

VCCD

D2

6

7

8

D1

D0

GNDS

9

SDO4/SDI1

SDO5/SDI0

FST

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

A17

A16

A15

GNDA

VCCQH

A14

A13

A12

VCCQL

GNDQ

A11

A10

GNDA

VCCA

A9

98

97

FSR

96

SCKT

95

SCKR

94

HCKT

93

HCKR

92

VCCQL

91

GNDQ

90

VCCQH

89

HDS/HWR

HRW/HRD

HACK/HRRQ

HOREQ/HTRQ

VCCS

88

87

86

85

84

A8

GNDS

83

A7

ADO

82

A6

ACI

81

GNDA

VCCA

A5

TIO0

80

HCS/HA10

HA9/HA2

HA8/HA1

HAS/HA0

HAD7

79

78

A4

77

A3

76

A2

75

GNDA

VCCA

A1

HAD6

HAD5

74

73

Figure 3-1 144-pin package

3-2

DSP56366 Advance Information

MOTOROLA

Packaging

Pin-out and Package Information

Table 3-1 Signal Identification by Name

Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.

Signal Name

SDO0/SDO0_1

Pin No.

A0

72

73

76

77

78

79

82

83

84

85

88

89

92

93

94

97

98

99

70

69

51

28

27

64

D9

113

114

115

116

117

118

121

122

123

124

125

128

131

132

133

55

GNDS

9

4

A1

D10

GNDS

26

32

31

23

43

42

41

40

37

36

35

34

33

17

16

30

21

SDO1/SDO1_1

SDO2/SDI3/SDO2_1/SDI3_1

SDO3/SDI2/SDO3_1/SDI2_1

SDO4/SDI1

SDO4_1/SDI1_1

SDO5/SDI0

SDO5_1/SDI0_1

SS#/HA2

TA#

5

A2

D11

HA8/HA1

HA9/HA2

HACK/HRRQ

HAD0

6

A3

D12

7

A4

D13

10

138

11

48

2

A5

D14

A6

D15

HAD1

A7

D16

HAD2

A8

D17

HAD3

A9

D18

HAD4

62

141

140

139

29

142

74

80

86

57

65

103

111

119

129

38

A10

A11

A12

A13

A14

A15

A16

A17

AA0

AA1

AA2

ACI

ADO

BB#

BG#

BR#

CAS#

D0

D19

HAD5

TCK

D20

HAD6

TDI

D21

HAD7

TDO

D22

HAS/HA0

HCKR

TIO0

D23

TMS

EXTAL

FSR

HCKT

VCCA

13

HCS/HA10

HDS/HWR

VCCA

FSR_1

FST

59

VCCA

12

HOREQ/HTRQ 24

VCCC

FST_1

GNDA

GNDC

GNDD

GNDH

GNDP

GNDQ

50

HREQ#

3

VCCC

75

HRW/HRD

MODA/IRQA#

MODB/IRQB#

MODC/IRQC#

MODD/IRQD#

MISO/SDA

MOSI/HA0

PCAP

22

137

136

135

134

144

143

46

VCCD

81

VCCD

87

VCCD

96

VCCD

71

58

VCCH

63

66

20

VCCQH

VCCQL

VCCP

52

104

112

120

130

39

95

100

101

102

105

106

107

108

109

110

49

61

18

D1

PINIT/NMI#

RD#

68

56

D2

44

91

D3

RESET#

SCK/SCL

SCKR

47

1

126

45

D4

19

15

D5

54

60

8

D6

SCKR_1

SCKT

VCCS

90

14

25

D7

VCCS

127

53

67

D8

SCKT_1

WR#

MOTOROLA

DSP56366 Advance Information

3-3

Packaging

Pin-out and Package Information

Table 3-2 Signal Identification by Pin Number

Pin No.

Signal Name

SCK/SCL

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1

37

38

39

40

41

HAD4

VCCH

GNDH

HAD3

HAD2

HAD1

HAD0

RESET#

VCCP

PCAP

GNDP

73

74

75

76

77

78

79

80

81

82

83

A1

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

D7

2

SS#/HA2

VCCA

GNDA

A2

D8

3

HREQ#

VCCD

GNDD

D9

4

SDO0/SDO0_1

SDO1/SDO1_1

5

A3

6

SDO2/SDI3/SDO2_1/SDI3_1 42

SDO3/SDI2/SDO3_1/SDI2_1 43

A4

D10

7

A5

D11

8

VCCS

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

VCCA

GNDA

A6

D12

9

GNDS

D13

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

SDO4/SDI1

SDO5/SDI0

FST

D14

A7

VCCD

GNDD

D15

SDO5_1/SDI0_1 84

A8

FSR

VCCQH

FST_1

AA2

85

A9

SCKT

86

VCCA

GNDA

A10

A11

GNDQ

VCCQL

A12

A13

A14

VCCQH

GNDA

A15

A16

A17

D0

D16

SCKR

87

D17

HCKT

CAS#

SCKT_1

GNDQ

EXTAL

VCCQL

VCCC

GNDC

FSR_1

SCKR_1

PINIT/NMI#

TA#

88

D18

HCKR

89

D19

VCCQL

GNDQ

90

VCCQL

GNDQ

D20

91

VCCQH

HDS/HWR

HRW/HRD

HACK/HRRQ

HOREQ/HTRQ

VCCS

92

93

VCCD

GNDD

D21

94

95

96

D22

97

D23

GNDS

98

MODD/IRQD#

MODC/IRQC#

MODB/IRQB#

MODA/IRQA#

SDO4_1/SDI1_1

TDO

ADO

BR#

99

ACI

BB#

100

101

102

103

104

105

106

107

108

TIO0

VCCC

GNDC

WR#

D1

HCS/HA10

HA9/HA2

HA8/HA1

HAS/HA0

HAD7

D2

VCCD

GNDD

D3

RD#

TDI

AA1

TCK

AA0

D4

TMS

HAD6

BG#

D5

MOSI/HA0

MISO/SDA

HAD5

A0

D6

3-4

DSP56366 Advance Information

MOTOROLA

Packaging

Pin-out and Package Information

3.1.2

LQFP Package Mechanical Drawing

Figure 3-2 DSP56366 144-pin LQFP Package

MOTOROLA

DSP56366 Advance Information

3-5

Packaging

Ordering Drawings

3.2

ORDERING DRAWINGS

The detailed package drawing is available on the Motorola web page at:

http://www.mot-sps.com/cgi-bin/cases.pl

Use package 918-03 for the search.

3-6

DSP56366 Advance Information

MOTOROLA

SECTION 4

DESIGN CONSIDERATIONS

4.1

THERMAL DESIGN CONSIDERATIONS

An estimation of the chip junction temperature, T_J, in °C can be obtained from the following equation:

= T + (P × R

T

)

J

A

D

θJA

Where:

T_A= ambient temperature °C

R_qJA= package junction-to-ambient thermal resistance °C/W

P_D= power dissipation in package W

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance

and a case-to-ambient thermal resistance.

R

= R

+ R

θJA

θJC

θCA

Where:

R_θJA= package junction-to-ambient thermal resistance °C/W

R_θJC= package junction-to-case thermal resistance °C/W

R_θCA= package case-to-ambient thermal resistance °C/W

R

_θJCis device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R_θCA. For example, the user can change the air flow

around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB),

or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This

model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated

through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations

where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of

the device thermal performance may need the additional modeling capability of a system level thermal

simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which

the package is mounted. Again, if the estimations obtained from R_θJAdo not satisfactorily answer whether

the thermal performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common ways for determining the junction-to-case thermal

resistance in plastic packages.

•

To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that

surface has a proper heat sink.

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal

resistance is measured from the junction to where the leads are attached to the case.

If the temperature of the package case (T_T) is determined by a thermocouple, the thermal

resistance is computed using the value obtained by the equation

(T_J– T_T)/P_D.

MOTOROLA

DSP56366 Advance Information

4-1

Design Considerations

Electrical Design Considerations

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using

the first definition. From a practical standpoint, that value is also suitable for determining the junction

temperature from a case thermocouple reading in forced convection environments. In natural convection,

using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple

reading on the case of the package will estimate a junction temperature slightly hotter than actual

temperature. Hence, the new thermal metric, thermal characterization parameter or Ψ_JT, has been defined

to be (T_J– T_T)/P_D. This value gives a better estimate of the junction temperature in natural convection

when using the surface temperature of the package. Remember that surface temperature readings of

packages are subject to significant errors caused by inadequate attachment of the sensor to the surface

and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge

thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

4.2

ELECTRICAL DESIGN CONSIDERATIONS

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields. However, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability of operation is

enhanced if unused inputs are tied to an

appropriate logic voltage level (e.g., either

GND or V ). The suggested value for a

CC

pullup or pulldown resistor is 10 kOhm.

Use the following list of recommendations to assure correct DSP operation:

•

Provide a low-impedance path from the board power supply to each V_CCpin on the DSP and from

the board ground to each GND pin.

Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of

the package to connect the V_CCpower source to GND.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_CCand

GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for V_CCand GND.

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB,

IRQC, IRQD, TA and BG pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are

recommended.

•

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating

capacitance. This is especially critical in systems with higher capacitive loads that could create

higher transient currents in the V_CCand GND circuits.

4-2

DSP56366 Advance Information

MOTOROLA

Design Considerations

Power Consumption Considerations

•

All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three pins

with internal pull-up resistors (TMS, TDI, TCK).

•

Take special care to minimize noise levels on the V_CCPand GND_Ppins.

If multiple DSP56366 devices are on the same board, check for cross-talk or excessive spikes on

the supplies due to synchronous operation of the devices.

•

RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied

while RESET is being asserted.

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V_CC

never exceeds 3.95 V.

4.3

POWER CONSUMPTION CONSIDERATIONS

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current

consumption are described in this section. Most of the current consumed by CMOS devices is alternating

current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by the following formula:

I = C × V × f

where

C = node/pin capacitance

V = voltage swing

f = frequency of node/pin toggle

Example 1 Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 120 MHz

clock, toggling at its maximum possible rate (60 MHz), the current consumption is

–12

6

I = 50 × 10

× 3.3 × 60 × 10 = 9.9mA

The maximum internal current (I_CCImax) value reflects the typical possible switching of the internal buses

on best-case operation conditions, which is not necessarily a real application case. The typical internal

current (I_CCItyp) value reflects the average switching of the internal buses on typical operating conditions.

For applications that require very low current consumption, do the following:

•

Set the EBD bit when not accessing external memory.

Minimize external memory accesses and use internal memory accesses.

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

MOTOROLA

DSP56366 Advance Information

4-3

Design Considerations

PLL Performance Issues

One way to evaluate power consumption is to use a current per MIPS measurement methodology to

minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A

benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test

current measurements, and the following equation to derive the current per MIPS value.

I ⁄ MIPS = I ⁄ MHz = (I

– I

typF2 typF1

) ⁄ (F –2 F) 1

where :

I_typF2= current at F2

I_typF1= current at F1

F2 = high frequency (any specified operating frequency)

F1 = low frequency (any specified operating frequency lower than F2)

Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and

F1 could be 33 MHz. The degree of difference between F1 and F2 determines

the amount of precision with which the current rating can be determined for an

application.

4.4

PLL PERFORMANCE ISSUES

The following explanations should be considered as general observations on expected PLL behavior.

There is no testing that verifies these exact numbers. These observations were measured on a limited

number of parts and were not verified over the entire temperature and voltage ranges.

4.4.1

Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and

the internal DSP clock for a given device in specific temperature, voltage, input frequency and MF. These

variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF≤

4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input

frequencies greater than 10 MHz, this jitter is less than ±2 ns.

4.4.2

Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of the internal DSP clock. For

small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between

0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2–3%.

4.4.3

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is

slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of

the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%.

The phase and frequency jitter performance results are only valid if the input jitter is less than the

prescribed values.

4-4

DSP56366 Advance Information

MOTOROLA

Design Considerations

Host Port Considerations

4.5

HOST PORT CONSIDERATIONS

Careful synchronization is required when reading multi-bit registers that are written by another

asynchronous system. This synchronization is a common problem when two asynchronous systems are

connected, as they are in the host interface. The following paragraphs present considerations for proper

operation.

4.5.1

Host Programming Considerations

•

Unsynchronized Reading of Receive Byte Registers—When reading the receive byte registers,

receive register high (RXH), receive register middle (RXM), or receive register low (RXL), the host

interface programmer should use interrupts or poll the receive register data full (RXDF) flag that

indicates whether data is available. This ensures that the data in the receive byte registers will be

valid.

•

Overwriting Transmit Byte Registers—The host interface programmer should not write to the

transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit

register low (TXL), unless the transmit register data empty (TXDE) bit is set, indicating that the

transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid

data to the host receive (HRX) register.

Synchronization of Status Bits from DSP to Host—HC, HOREQ, DMA, HF3, HF2, TRDY,

TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor

(refer to the user’s manual for descriptions of these status bits). The host can read these status bits

very quickly without regard to the clock rate used by the DSP, but the state of the bit could be

changing during the read operation. This is not generally a system problem, because the bit will be read

correctly in the next pass of any host polling routine.

However, if the host asserts HEN for more than timing number 31, with

a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be

stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP

changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits

during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has

significance, the host could read the wrong combination. Therefore, read the bits twice and check

for consensus.

•

Overwriting the Host Vector—The host interface programmer should change the host vector (HV)

register only when the host command (HC) bit is clear. This ensures that the DSP interrupt control

logic will receive a stable vector.

Cancelling a Pending Host Command Exception—The host processor may elect to clear the HC

bit to cancel the host command exception request at any time before it is recognized by the DSP.

Because the host does not know exactly when the exception will be recognized (due to exception

processing synchronization and pipeline delays), the DSP may execute the host command

exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the

same time that the HC bit is cleared.

•

Variance in the Host Interface Timing—The host interface (HDI) may vary (e.g. due to the PLL

lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make

sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then

polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together

with the INIT and then polling INIT, ISR, and the HOREQ pin).

MOTOROLA

DSP56366 Advance Information

4-5

Design Considerations

Host Port Considerations

4.5.2

DSP Programming Considerations

•

Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, HCP, HTDE, and HRDF

status bits are set or cleared by the host processor side of the interface. These bits are individually

synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)

•

Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when reading status bits

HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have

significance). A very small probability exists that the DSP will read the status bits synchronized

during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.

4-6

DSP56366 Advance Information

MOTOROLA

SECTION 5

ORDERING INFORMATION

Consult a Motorola Semiconductor sales office or authorized distributor to determine product

availability and to place an order.

Table 5-1 Ordering Information

Supply

Voltage

Count

Frequency

(MHz)

Part

Package Type

Order Number

DSP56366

3.3 V

Thin quad flat pack (TQFP)

144

120

XCD56366PV120

Notes: 1. Please consult the web site at www.dspaudio.motorola.com for current availability.

2. Future products in the DSP56366 family may include other ROM-based options. For additional

information on future part development, or to request customer-specific ROM-based support, call your

local Motorola Semiconductor sales office or authorized distributor.

MOTOROLA

DSP56366 Advance Information

5-1

THIS PAGE INTENTIONALLY LEFT BLANK

APPENDIX A

POWER CONSUMPTION BENCHMARK

The following benchmark program permits evaluation of DSP power usage in a test situation. It

enables the PLL, disables the external clock, and uses repeated multiply-accumulate instructions

with a set of synthetic DSP application data to emulate intensive sustained DSP operation.

;********************************************************************;**

******************************************************************

;* ;* CHECKS

Typical Power Consumption

;********************************************************************

page

200,55,0,0,0

nolist

I_VEC EQU $000000 ; Interrupt vectors for program debug only

START EQU $8000 ; MAIN (external) program starting address

INT_PROG EQU $100 ; INTERNAL program memory starting address

INT_XDAT EQU $0

INT_YDAT EQU $0

; INTERNAL X-data memory starting address

; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm"

INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM)

; Default: 1 w.s (SRAM)

;

movep

#$0d0000,x:M_PCTL

; XTAL disable

; PLL enable

; CLKOUT disable

;

; Load the program

;

move

#INT_PROG,r0

#PROG_START,r1

do

move

#(PROG_END-PROG_START),PLOAD_LOOP

p:(r1)+,x0

move

x0,p:(r0)+

nop

PLOAD_LOOP

;

; Load the X-data

;

MOTOROLA

DSP56366 Advance Information

A-1

Power Consumption Benchmark

move

do

move

#INT_XDAT,r0

#XDAT_START,r1

#(XDAT_END-XDAT_START),XLOAD_LOOP

p:(r1)+,x0

x0,x:(r0)+

XLOAD_LOOP

;

; Load the Y-data

;

move

#INT_YDAT,r0

move

#YDAT_START,r1

do

move

#(YDAT_END-YDAT_START),YLOAD_LOOP

p:(r1)+,x0

move

YLOAD_LOOP

;

x0,y:(r0)+

jmp

INT_PROG

PROG_START

move

;

#$0,r0

#$0,r4

#$3f,m0

#$3f,m4

clr

a

clr

b

move

bset

;

#$0,x0

#$0,x1

#$0,y0

#$0,y1

#4,omr

; ebd

sbr

dor

mac

add

mac

move

#60,_end

x0,y0,a x:(r0)+,x1

x1,y1,a x:(r0)+,x0

a,b

x0,y0,a x:(r0)+,x1

x1,y1,a

y:(r4)+,y1

y:(r4)+,y0

b1,x:$ff

_end

bra

nop

sbr

PROG_END

nop

XDAT_START

org

;

x:0

A-2

DSP56366 Advance Information

MOTOROLA

Power Consumption Benchmark

dc

$262EB9

$86F2FE

$E56A5F

$616CAC

$8FFD75

$9210A

$A06D7B

$CEA798

$8DFBF1

$A063D6

$6C6657

$C2A544

$A3662D

$A4E762

$84F0F3

$E6F1B0

$B3829

$8BF7AE

$63A94F

$EF78DC

$242DE5

$A3E0BA

$EBAB6B

$8726C8

$CA361

$2F6E86

$A57347

$4BE774

$8F349D

$A1ED12

$4BFCE3

$EA26E0

$CD7D99

$4BA85E

$27A43F

$A8B10C

$D3A55

$25EC6A

$2A255B

$A5F1F8

$2426D1

$AE6536

$CBBC37

$6235A4

$37F0D

$63BEC2

$A5E4D3

$8CE810

$3FF09

$60E50E

$CFFB2F

$40753C

$8262C5

MOTOROLA

DSP56366 Advance Information

A-3

Power Consumption Benchmark

dc

$CA641A

$EB3B4B

$2DA928

$AB6641

$28A7E6

$4E2127

$482FD4

$7257D

$E53C72

$1A8C3

$E27540

XDAT_END

YDAT_START

org

;

y:0

dc

$5B6DA

$C3F70B

$6A39E8

$81E801

$C666A6

$46F8E7

$AAEC94

$24233D

$802732

$2E3C83

$A43E00

$C2B639

$85A47E

$ABFDDF

$F3A2C

$2D7CF5

$E16A8A

$ECB8FB

$4BED18

$43F371

$83A556

$E1E9D7

$ACA2C4

$8135AD

$2CE0E2

$8F2C73

$432730

$A87FA9

$4A292E

$A63CCF

$6BA65C

$E06D65

$1AA3A

$A1B6EB

$48AC48

$EF7AE1

$6E3006

$62F6C7

A-4

DSP56366 Advance Information

MOTOROLA

Power Consumption Benchmark

dc

$6064F4

$87E41D

$CB2692

$2C3863

$C6BC60

$43A519

$6139DE

$ADF7BF

$4B3E8C

$6079D5

$E0F5EA

$8230DB

$A3B778

$2BFE51

$E0A6B6

$68FFB7

$28F324

$8F2E8D

$667842

$83E053

$A1FD90

$6B2689

$85B68E

$622EAF

$6162BC

$E4A245

YDAT_END

MOTOROLA

DSP56366 Advance Information

A-5

THIS PAGE INTENTIONALLY LEFT BLANK

APPENDIX B

IBIS MODEL

[IBIS ver]

[File name]

[File Rev]

[Date]

2.1

56366.ibs

0.0

29/6/2000

56366

[Component]

[Manufacturer] Motorola

[Package]

|variable

R_pkg

typ

45m

min

22m

max

75m

L_pkg

C_pkg

2.5nH

1.3pF

1.1nH

1.2pF

4.3nH

1.4pF

[Pin]signal_name model_name

1 sck

2 ss_

ip5b_io

3 hreq_

4 sdo0

5 sdo1

ip5b_io

6 sdoi23

7 sdoi32

8 svcc

ip5b_io

power

gnd

9 sgnd

10 sdoi41

11 sdoi50

12 fst

ip5b_io

power

13 fsr

14 sckt

15 sckr

16 hsckt

17 hsckr

18 qvccl

19 gnd

gnd

20 qvcch

21 hp12

22 hp11

23 hp15

24 hp14

25 svcc

26 sgnd

27 ado

28 aci

29 tio

30 hp13

31 hp10

32 hp9

power

ip5b_io

power

gnd

ip5b_io

33 hp8

34 hp7

MOTOROLA

DSP56366 Advance Information

B-1

IBIS Model

35 hp6

36 hp5

37 hp4

38 svcc

39 sgnd

40 hp3

41 hp2

42 hp1

ip5b_io

power

gnd

ip5b_io

ip5b_i

power

gnd

ipbw_io

power

ipbw_io

icbc_o

ipbw_io

gnd

43 hp0

44 ires_

45 pvcc

46 pcap

47 pgnd

48 sdo5

49 qvcch

50 fst_1

51 aa2

52 cas_

53 sck_1

54 qgnd

55 cxtldis_

56 qvccl

57 cvcc

58 cgnd

59 fsr_1

60 sckr1

61 nmi_

62 ta_

63 br_

64 bb_

65 cvcc

66 cgnd

67 wr_

68 rd_

69 aa1

70 aa0

71 bg_

72 eab0

73 eab1

74 avcc

75 agnd

76 eab2

77 eab3

78 eab4

79 eab5

80 avcc

81 agnd

82 eab6

83 eab7

84 eab8

85 eab9

86 avcc

87 agnd

iexlh_i

power

gnd

ipbw_io

ipbw_i

icbc_o

power

gnd

icbc_o

icba_o

power

gnd

icba_o

power

gnd

icba_o

power

gnd

B-2

DSP56366 Advance Information

MOTOROLA

IBIS Model

88 eab10

89 eab11

90 qgnd

icba_o

gnd

91 qvcc

power

92 eab12

93 eab13

94 eab14

95 qvcch

96 agnd

icba_o

power

gnd

97 eab15

98 eab16

99 eab17

100 edb0

101 edb1

102 edb2

103 dvcc

104 dgnd

105 edb3

106 edb4

107 edb5

108 edb6

109 edb7

110 edb8

111 dvcc

112 dgnd

113 edb9

114 edb10

115 edb11

116 edb12

117 edb13

118 edb14

119 dvcc

120 dgnd

121 edb15

122 edb16

123 edb17

124 edb18

125 edb19

126 qvccl

127 qgnd

128 edb20

129 dvcc

130 dgnd

131 edb21

132 edb22

133 edb23

134 irqd_

135 irqc_

136 irqb_

137 irqa_

138 sdo4_1

139 tdo

icba_o

icba_io

power

gnd

icba_io

power

gnd

icba_io

power

gnd

icba_io

power

gnd

icba_io

power

gnd

icba_io

ip5b_i

ip5b_io

ip5b_o

ip5b_i

140 tdi

MOTOROLA

DSP56366 Advance Information

B-3

IBIS Model

141 tck

ip5b_i

ip5b_io

142 tms

143 mosi

144 sda

|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

ip5b_i

Input

Non-Inverting

5.00pF

|

[Voltage Range]

[GND_clamp]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-9.69e-03

-2.83e-04

-1.35e-06

-1.31e-09

-2.92e-11

-2.44e-11

-3.65e+02

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-7.81e-03

-8.42e-04

-1.00e-05

-8.58e-09

-3.64e-11

-2.79e-11

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-5.70e-03

-4.53e-05

-3.74e-07

-3.00e-09

-5.14e-10

|

[Model]

Model_type

Polarity

ip5b_io

I/O

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

[Voltage Range]

[Pulldown]

|voltage

|

5.00pF

3v

5.00pF

3.3v

I(typ)

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

B-4

DSP56366 Advance Information

MOTOROLA

IBIS Model

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-5.10e-02

-3.65e-02

-2.65e-02

-1.62e-02

-5.49e-03

5.377e-03

1.516e-02

2.370e-02

3.098e-02

3.700e-02

4.175e-02

4.531e-02

4.779e-02

4.935e-02

5.013e-02

5.046e-02

5.063e-02

5.075e-02

5.085e-02

5.090e-02

4.771e-02

4.525e-02

4.657e-02

4.904e-02

5.221e-02

5.524e-02

5.634e-02

5.751e-02

5.634e-02

5.648e-02

5.664e-02

5.679e-02

5.693e-02

5.707e-02

5.722e-02

5.741e-02

5.766e-02

5.801e-02

5.824e-02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-2.25e-02

-1.38e-02

-8.35e-03

-2.80e-03

2.744e-03

7.871e-03

1.252e-02

1.667e-02

2.026e-02

2.324e-02

2.553e-02

2.709e-02

2.803e-02

2.851e-02

2.876e-02

2.892e-02

2.904e-02

2.912e-02

2.876e-02

2.994e-02

3.321e-02

3.570e-02

3.801e-02

4.029e-02

4.253e-02

4.463e-02

4.645e-02

4.786e-02

4.881e-02

4.912e-02

4.795e-02

4.679e-02

4.688e-02

4.700e-02

4.712e-02

4.723e-02

4.733e-02

4.737e-02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.69e+00

-5.63e-02

-4.28e-02

-3.12e-02

-1.91e-02

-6.52e-03

6.427e-03

1.823e-02

2.869e-02

3.776e-02

4.544e-02

5.171e-02

5.660e-02

6.023e-02

6.271e-02

6.419e-02

6.494e-02

6.525e-02

6.540e-02

6.549e-02

6.555e-02

6.561e-02

6.182e-02

6.049e-02

6.178e-02

6.450e-02

6.659e-02

6.867e-02

6.970e-02

6.938e-02

6.960e-02

6.983e-02

7.005e-02

7.026e-02

7.049e-02

7.074e-02

7.105e-02

7.147e-02

7.205e-02

7.242e-02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

2.922e-04

2.881e-04

2.177e-04

2.175e-04

4.123e-04

4.021e-04

MOTOROLA

DSP56366 Advance Information

B-5

IBIS Model

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

2.853e-04

2.836e-04

2.825e-04

2.819e-04

2.815e-04

2.813e-04

2.812e-04

2.811e-04

2.810e-04

2.809e-04

2.808e-04

2.997e-04

1.750e-02

1.048e-02

3.487e-03

-3.40e-03

-9.69e-03

-1.52e-02

-2.02e-02

-2.46e-02

-2.84e-02

-3.14e-02

-3.37e-02

-3.55e-02

-3.68e-02

-3.78e-02

-3.85e-02

-3.91e-02

-3.96e-02

-4.01e-02

-4.04e-02

-4.08e-02

-4.11e-02

-4.14e-02

-4.17e-02

-4.32e-02

-4.08e-01

-2.73e+01

-6.13e+01

-9.54e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.21e+02

2.173e-04

2.172e-04

2.171e-04

2.170e-04

2.169e-04

2.167e-04

2.520e-04

3.078e-02

2.684e-02

2.277e-02

1.864e-02

1.447e-02

1.031e-02

6.181e-03

2.084e-03

-2.03e-03

-5.71e-03

-8.99e-03

-1.19e-02

-1.43e-02

-1.62e-02

-1.77e-02

-1.88e-02

-1.95e-02

-2.00e-02

-2.04e-02

-2.07e-02

-2.10e-02

-2.12e-02

-2.15e-02

-2.17e-02

-2.18e-02

-2.20e-02

-2.78e-02

-1.20e+00

-2.15e+01

-4.52e+01

-6.89e+01

-9.25e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.18e+02

3.946e-04

3.893e-04

3.857e-04

3.834e-04

3.820e-04

3.812e-04

3.808e-04

3.806e-04

3.804e-04

3.802e-04

3.801e-04

3.799e-04

3.797e-04

3.776e-04

4.568e-03

-4.22e-03

-1.24e-02

-1.95e-02

-2.61e-02

-3.21e-02

-3.73e-02

-4.18e-02

-4.55e-02

-4.85e-02

-5.09e-02

-5.27e-02

-5.41e-02

-5.51e-02

-5.60e-02

-5.67e-02

-5.74e-02

-5.79e-02

-5.84e-02

-5.89e-02

-5.94e-02

-5.98e-02

-6.10e-02

-6.84e-02

-7.73e+00

-4.18e+01

-7.59e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.41e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

B-6

DSP56366 Advance Information

MOTOROLA

IBIS Model

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-9.69e-03

-2.83e-04

-1.35e-06

-1.31e-09

-2.92e-11

-2.44e-11

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-5.70e-03

-4.53e-05

-3.74e-07

-3.00e-09

-5.14e-10

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-7.81e-03

-8.42e-04

-1.00e-05

-8.58e-09

-3.64e-11

-2.79e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.030/0.465

1.290/0.671

0.605/0.676

0.829/0.122

1.320/0.366

1.520/0.431

dV/dt_f

|

[Model]

Model_type

Polarity

C_comp

|

ip5b_o

3-state

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-5.10e-02

-3.65e+02

-5.18e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.69e+00

-5.63e-02

MOTOROLA

DSP56366 Advance Information

B-7

IBIS Model

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-3.65e-02

-2.65e-02

-1.62e-02

-5.49e-03

5.377e-03

1.516e-02

2.370e-02

3.098e-02

3.700e-02

4.175e-02

4.531e-02

4.779e-02

4.935e-02

5.013e-02

5.046e-02

5.063e-02

5.075e-02

5.085e-02

5.090e-02

4.771e-02

4.525e-02

4.657e-02

4.904e-02

5.221e-02

5.524e-02

5.634e-02

5.751e-02

5.634e-02

5.648e-02

5.664e-02

5.679e-02

5.693e-02

5.707e-02

5.722e-02

5.741e-02

5.766e-02

5.801e-02

5.824e-02

-2.25e-02

-1.38e-02

-8.35e-03

-2.80e-03

2.744e-03

7.871e-03

1.252e-02

1.667e-02

2.026e-02

2.324e-02

2.553e-02

2.709e-02

2.803e-02

2.851e-02

2.876e-02

2.892e-02

2.904e-02

2.912e-02

2.876e-02

2.994e-02

3.321e-02

3.570e-02

3.801e-02

4.029e-02

4.253e-02

4.463e-02

4.645e-02

4.786e-02

4.881e-02

4.912e-02

4.795e-02

4.679e-02

4.688e-02

4.700e-02

4.712e-02

4.723e-02

4.733e-02

4.737e-02

-4.28e-02

-3.12e-02

-1.91e-02

-6.52e-03

6.427e-03

1.823e-02

2.869e-02

3.776e-02

4.544e-02

5.171e-02

5.660e-02

6.023e-02

6.271e-02

6.419e-02

6.494e-02

6.525e-02

6.540e-02

6.549e-02

6.555e-02

6.561e-02

6.182e-02

6.049e-02

6.178e-02

6.450e-02

6.659e-02

6.867e-02

6.970e-02

6.938e-02

6.960e-02

6.983e-02

7.005e-02

7.026e-02

7.049e-02

7.074e-02

7.105e-02

7.147e-02

7.205e-02

7.242e-02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

2.922e-04

2.881e-04

2.853e-04

2.836e-04

2.825e-04

2.819e-04

2.815e-04

2.813e-04

2.812e-04

2.811e-04

2.810e-04

2.177e-04

2.175e-04

2.173e-04

2.172e-04

2.171e-04

2.170e-04

2.169e-04

2.167e-04

2.520e-04

3.078e-02

2.684e-02

4.123e-04

4.021e-04

3.946e-04

3.893e-04

3.857e-04

3.834e-04

3.820e-04

3.812e-04

3.808e-04

3.806e-04

3.804e-04

B-8

DSP56366 Advance Information

MOTOROLA

IBIS Model

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

2.809e-04

2.808e-04

2.997e-04

1.750e-02

1.048e-02

3.487e-03

-3.40e-03

-9.69e-03

-1.52e-02

-2.02e-02

-2.46e-02

-2.84e-02

-3.14e-02

-3.37e-02

-3.55e-02

-3.68e-02

-3.78e-02

-3.85e-02

-3.91e-02

-3.96e-02

-4.01e-02

-4.04e-02

-4.08e-02

-4.11e-02

-4.14e-02

-4.17e-02

-4.32e-02

-4.08e-01

-2.73e+01

-6.13e+01

-9.54e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.21e+02

2.277e-02

1.864e-02

1.447e-02

1.031e-02

6.181e-03

2.084e-03

-2.03e-03

-5.71e-03

-8.99e-03

-1.19e-02

-1.43e-02

-1.62e-02

-1.77e-02

-1.88e-02

-1.95e-02

-2.00e-02

-2.04e-02

-2.07e-02

-2.10e-02

-2.12e-02

-2.15e-02

-2.17e-02

-2.18e-02

-2.20e-02

-2.78e-02

-1.20e+00

-2.15e+01

-4.52e+01

-6.89e+01

-9.25e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.18e+02

3.802e-04

3.801e-04

3.799e-04

3.797e-04

3.776e-04

4.568e-03

-4.22e-03

-1.24e-02

-1.95e-02

-2.61e-02

-3.21e-02

-3.73e-02

-4.18e-02

-4.55e-02

-4.85e-02

-5.09e-02

-5.27e-02

-5.41e-02

-5.51e-02

-5.60e-02

-5.67e-02

-5.74e-02

-5.79e-02

-5.84e-02

-5.89e-02

-5.94e-02

-5.98e-02

-6.10e-02

-6.84e-02

-7.73e+00

-4.18e+01

-7.59e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.41e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

MOTOROLA

DSP56366 Advance Information

B-9

IBIS Model

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-7.83e+01

-4.43e+01

-1.02e+01

-9.69e-03

-2.83e-04

-1.35e-06

-1.31e-09

-2.92e-11

-2.44e-11

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-5.70e-03

-4.53e-05

-3.74e-07

-3.00e-09

-5.14e-10

-7.58e+01

-4.17e+01

-7.67e+00

-7.81e-03

-8.42e-04

-1.00e-05

-8.58e-09

-3.64e-11

-2.79e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.030/0.465

1.290/0.671

0.605/0.676

0.829/0.122

1.320/0.366

1.520/0.431

dV/dt_f

|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

icba_io

I/O

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-5.18e+02

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-2.70e-02

-1.32e-02

-9.33e-03

-5.75e-03

-1.97e-03

1.945e-03

5.507e-03

8.649e-03

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.19e+00

-1.25e-02

-4.69e-03

-2.81e-03

-9.48e-04

9.285e-04

2.640e-03

4.168e-03

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.68e+00

-2.90e-02

-1.63e-02

-1.10e-02

-6.76e-03

-2.32e-03

2.307e-03

6.599e-03

1.048e-02

B-10

DSP56366 Advance Information

MOTOROLA

IBIS Model

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

1.136e-02

1.364e-02

1.547e-02

1.688e-02

1.299e-01

1.366e-01

1.404e-01

1.423e-01

1.433e-01

1.440e-01

1.445e-01

1.450e-01

1.454e-01

1.458e-01

1.461e-01

1.464e-01

1.469e-01

1.490e-01

1.501e+00

1.813e+01

3.540e+01

5.269e+01

7.541e+01

1.012e+02

1.270e+02

1.527e+02

1.785e+02

2.043e+02

2.301e+02

2.559e+02

2.688e+02

5.504e-03

6.636e-03

7.551e-03

8.240e-03

6.458e-02

6.746e-02

6.916e-02

7.006e-02

7.059e-02

7.098e-02

7.128e-02

7.154e-02

7.176e-02

7.196e-02

7.223e-02

8.810e-02

2.589e+00

1.451e+01

2.658e+01

3.866e+01

5.076e+01

6.461e+01

8.261e+01

1.006e+02

1.186e+02

1.366e+02

1.546e+02

1.726e+02

1.906e+02

2.086e+02

2.176e+02

1.393e-02

1.693e-02

1.950e-02

2.162e-02

2.331e-02

1.755e-01

1.847e-01

1.907e-01

1.940e-01

1.958e-01

1.970e-01

1.979e-01

1.986e-01

1.993e-01

1.999e-01

2.004e-01

2.009e-01

2.015e-01

2.030e-01

2.385e-01

9.563e+00

2.682e+01

4.409e+01

6.258e+01

8.836e+01

1.141e+02

1.399e+02

1.657e+02

1.915e+02

2.173e+02

2.302e+02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.360e+00

4.275e-02

8.208e-03

5.635e-03

3.370e-03

1.118e-03

-1.09e-03

1.905e+02

1.725e+02

1.545e+02

1.365e+02

1.185e+02

1.005e+02

8.253e+01

6.454e+01

5.068e+01

3.859e+01

2.651e+01

1.444e+01

2.518e+00

2.012e-02

3.518e-03

2.053e-03

6.789e-04

-6.56e-04

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.362e+00

4.663e-02

1.070e-02

7.068e-03

4.233e-03

1.410e-03

-1.38e-03

MOTOROLA

DSP56366 Advance Information

B-11

IBIS Model

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-3.12e-03

-4.96e-03

-6.60e-03

-8.04e-03

-9.26e-03

-1.03e-02

-1.25e-01

-1.31e-01

-1.36e-01

-1.40e-01

-1.42e-01

-1.44e-01

-1.46e-01

-1.48e-01

-1.49e-01

-1.50e-01

-1.52e-01

-1.53e-01

-1.54e-01

-1.57e-01

-5.25e-01

-2.74e+01

-6.14e+01

-9.55e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.21e+02

-1.86e-03

-2.93e-03

-3.87e-03

-4.66e-03

-5.30e-03

-6.55e-02

-6.93e-02

-7.19e-02

-7.38e-02

-7.53e-02

-7.65e-02

-7.76e-02

-7.85e-02

-7.93e-02

-8.00e-02

-8.06e-02

-8.13e-02

-8.84e-02

-1.26e+00

-2.16e+01

-4.53e+01

-6.89e+01

-9.26e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.19e+02

-3.99e-03

-6.39e-03

-8.59e-03

-1.06e-02

-1.23e-02

-1.38e-02

-1.70e-01

-1.82e-01

-1.91e-01

-1.97e-01

-2.03e-01

-2.07e-01

-2.10e-01

-2.13e-01

-2.15e-01

-2.17e-01

-2.19e-01

-2.21e-01

-2.22e-01

-2.24e-01

-2.27e-01

-2.38e-01

-7.90e+00

-4.20e+01

-7.60e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.42e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-1.22e-02

-5.18e-04

-2.43e-06

-2.33e-09

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-6.62e-03

-6.64e-05

-6.35e-07

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-1.17e-02

-1.56e-03

-1.80e-05

-1.54e-08

B-12

DSP56366 Advance Information

MOTOROLA

IBIS Model

-1.00e-01

0.000e+00

|

-2.10e-11

-1.70e-11

-6.31e-09

-1.95e-09

-2.99e-11

-1.91e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.236e+01

4.389e+01

2.662e+01

9.358e+00

3.399e-02

3.426e-04

2.840e-06

3.401e-09

6.162e-11

5.758e-11

1.905e+02

1.725e+02

1.545e+02

1.365e+02

1.185e+02

1.005e+02

8.253e+01

6.454e+01

5.068e+01

3.859e+01

2.651e+01

1.444e+01

2.517e+00

1.577e-02

7.857e-05

6.836e-07

7.379e-09

2.438e-09

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.359e+00

3.554e-02

9.211e-04

1.655e-05

1.946e-08

7.622e-11

6.240e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.680/0.164

1.690/0.219

1.360/0.329

1.310/0.442

1.900/0.124

1.880/0.155

dV/dt_f

|

[Model]

Model_type

Polarity

C_comp

|

icba_o

3-state

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-3.65e+02

-5.18e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

MOTOROLA

DSP56366 Advance Information

B-13

IBIS Model

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-2.70e-02

-1.32e-02

-9.33e-03

-5.75e-03

-1.97e-03

1.945e-03

5.507e-03

8.649e-03

1.136e-02

1.364e-02

1.547e-02

1.688e-02

1.299e-01

1.366e-01

1.404e-01

1.423e-01

1.433e-01

1.440e-01

1.445e-01

1.450e-01

1.454e-01

1.458e-01

1.461e-01

1.464e-01

1.469e-01

1.490e-01

1.501e+00

1.813e+01

3.540e+01

5.269e+01

7.541e+01

1.012e+02

1.270e+02

1.527e+02

1.785e+02

2.043e+02

2.301e+02

2.559e+02

2.688e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.19e+00

-1.25e-02

-4.69e-03

-2.81e-03

-9.48e-04

9.285e-04

2.640e-03

4.168e-03

5.504e-03

6.636e-03

7.551e-03

8.240e-03

6.458e-02

6.746e-02

6.916e-02

7.006e-02

7.059e-02

7.098e-02

7.128e-02

7.154e-02

7.176e-02

7.196e-02

7.223e-02

8.810e-02

2.589e+00

1.451e+01

2.658e+01

3.866e+01

5.076e+01

6.461e+01

8.261e+01

1.006e+02

1.186e+02

1.366e+02

1.546e+02

1.726e+02

1.906e+02

2.086e+02

2.176e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.68e+00

-2.90e-02

-1.63e-02

-1.10e-02

-6.76e-03

-2.32e-03

2.307e-03

6.599e-03

1.048e-02

1.393e-02

1.693e-02

1.950e-02

2.162e-02

2.331e-02

1.755e-01

1.847e-01

1.907e-01

1.940e-01

1.958e-01

1.970e-01

1.979e-01

1.986e-01

1.993e-01

1.999e-01

2.004e-01

2.009e-01

2.015e-01

2.030e-01

2.385e-01

9.563e+00

2.682e+01

4.409e+01

6.258e+01

8.836e+01

1.141e+02

1.399e+02

1.657e+02

1.915e+02

2.173e+02

2.302e+02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.905e+02

1.725e+02

1.545e+02

1.365e+02

1.185e+02

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

B-14

DSP56366 Advance Information

MOTOROLA

IBIS Model

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.360e+00

4.275e-02

8.208e-03

5.635e-03

3.370e-03

1.118e-03

-1.09e-03

-3.12e-03

-4.96e-03

-6.60e-03

-8.04e-03

-9.26e-03

-1.03e-02

-1.25e-01

-1.31e-01

-1.36e-01

-1.40e-01

-1.42e-01

-1.44e-01

-1.46e-01

-1.48e-01

-1.49e-01

-1.50e-01

-1.52e-01

-1.53e-01

-1.54e-01

-1.57e-01

-5.25e-01

-2.74e+01

-6.14e+01

-9.55e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.21e+02

1.005e+02

8.253e+01

6.454e+01

5.068e+01

3.859e+01

2.651e+01

1.444e+01

2.518e+00

2.012e-02

3.518e-03

2.053e-03

6.789e-04

-6.56e-04

-1.86e-03

-2.93e-03

-3.87e-03

-4.66e-03

-5.30e-03

-6.55e-02

-6.93e-02

-7.19e-02

-7.38e-02

-7.53e-02

-7.65e-02

-7.76e-02

-7.85e-02

-7.93e-02

-8.00e-02

-8.06e-02

-8.13e-02

-8.84e-02

-1.26e+00

-2.16e+01

-4.53e+01

-6.89e+01

-9.26e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.19e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.362e+00

4.663e-02

1.070e-02

7.068e-03

4.233e-03

1.410e-03

-1.38e-03

-3.99e-03

-6.39e-03

-8.59e-03

-1.06e-02

-1.23e-02

-1.38e-02

-1.70e-01

-1.82e-01

-1.91e-01

-1.97e-01

-2.03e-01

-2.07e-01

-2.10e-01

-2.13e-01

-2.15e-01

-2.17e-01

-2.19e-01

-2.21e-01

-2.22e-01

-2.24e-01

-2.27e-01

-2.38e-01

-7.90e+00

-4.20e+01

-7.60e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.42e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-5.20e+02

-4.69e+02

-4.18e+02

-3.65e+02

-3.30e+02

-2.94e+02

-5.18e+02

-4.67e+02

-4.16e+02

MOTOROLA

DSP56366 Advance Information

B-15

IBIS Model

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-1.22e-02

-5.18e-04

-2.43e-06

-2.33e-09

-2.10e-11

-1.70e-11

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-6.62e-03

-6.64e-05

-6.35e-07

-6.31e-09

-1.95e-09

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-1.17e-02

-1.56e-03

-1.80e-05

-1.54e-08

-2.99e-11

-1.91e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.236e+01

4.389e+01

2.662e+01

9.358e+00

3.399e-02

3.426e-04

2.840e-06

3.401e-09

6.162e-11

5.758e-11

1.905e+02

1.725e+02

1.545e+02

1.365e+02

1.185e+02

1.005e+02

8.253e+01

6.454e+01

5.068e+01

3.859e+01

2.651e+01

1.444e+01

2.517e+00

1.577e-02

7.857e-05

6.836e-07

7.379e-09

2.438e-09

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.359e+00

3.554e-02

9.211e-04

1.655e-05

1.946e-08

7.622e-11

6.240e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

dV/dt_f

|

1.680/0.164

1.690/0.219

1.360/0.329

1.310/0.442

1.900/0.124

1.880/0.155

|

[Model]

Model_type

Polarity

C_comp

icbc_o

3-state

Non-Inverting

5.00pF

B-16

DSP56366 Advance Information

MOTOROLA

IBIS Model

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.42e+01

-1.02e+01

-2.51e-02

-1.30e-02

-9.33e-03

-5.75e-03

-1.97e-03

1.945e-03

5.507e-03

8.649e-03

1.136e-02

1.364e-02

1.547e-02

1.688e-02

9.632e-02

1.012e-01

1.039e-01

1.053e-01

1.060e-01

1.065e-01

1.069e-01

1.073e-01

1.076e-01

1.078e-01

1.081e-01

1.083e-01

1.086e-01

1.103e-01

1.437e+00

1.800e+01

3.519e+01

5.241e+01

7.505e+01

1.007e+02

1.264e+02

1.522e+02

1.779e+02

-3.65e+02

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.11e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-2.65e-02

-1.58e-02

-1.10e-02

-6.76e-03

-2.32e-03

2.307e-03

6.599e-03

1.048e-02

1.393e-02

1.693e-02

1.950e-02

2.162e-02

2.331e-02

1.302e-01

1.369e-01

1.412e-01

1.436e-01

1.449e-01

1.458e-01

1.464e-01

1.470e-01

1.475e-01

1.479e-01

1.483e-01

1.487e-01

1.491e-01

1.503e-01

1.810e-01

9.452e+00

2.664e+01

4.384e+01

6.224e+01

8.794e+01

1.136e+02

1.394e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.51e+01

-2.15e+01

-1.18e+00

-1.16e-02

-4.67e-03

-2.81e-03

-9.48e-04

9.285e-04

2.640e-03

4.168e-03

5.504e-03

6.636e-03

7.551e-03

8.240e-03

4.783e-02

4.994e-02

5.118e-02

5.184e-02

5.223e-02

5.251e-02

5.274e-02

5.293e-02

5.309e-02

5.324e-02

5.344e-02

6.705e-02

2.529e+00

1.438e+01

2.638e+01

3.839e+01

5.041e+01

6.419e+01

8.210e+01

1.000e+02

1.179e+02

1.359e+02

1.538e+02

MOTOROLA

DSP56366 Advance Information

B-17

IBIS Model

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

2.036e+02

2.293e+02

2.550e+02

2.678e+02

1.717e+02

1.896e+02

2.075e+02

2.165e+02

1.651e+02

1.908e+02

2.165e+02

2.293e+02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

2.677e+02

2.420e+02

2.163e+02

1.906e+02

1.649e+02

1.392e+02

1.135e+02

8.778e+01

6.208e+01

4.368e+01

2.649e+01

9.302e+00

3.838e-02

8.115e-03

5.634e-03

3.370e-03

1.118e-03

-1.09e-03

-3.12e-03

-4.96e-03

-6.60e-03

-8.04e-03

-9.26e-03

-1.03e-02

-9.03e-02

-9.49e-02

-9.84e-02

-1.01e-01

-1.03e-01

-1.05e-01

-1.06e-01

-1.07e-01

-1.08e-01

-1.09e-01

-1.10e-01

-1.11e-01

-1.14e-01

-4.76e-01

-2.73e+01

-6.14e+01

-9.54e+01

-1.38e+02

-1.89e+02

-2.40e+02

1.896e+02

1.716e+02

1.537e+02

1.358e+02

1.179e+02

9.996e+01

8.205e+01

6.413e+01

5.035e+01

3.834e+01

2.633e+01

1.433e+01

2.477e+00

1.789e-02

3.503e-03

2.053e-03

6.789e-04

-6.56e-04

-1.86e-03

-2.93e-03

-3.87e-03

-4.66e-03

-5.30e-03

-4.75e-02

-5.02e-02

-5.21e-02

-5.34e-02

-5.45e-02

-5.54e-02

-5.62e-02

-5.68e-02

-5.74e-02

-5.79e-02

-5.84e-02

-5.89e-02

-6.49e-02

-1.23e+00

-2.16e+01

-4.52e+01

-6.89e+01

-9.25e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

2.677e+02

2.420e+02

2.163e+02

1.906e+02

1.649e+02

1.392e+02

1.135e+02

8.778e+01

6.208e+01

4.368e+01

2.649e+01

9.303e+00

4.183e-02

1.045e-02

7.064e-03

4.233e-03

1.410e-03

-1.38e-03

-3.99e-03

-6.39e-03

-8.59e-03

-1.06e-02

-1.23e-02

-1.41e-02

-1.23e-01

-1.31e-01

-1.38e-01

-1.43e-01

-1.47e-01

-1.50e-01

-1.52e-01

-1.54e-01

-1.56e-01

-1.57e-01

-1.59e-01

-1.60e-01

-1.61e-01

-1.62e-01

-1.64e-01

-1.73e-01

-7.82e+00

-4.19e+01

-7.59e+01

-1.11e+02

-1.61e+02

B-18

DSP56366 Advance Information

MOTOROLA

IBIS Model

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.20e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.18e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.41e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.42e+01

-1.02e+01

-1.03e-02

-3.74e-04

-1.72e-06

-1.67e-09

-2.03e-11

-1.69e-11

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.51e+01

-2.15e+01

-1.17e+00

-5.73e-03

-5.06e-05

-4.65e-07

-4.80e-09

-1.61e-09

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.11e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.66e+00

-9.27e-03

-1.14e-03

-1.28e-05

-1.10e-08

-2.71e-11

-1.89e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.677e+02

2.420e+02

2.163e+02

1.906e+02

1.649e+02

1.392e+02

1.135e+02

8.778e+01

6.208e+01

4.368e+01

2.649e+01

9.300e+00

2.962e-02

2.501e-04

2.066e-06

2.487e-09

5.672e-11

5.334e-11

1.896e+02

1.716e+02

1.537e+02

1.358e+02

1.179e+02

9.996e+01

8.205e+01

6.413e+01

5.035e+01

3.834e+01

2.633e+01

1.433e+01

2.475e+00

1.354e-02

6.280e-05

5.128e-07

5.639e-09

1.992e-09

2.677e+02

2.420e+02

2.163e+02

1.906e+02

1.649e+02

1.392e+02

1.135e+02

8.778e+01

6.208e+01

4.368e+01

2.649e+01

9.301e+00

3.075e-02

6.708e-04

1.204e-05

1.417e-08

6.832e-11

5.783e-11

[Ramp]

R_load = 50.00

MOTOROLA

DSP56366 Advance Information

B-19

IBIS Model

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.570/0.200

1.590/0.304

1.210/0.411

1.170/0.673

1.810/0.149

1.800/0.205

dV/dt_f

|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

ipbw_i

Input

Non-Inverting

5.00pF

|

[Voltage Range]

[GND_clamp]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-5.17e+02

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.82e+01

-4.42e+01

-1.02e+01

-7.17e-03

-1.14e-04

-4.86e-07

-5.19e-10

-1.91e-11

-1.68e-11

-3.65e+02

-3.29e+02

-2.94e+02

-2.58e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.24e+01

-6.87e+01

-4.51e+01

-2.15e+01

-1.16e+00

-4.39e-03

-2.55e-05

-1.91e-07

-2.47e-09

-1.17e-09

-4.66e+02

-4.15e+02

-3.64e+02

-3.13e+02

-2.62e+02

-2.11e+02

-1.60e+02

-1.10e+02

-7.57e+01

-4.16e+01

-7.64e+00

-4.87e-03

-3.03e-04

-2.73e-06

-2.57e-09

-2.19e-11

-1.84e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

1.885e+02

1.707e+02

1.528e+02

1.350e+02

1.172e+02

9.935e+01

8.152e+01

6.369e+01

4.999e+01

3.806e+01

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

B-20

DSP56366 Advance Information

MOTOROLA

IBIS Model

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.634e+01

9.237e+00

2.454e-02

8.741e-05

6.316e-07

8.479e-10

4.420e-11

4.215e-11

2.613e+01

1.421e+01

2.430e+00

1.104e-02

4.079e-05

2.484e-07

3.001e-09

1.346e-09

2.634e+01

9.237e+00

2.488e-02

2.050e-04

2.961e-06

3.721e-09

4.943e-11

4.543e-11

|

[Model]

Model_type

Polarity

ipbw_io

I/O

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

[Voltage Range]

[Pulldown]

|voltage

|

5.00pF

3v

5.00pF

3.3v

I(typ)

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.82e+01

-4.42e+01

-1.02e+01

-3.69e-02

-2.52e-02

-1.83e-02

-1.11e-02

-3.77e-03

3.729e-03

1.076e-02

1.723e-02

2.311e-02

2.836e-02

3.292e-02

3.675e-02

3.979e-02

4.205e-02

4.347e-02

4.413e-02

4.445e-02

4.465e-02

4.479e-02

-3.65e+02

-3.29e+02

-2.94e+02

-2.58e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.24e+01

-6.87e+01

-4.51e+01

-2.15e+01

-1.17e+00

-1.67e-02

-9.77e-03

-5.89e-03

-1.98e-03

1.940e-03

5.578e-03

8.907e-03

1.191e-02

1.455e-02

1.680e-02

1.862e-02

1.997e-02

2.085e-02

2.136e-02

2.162e-02

2.176e-02

2.186e-02

2.194e-02

-5.17e+02

-4.66e+02

-4.15e+02

-3.64e+02

-3.13e+02

-2.62e+02

-2.11e+02

-1.60e+02

-1.10e+02

-7.57e+01

-4.17e+01

-7.66e+00

-3.79e-02

-2.81e-02

-2.04e-02

-1.24e-02

-4.20e-03

4.177e-03

1.216e-02

1.965e-02

2.663e-02

3.305e-02

3.887e-02

4.404e-02

4.850e-02

5.223e-02

5.518e-02

5.728e-02

5.843e-02

5.899e-02

5.931e-02

MOTOROLA

DSP56366 Advance Information

B-21

IBIS Model

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

4.492e-02

4.502e-02

4.511e-02

4.519e-02

4.526e-02

4.536e-02

4.614e-02

1.344e+00

1.783e+01

3.495e+01

5.208e+01

7.463e+01

1.002e+02

1.259e+02

1.515e+02

1.771e+02

2.027e+02

2.283e+02

2.539e+02

2.667e+02

2.200e-02

2.206e-02

2.211e-02

2.219e-02

3.324e-02

2.452e+00

1.423e+01

2.615e+01

3.808e+01

5.001e+01

6.371e+01

8.154e+01

9.937e+01

1.172e+02

1.350e+02

1.529e+02

1.707e+02

1.885e+02

2.064e+02

2.153e+02

5.953e-02

5.971e-02

5.986e-02

5.999e-02

6.010e-02

6.021e-02

6.032e-02

6.065e-02

8.548e-02

9.298e+00

2.640e+01

4.352e+01

6.184e+01

8.745e+01

1.131e+02

1.387e+02

1.643e+02

1.899e+02

2.155e+02

2.283e+02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.635e+01

9.243e+00

5.536e-02

2.847e-02

2.025e-02

1.208e-02

3.994e-03

-3.88e-03

-1.11e-02

-1.76e-02

-2.35e-02

-2.86e-02

-3.30e-02

-3.65e-02

-3.92e-02

-4.12e-02

-4.26e-02

-4.36e-02

-4.43e-02

1.885e+02

1.707e+02

1.528e+02

1.350e+02

1.172e+02

9.935e+01

8.152e+01

6.369e+01

4.999e+01

3.806e+01

2.613e+01

1.421e+01

2.435e+00

2.689e-02

1.265e-02

7.503e-03

2.474e-03

-2.38e-03

-6.76e-03

-1.06e-02

-1.40e-02

-1.69e-02

-1.93e-02

-2.10e-02

-2.22e-02

-2.29e-02

-2.35e-02

-2.38e-02

-2.42e-02

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.635e+01

9.245e+00

6.260e-02

3.437e-02

2.451e-02

1.467e-02

4.868e-03

-4.76e-03

-1.37e-02

-2.20e-02

-2.95e-02

-3.63e-02

-4.23e-02

-4.75e-02

-5.17e-02

-5.51e-02

-5.77e-02

-5.97e-02

-6.11e-02

B-22

DSP56366 Advance Information

MOTOROLA

IBIS Model

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-4.49e-02

-4.54e-02

-4.58e-02

-4.61e-02

-4.65e-02

-4.68e-02

-4.70e-02

-4.73e-02

-4.81e-02

-4.00e-01

-2.72e+01

-6.12e+01

-9.52e+01

-1.37e+02

-1.88e+02

-2.39e+02

-2.90e+02

-3.41e+02

-3.92e+02

-4.43e+02

-4.94e+02

-5.20e+02

-2.44e-02

-2.47e-02

-2.49e-02

-2.50e-02

-2.52e-02

-2.54e-02

-2.99e-02

-1.19e+00

-2.15e+01

-4.51e+01

-6.87e+01

-9.24e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.58e+02

-2.94e+02

-3.29e+02

-3.65e+02

-4.00e+02

-4.18e+02

-6.22e-02

-6.31e-02

-6.38e-02

-6.44e-02

-6.49e-02

-6.54e-02

-6.58e-02

-6.62e-02

-6.66e-02

-6.72e-02

-7.21e-02

-7.70e+00

-4.17e+01

-7.57e+01

-1.10e+02

-1.60e+02

-2.11e+02

-2.62e+02

-3.13e+02

-3.64e+02

-4.15e+02

-4.41e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.82e+01

-4.42e+01

-1.02e+01

-7.17e-03

-1.14e-04

-4.86e-07

-5.19e-10

-1.91e-11

-1.68e-11

-3.65e+02

-3.29e+02

-2.94e+02

-2.58e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.24e+01

-6.87e+01

-4.51e+01

-2.15e+01

-1.16e+00

-4.39e-03

-2.55e-05

-1.91e-07

-2.47e-09

-1.17e-09

-5.17e+02

-4.66e+02

-4.15e+02

-3.64e+02

-3.13e+02

-2.62e+02

-2.11e+02

-1.60e+02

-1.10e+02

-7.57e+01

-4.16e+01

-7.64e+00

-4.87e-03

-3.03e-04

-2.73e-06

-2.57e-09

-2.19e-11

-1.84e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.885e+02

1.707e+02

1.528e+02

1.350e+02

1.172e+02

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

MOTOROLA

DSP56366 Advance Information

B-23

IBIS Model

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.634e+01

9.237e+00

2.454e-02

8.741e-05

6.316e-07

8.479e-10

4.420e-11

4.215e-11

9.935e+01

8.152e+01

6.369e+01

4.999e+01

3.806e+01

2.613e+01

1.421e+01

2.430e+00

1.104e-02

4.079e-05

2.484e-07

3.001e-09

1.346e-09

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.634e+01

9.237e+00

2.488e-02

2.050e-04

2.961e-06

3.721e-09

4.943e-11

4.543e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.140/0.494

1.150/0.505

0.699/0.978

0.642/0.956

1.400/0.354

1.350/0.350

dV/dt_f

|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

iexlh_i

Input

Non-Inverting

5.00pF

|

[Voltage Range]

[GND_clamp]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-5.21e+02

-4.70e+02

-4.19e+02

-3.68e+02

-3.17e+02

-2.66e+02

-2.15e+02

-1.64e+02

-1.14e+02

-7.93e+01

-4.53e+01

-1.13e+01

-7.94e-03

-1.62e-06

-3.45e-10

-1.29e-11

-3.66e+02

-5.18e+02

-3.30e+02

-2.95e+02

-2.59e+02

-2.24e+02

-1.89e+02

-1.53e+02

-1.18e+02

-9.34e+01

-6.98e+01

-4.62e+01

-2.26e+01

-1.87e+00

-5.11e-03

-1.40e-05

-3.90e-08

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.11e+02

-7.68e+01

-4.28e+01

-8.78e+00

-3.77e-03

-7.69e-07

-1.72e-10

-1.38e-11

B-24

DSP56366 Advance Information

MOTOROLA

IBIS Model

-1.00e-01

0.000e+00

|

-1.10e-11

-1.01e-11

-8.67e-10

-7.13e-10

-1.19e-11

-1.10e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.653e+02

2.398e+02

2.143e+02

1.888e+02

1.633e+02

1.378e+02

1.123e+02

8.682e+01

6.133e+01

4.313e+01

2.614e+01

9.145e+00

1.797e-02

3.667e-06

7.730e-10

2.293e-11

2.096e-11

2.004e-11

1.870e+02

1.693e+02

1.516e+02

1.339e+02

1.162e+02

9.847e+01

8.076e+01

6.305e+01

4.947e+01

3.766e+01

2.585e+01

1.404e+01

2.364e+00

7.589e-03

2.072e-05

5.767e-08

1.163e-09

9.618e-10

2.653e+02

2.398e+02

2.143e+02

1.888e+02

1.633e+02

1.378e+02

1.123e+02

8.682e+01

6.133e+01

4.313e+01

2.614e+01

9.145e+00

1.797e-02

3.667e-06

7.748e-10

2.476e-11

2.278e-11

2.186e-11

[End]

MOTOROLA

DSP56366 Advance Information

B-25

THIS PAGE INTENTIONALLY LEFT BLANK

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution

P.O. Box 5405

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81-3-3440-3569

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HOME PAGE:

http://motorola.com/semiconductors

Information in this document is provided solely to enable system and software implementers to use Motorola products.

There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or

integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume

any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical

experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could

create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

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if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

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DSP56366/D

Rev. 1.5

11/2003

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DSP56366 : 24-bit Audio Digital Signal Processor

Page Contents:

The DSP56366 processor is based on the 24-bit DSP56300 architecture, and is a member of the 56300

TM

Motorola Symphony

DSP Family. It utilizes the single-instruction-per-clock-cycle DSP56300 core, while

Features

retaining code compatibility with the DSP56000 core family. The DSP56366 is targeted to applications that

require digital audio compression/decompression, sound field processing, acoustic equalization and other

digital audio algorithms.

Documentation

Tools

Applications

A general purpose DSP56366 is available as well as a multimode, multichannel audio decoder for

consumer applications such as Audio/Video (A/V) receivers, surround sound decoders, Digital Versatile

Disk (DVD) players, digital TV, and other audio applications (applicable licenses are required).

Orderable Parts


型号：	DSPD366DB1
厂家：	MOTOROLA
描述：	24-BIT, OTHER DSP 外围集成电路
文件：	总157页 (文件大小：1957K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DSPD366DB1 [MOTOROLA]

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