74LVC2G08DP [PHILIPS]
AND Gate, CMOS, PDSO8,;
| 型号： | 74LVC2G08DP |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | AND Gate, CMOS, PDSO8, PC 栅 光电二极管 逻辑集成电路 |
| 文件： | 总12页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC2G08
Dual 2-input AND gate
Product specification
2003 Aug 25
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 to 5.5 V
The 74LVC2G08 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
• 5 V tolerant inputs and outputs for interfacing with 5 V
logic
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V)
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• SOT505-2 package
The 74LVC2G08 provides the 2-input AND gate.
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
• Specified from −40 to +85 °C and −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay inputs nA, nB to
outputs nY
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ 3.2
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.2
ns
ns
ns
ns
ns
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.5
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.1
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.7
CI
input capacitance
2.5
pF
pF
CPD
power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2
14.4
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC
.
2003 Aug 25
2
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nA
nB
nY
L
L
L
H
L
L
L
H
H
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
SOT505-2
MARKING
74LVC2G08DP
−40 to +125 °C
8
TSSOP8
plastic
V08
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
3
4
5
6
7
8
1A
data input
1B
data input
2Y
data output
ground (0 V)
data input
GND
2A
2B
data input
1Y
data output
supply voltage
VCC
2003 Aug 25
3
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
handbook, halfpage
1A
1B
1
2
3
4
8
7
6
5
V
CC
handbook, halfpage
1
2
1A
1B
1Y
2Y
7
3
1Y
2B
2A
08
5
6
2A
2B
2Y
GND
MNA724
MNA723
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1
handbook, halfpage
&
&
7
3
2
handbook, halfpage
A
Y
5
6
B
MNA221
MNA725
Fig.3 Logic symbol (IEEE/IEC).
Fig.4 Logic diagram (one driver).
2003 Aug 25
4
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
5.5
UNIT
V
VI
input voltage
0
5.5
VCC
5.5
+125
20
V
VO
output voltage
active mode
0
V
Power-down mode; VCC = 0 V
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.65 to 2.7 V
ns/V
ns/V
VCC = 2.7 to 5.5 V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5
V
IIK
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
mA
V
active mode; notes 1 and 2
−0.5
VCC + 0.5
+6.5
±50
Power-down mode; notes 1 and 2 −0.5
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
VO = 0 to VCC
−
mA
mA
°C
mW
ICC, IGND
−
±100
+150
300
Tstg
PD
−65
−
Tamb = −40 to +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
2003 Aug 25
5
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C; note 1
VIH HIGH-level input voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
LOW-level input voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA
IO = 4 mA
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.08
0.14
0.19
0.37
0.43
0.45
0.3
2.7
0.4
3.0
0.55
0.55
4.5
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
1.65 to 5.5
V
CC − 0.1
−
−
V
1.65
2.3
2.7
3.0
4.5
5.5
0
1.2
1.9
2.2
2.3
3.8
−
1.53
2.13
2.50
2.60
4.10
±0.1
±0.1
−
V
IO = −8 mA
−
V
IO = −12 mA
IO = − 24 mA
IO = −32 mA
VI = 5.5 V or GND
VI or VO = 5.5 V
−
V
−
V
−
V
ILI
input leakage current
±5
±10
µA
µA
Ioff
power-off leakage
current
−
ICC
quiescent supply current VI = VCC or GND;
IO = 0
5.5
−
−
0.1
5
10
µA
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0
2.3 to 5.5
500
2003 Aug 25
6
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
TEST CONDITIONS
OTHER VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 to +125 °C
VIH HIGH-level input voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
LOW-level input voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA
IO = 4 mA
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.10
0.70
0.45
0.60
0.80
0.80
V
V
V
V
V
V
2.7
3.0
4.5
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
1.65 to 5.5
V
CC − 0.1
−
−
−
−
−
−
−
−
−
V
1.65
2.3
2.7
3.0
4.5
5.5
0
0.95
1.7
1.9
2.0
3.4
−
−
V
IO = −8 mA
−
V
IO = −12 mA
IO = − 24 mA
IO = −32 mA
VI = 5.5 V or GND
VI or VO = 5.5 V
−
V
−
V
−
V
ILI
input leakage current
±20
±20
µA
µA
Ioff
power-off leakage
current
−
ICC
quiescent supply current VI = VCC or GND;
IO = 0
5.5
−
−
−
−
40
µA
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0
2.3 to 5.5
5000
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2003 Aug 25
7
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
AC CHARACTERISTICS
GND = 0 V
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C; note 1
tPHL/tPLH
propagation delay
inputs nA, nB to outputs nY
see Figs 5 and 6
1.65 to 1.95
2.3 to 2.7
2.7
1.0
0.5
1.0
0.5
0.5
3.2
2.2
2.5
2.1
1.7
9.0
5.1
5.3
4.7
3.8
ns
ns
ns
ns
ns
3.0 to 3.6
4.5 to 5.5
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay
inputs nA, nB to outputs nY
see Figs 5 and 6
1.65 to 1.95
2.3 to 2.7
2.7
1.0
0.5
1.0
0.5
0.5
−
−
−
−
−
11.3
6.4
6.7
5.9
4.8
ns
ns
ns
ns
ns
3.0 to 3.6
4.5 to 5.5
Note
1. All typical values are measured at Tamb = 25 °C.
AC WAVEFORMS
V
handbook, halfpage
nA, nB input
I
V
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
MNA224
OL
INPUT
VCC
VM
VI
tr = tf
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
0.5 × VCC VCC
0.5 × VCC VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
4.5 to 5.5 V
0.5 × VCC VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 The inputs nA, nB to outputs nY propagation delay and the output transition times.
8
2003 Aug 25
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
tPLH/tPHL
VCC
VI
VCC
CL
RL
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
open
open
open
open
open
VCC
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
VCC
3.0 to 3.6 V
4.5 to 5.5 V
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2003 Aug 25
9
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
PACKAGE OUTLINE
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.25
0.65
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
2003 Aug 25
10
Philips Semiconductors
Product specification
Dual 2-input AND gate
74LVC2G08
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Aug 25
11
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/01/pp12
Date of release: 2003 Aug 25
Document order number: 9397 750 11849
相关型号：
74LVC2G08GM-G
IC LVC/LCX/Z SERIES, DUAL 2-INPUT AND GATE, PDSO8, 0.95 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-833-1, SON-8, Gate
NXP
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