74LVC2G08GD,125 [NXP]
74LVC2G08 - Dual 2-input AND gate SON 8-Pin;
| 型号： | 74LVC2G08GD,125 |
| 厂家： | 
NXP |
| 描述： | 74LVC2G08 - Dual 2-input AND gate SON 8-Pin 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总16页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2G08
Dual 2-input AND gate
Rev. 08 — 9 June 2008
Product data sheet
1. General description
The 74LVC2G08 provides a 2-input AND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant outputs for interfacing with 5 V logic
I High noise immunity
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC2G08DP
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G08DC −40 °C to +125 °C
74LVC2G08GT −40 °C to +125 °C
VSSOP8
XSON8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
74LVC2G08GD −40 °C to +125 °C
74LVC2G08GM −40 °C to +125 °C
XSON8U
XQFN8U
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
plastic extremely thin quad flat package; no leads;
SOT902-1
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2.
Marking codes
Type number
74LVC2G08DP
74LVC2G08DC
74LVC2G08GT
74LVC2G08GD
74LVC2G08GM
Marking code
V08
V08
V08
V08
V08
5. Functional diagram
&
&
1A
1Y
1B
2A
2Y
2B
001aah788
001aah789
Fig 1. Logic symbol
Fig 2. IEC logic symbol
A
B
Y
mna221
Fig 3. Logic diagram (one gate)
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
2 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
6. Pinning information
6.1 Pinning
74LVC2G08
1A
1B
1
2
3
4
8
7
6
5
V
CC
1Y
2B
2A
74LVC2G08
2Y
1
2
3
4
8
7
6
5
1A
1B
V
CC
1Y
2B
2A
GND
2Y
GND
001aae982
Transparent top view
001aae981
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5. Pin configuration SOT833-1 (XSON8)
74LVC2G08
terminal 1
index area
1Y
1
7
6
5
1A
1B
2Y
74LVC2G08
1A
1B
1
2
3
4
8
7
6
5
V
CC
2B
2A
2
3
1Y
2B
2A
2Y
GND
001aae983
001aai245
Transparent top view
Transparent top view
Fig 6. Pin configuration SOT996-2 (XSON8U)
Fig 7. Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2, SOT765-1,
SOT902-1
SOT833-1 and SOT996-2
1A
1
2
3
4
5
7
6
5
4
3
data input
data input
data output
ground (0 V)
data input
1B
2Y
GND
2A
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
3 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
Table 3.
Symbol
Pin description …continued
Pin
Description
SOT505-2, SOT765-1,
SOT902-1
SOT833-1 and SOT996-2
2B
6
7
8
2
1
8
data input
1Y
data output
supply voltage
VCC
7. Functional description
Table 4.
Function table[1]
Input
nA
L
Output
nB
X
nY
L
X
L
L
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−0.5
−50
-
Max
+6.5
+6.5
VCC + 0.5
+6.5
-
Unit
V
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
Active mode
V
[1][2]
Power-down mode
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
mA
mA
mA
mA
mA
°C
IOK
IO
VO < 0 V or VO > VCC
VO = 0 V to VCC
±50
±50
100
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
300
[3]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.
[3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly at 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly at 8 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly at 2.4 mW/K.
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
4 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
9. Recommended operating conditions
Table 6.
Symbol
VCC
Operating conditions
Parameter
Conditions
Min
Max
5.5
Unit
V
supply voltage
input voltage
1.65
VI
0
5.5
V
VO
output voltage
Active mode
0
VCC
5.5
V
Power-down mode
0
V
Tamb
ambient temperature
−40
+125
20
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
10
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
0.35 × VCC
0.7
0.8
0.3 × VCC
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
V
CC − 0.1
-
-
-
-
-
-
-
V
V
V
V
V
V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
1.2
1.9
2.2
2.3
3.8
1.53
2.13
2.50
2.60
4.10
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
-
-
-
-
-
-
-
-
-
0.1
V
0.08 0.45
0.14 0.3
0.19 0.4
0.37 0.55
0.43 0.55
±0.1 ±5
V
IO = 8 mA; VCC = 2.3 V
V
IO = 12 mA; VCC = 2.7 V
V
IO = 24 mA; VCC = 3.0 V
V
IO = 32 mA; VCC = 4.5 V
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
µA
µA
IOFF
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
±0.1 ±10
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
5 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ICC
∆ICC
Ci
supply current
VI = 5.5 V or GND;
V
-
0.1
10
µA
CC = 1.65 V to 5.5 V; IO = 0 A
additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
-
-
5
500
-
µA
V
input capacitance
2.5
pF
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
0.35 × VCC
0.7
0.8
0.3 × VCC
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
0.95
1.7
1.9
2.0
3.4
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.70
0.45
0.60
0.80
0.80
±20
±20
40
V
IO = 8 mA; VCC = 2.3 V
V
IO = 12 mA; VCC = 2.7 V
V
IO = 24 mA; VCC = 3.0 V
V
IO = 32 mA; VCC = 4.5 V
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
µA
µA
µA
IOFF
ICC
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
supply current VI = 5.5 V or GND;
CC = 1.65 V to 5.5 V; IO = 0 A
additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
V
∆ICC
-
-
5000
µA
V
[1] All typical values are measured at Tamb = 25 °C.
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
6 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay nA, nB to nY; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
0.5
1.0
0.5
0.5
-
3.2
2.2
9.0
5.1
5.3
4.7
3.8
-
1.0
0.5
1.0
0.5
0.5
-
11.3
6.4
6.7
5.9
4.8
-
ns
ns
ns
ns
ns
pF
VCC = 2.7 V
2.5
VCC = 3.0 V to 3.6 V
2.1
VCC = 4.5 V to 5.5 V
1.7
[3]
CPD
power dissipation per gate; VI = GND to VCC
capacitance
14.4
[1] Typical values are measured at nominal VCC and at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
V
I
V
nA, nB input
GND
M
t
t
PLH
PHL
V
OH
nY output
V
M
V
OL
mna224
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Input (nA, nB) to output (nY) propagation delays
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
7 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
Table 9.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5VCC
0.5VCC
1.5 V
1.5 V
0.5VCC
0.5VCC
0.5VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5VCC
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
VEXT = Test voltage for switching times
Fig 9. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
8 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 10. Package outline SOT505-2 (TSSOP8)
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
9 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 11. Package outline SOT765-1 (VSSOP8)
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
10 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 12. Package outline SOT833-1 (XSON8)
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
11 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
C A
C
B
b
e
L
1
y
y
w
C
1
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 13. Package outline SOT996-2 (XSON8U)
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
12 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
y
C
1
L
M
M
v
C A
C
B
4
w
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
MO-255
JEITA
05-11-25
07-11-14
SOT902-1
- - -
- - -
Fig 14. Package outline SOT902-1 (XQFN8U)
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
13 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
14. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
74LVC2G08_8
Modifications:
74LVC2G08_7
74LVC2G08_6
74LVC2G08_5
74LVC2G08_4
74LVC2G08_3
74LVC2G08_2
74LVC2G08_1
Release date
20080609
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC2G08_7
• Added type number 74LVC2G08GD (XSON8U package)
20080303
20070904
20060515
20050201
20040915
20031020
20030825
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
Product specification
-
-
-
-
-
-
-
74LVC2G08_6
74LVC2G08_5
74LVC2G08_4
74LVC2G08_3
74LVC2G08_2
74LVC2G08_1
-
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
14 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC2G08_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 9 June 2008
15 of 16
74LVC2G08
NXP Semiconductors
Dual 2-input AND gate
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 June 2008
Document identifier: 74LVC2G08_8
相关型号：
74LVC2G08GM-G
IC LVC/LCX/Z SERIES, DUAL 2-INPUT AND GATE, PDSO8, 0.95 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-833-1, SON-8, Gate
NXP
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