PI6C2520AX [PERICOM]
PLL Based Clock Driver, 6C Series, 20 True Output(s), 0 Inverted Output(s), PDSO56, PLASTIC, TSSOP-56;
| 型号： | PI6C2520AX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PLL Based Clock Driver, 6C Series, 20 True Output(s), 0 Inverted Output(s), PDSO56, PLASTIC, TSSOP-56 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C2520
Low-Noise Phase-Locked Loop
Clock Driver with 20 Clock Outputs
Product Features
Product Description
Low-Noise Phase-Locked Loop Clock Distribution.
The PI6C2520 is a low-skew, low-jitter, phase-locked loop (PLL)
clock driver, distributing low-noise clock signals for Networking
Applications. By connecting the feedback FB_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to any clock output will be nearly zero. This zero-delay
feature allows the CLK_IN input clock to be distributed, providing
5 banks of 4 clocks and an extra clock for feedback.
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction. The clock outputs track the Clock Input
modulation.
Maximumclockfrequencyof125MHz.
Zero Input-to-Output delay.
Low jitter: Cycle-to-Cycle jitter ±100ps max.
On-chip series damping resistor at clock output drivers for
low noise and EMI reduction.
For test purposes, the PLL can be bypassed by strapping AV to
ground. The PI6C2520, which allows a Spread Spectrum clock in-
CC
put, operates at 3.3V V and provides integrated series-damping
CC
Operates at 3.3V VCC
Output-to-Output skew less than 200ps.
Package: Plastic 56-pin TSSOP (A).
.
resistors that make it ideal for driving point-to-point loads. Output
signal duty cycles are adjusted to 50 percent, independent of the
duty cycle at the input clock.
Each bank of outputs can be enabled or disabled via the 1G, 2G,
3G, 4G, and 5G control inputs. When the G inputs are high, the
outputs switch in phase and frequency with CLK_IN. When the G
inputs are low, the outputs are disabled to the logic low state.
BlockDiagram
ProductPinConfiguration
1
V
V
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1G
CC
CC
Y
4
2
Y
4 0
Y
4 1
GND
GND
1 0
1Y [0:3]
3
Y
1 1
GND
GND
2G
4
4
2Y [0:3]
5
3G
4
6
Y
4 2
Y
4 3
Y
3Y [0:3]
1 2
7
Y
1 3
4G
4
8
V
V
4Y [0:3]
CC
CC
9
4G
1G
5G
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
AV
GND
AV
CC
CC
4
FB_IN
AGND
FB_OUT
GND
CLK_IN
CLK_IN
FB_IN
5Y [0:3]
56-Pin
A
AGND
5G
PLL
FB_OUT
GND
2G
AV
CC
3G
V
V
CC
CC
Y
3 0
Y
3 1
GND
GND
Y
2 0
Y
2 1
GND
GND
Y
3 2
Y
3 3
Y
2 2
Y
2 3
V
V
CC
CC
V
V
CC
CC
Y
5 3
Y
5 2
GND
Y
5 0
Y
5 1
GND
PS8435B
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PI6C2520
Low-Noise, Phase-LockedLoop
ClockDriverwith20ClockOutputs
PinFunctions
Pin Name
CLK_IN
Pin Number
Type
Description
Clock input. CLK allows spread spectrum.
12
45
I
I
FB_IN
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Output bank enable. When 1G is LOW, outputs 1Y[0:3] are disabled to
a logic low state. When 1G is HIGH, all outputs 1Y[0:3] are enabled.
1G
2G
3G
4G
5G
9
I
I
I
I
I
Output bank enable. When 2G is LOW, outputs 2Y[0:3] are disabled to
a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled.
16
41
48
14
Output bank enable. When 3G is LOW, outputs 3Y[0:3] are disabled to
a logic low state. When 3G is HIGH, all outputs 3Y[0:3] are enabled.
Output bank enable. When 4G is LOW, outputs 4Y[0:3] are disabled to
a logic low state. When 4G is HIGH, all outputs 4Y[0:3] are enabled.
Output bank enable. When 5G is LOW, outputs 5Y[0:3] are disabled to
a logic low state. When 5G is HIGH, all outputs 5Y[0:3] are enabled.
Feedback output. FB_OUT is dedicated for external feedback. FB_OUT
has an embedded series-damping resistor of the same value as the clock outputs
1Yx, 2Yx, 3Yx, 4Yx, and 5Yx.
FB_OUT
43
O
Clock outputs. These outputs provide low-skew copies of CLK.
Each output has an embedded series-damping resistor.
1Y[0:3]
2Y[0:3]
3Y[0:3]
4Y[0:3]
5Y[0:3]
2,3,6,7
O
O
O
O
O
Clock outputs. These outputs provide low-skew copies of CLK.
Each output has an embedded series-damping resistor.
18,19,22,23
39,38,35,34
55,54.51,50
26,27,30,31
Clock outputs. These outputs provide low-skew copies of CLK.
Each output has an embedded series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK.
Each output has an embedded series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK.
Each output has an embedded series-damping resistor.
Analog power supply. AV can be also used to bypass the PLL for
CC
AV
11,46
13,44
Power test purposes. When AV is strapped to ground, PLL is bypassed and
CC
CC
CLK is buffered directly to the device outputs.
AGND
Ground Analog ground. AGND provides the ground reference for the analog circuitry
1,8,17,24,25,32,33,40,
49,56
V
Power Power supply
Ground Ground
CC
4,5,10,15,20,21,28,29,
36,37,42,47,52,53
GND
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PI6C2520
Low-Noise, Phase-LockedLoop
ClockDriverwith20ClockOutputs
Absolute Maximum Ratings (Over Operating Free-Air Temperature, unless otherwise noted)
Supply voltage range, V ................................................................................................................................................... 0.5Vto4.6V
CC
(1)
Input voltage range, V
.................................................................................................................................................... 0.5Vto6.5V
I
(1,2)
Voltage range applied to any output in the high or low state, V
................................................... 0.5VtoV +0.5V
CC
O
Input clamp current, I (V <0)......................................................................................................................... 50mA
IK
I
Output clamp current, I (V <0orV >V ) ............................................................................................... ±50mA
OK
O
O
CC
Continuous output current, I (V - 0 to V )................................................................................................. ±50mA
O
O
CC
Continuous current through each V or GND .............................................................................................. ±100mA
CC
(3)
Maximum power dissipation at T = 55°C (in still air) ........................................................................................................ 0.85W
A
Storage Temperature Range, T ...................................................................................................................................65°Cto150°C
stg
Stressesbeyondthoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctional
operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure
to Absolute-Maximum-Rated conditions for extended periods may affect device reliability.
Notes:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. Thisvalueislimitedto4.6Vmaximum.
3. Maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
RecommendedOperatingConditions(4)
Symbol
VCC
VIH
VIL
Parameter
Min.
Max.
Units
Supply voltage
3
2
3.6
High-level input voltage
Low-level input voltage
Input Voltage
V
0.8
VCC
12
12
VI
0
0
IOH
IOL
High-level output current
Low-level output current
mA
°C
TA
Operating free-air temperature
70
Notes:
4. Unused inputs must be held high or low to prevent them from floating.
FunctionTable
xG
L
L
H
H
CLK_IN
xY[0:3]
FB_OUT
L
H
L
L
L
L
H
L
H
L
H
H
Note:
x is from 1 to 5
PS8435B
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PI6C2520
Low-Noise, Phase-LockedLoop
ClockDriverwith20ClockOutputs
Electrical Characteristics(Over Recommended Operating Free-air Temperature Range, unless otherwise noted)
Symbol
Test Condition
Input current at 18mA
VCC
Min.
Typ.(1) Max. Units
VIK, Input clamp voltage
3V
0.79
2.99
2.66
2.83
0.01
0.3
1.2
IOH = 100µA
Min. to Max. VCC 0.2
VOH
IOH = 12mA
2.1
3V
2.4
V
IOH = 6mA
IOL = 100µA
Min. to Max.
0.2
0.8
0.55
±5
VOL
IOL = 12mA
3V
IOL = 6mA
0.15
II, Input current
Clock input voltage = VCC or GND
Clock input voltage = VCC or GND
Input voltage = VCC or GND
Output voltage = VCC or GND
3.6V
µA
pF
ICC, Analog supply current
20
Ci
4
6
3.5
3.3V
CO
One input @ VCC 0.6V,
other inputs @ VCC or GND
∆ICC
3.3V to 3.6V
4.0
500
µA
Notes:
1. For Min. or Max. conditions, use the appropriate value specified under recommended operating conditions.
TimingRequirements(Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature).
Symbol
FCLK
Parameter
Min.
25
Max.
125
60
Units
MHz
%
Note
Clock Frequency
1
DCYI
Input clock duty cycle
40
tStabilization
Stabilization Time after power up
1
ms
(1,3)
Switching Characteristics (Over Recommended Ranges of Supply Voltage & Operating Free-Air Temperature, C = 22pF)
L
VCC = 3.3V ± 0.3V
Min.
Typ.
Max.
Parameter
phase error
From (Input)
CLK_IN↑ = 100MHz
Any Y or FBOUT
To (Output)
Units
t
FB_IN↑
170
(2)
tsk(O)
200
100
55
ps
Jitter(pk-pk)
Duty cycle
F(CLK_IN> 66MHz)
F(CLK_IN ≤ 66MHz)
F(CLK_IN > 66MHz)
100
45
Any Y or FB_OUT
%
ns
45
55
tr
tf
0.7
1.2
2.8
2.8
Measured from 20% to 80%
Notes:
1. These parameters are not production tested.
2. The t specification is only valid for equal loading of all outputs.
sk(o)
3. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
PS8435B
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PI6C2520
Low-Noise, Phase-LockedLoop
ClockDriverwith20ClockOutputs
ParameterMeasurementInformation
3V
Input
50% V
50% V
CC
CC
From Output
Under Test
0V
V
t
pd
500Ω
22pF
OH
80%
20%
80%
20%
Output
50% V
CC
V
OL
t
t
f
r
Load Circuit
Voltage Waveforms
Propagation Delay times
Notes:
1. C includes probe and jig capacitance.
L
2. All input pulses are supplied by generators having the following characteristics: CLK_IN ≤ 100MHz, Z = 50 ohms, t ≤ 1.2ns, t ≤ 1.2ns.
O
r
f
3. The outputs are measured one at a time with one transition per measurement.
CLK_IN
FB_IN
t
error
phase
FB_OUT
Any Y
t
sk(O)
Any Y
Any Y
t
sk(O)
Phase Error and Skew Calculations
PS8435B
07/25/00
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PI6C2520
Low-Noise, Phase-LockedLoop
ClockDriverwith20ClockOutputs
56-pinThinShrinkSmall-OutlinePackage(A)
56
.236
.244
6.0
6.2
1
.547 13.9
.555 14.1
SEATING PLANE
.047
Max.
1.20
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.0197
BSC
0.50
.007
.011
.002
.006
0.05
0.15
.319
BSC
0.17
0.27
8.1
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
OrderingInformation
Part Number
Ordering P/N
PI6C2520A
Package
PI6C2520
56-Pin TSSOP
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8435B
07/25/00
6
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