PI6C2952FBEX [PERICOM]
PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, LQFP-32;型号: | PI6C2952FBEX |
厂家: | PERICOM SEMICONDUCTOR CORPORATION |
描述: | PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, LQFP-32 时钟驱动器 |
文件: | 总6页 (文件大小:72K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PI6C2952
Low Voltage PLL Clock Driver
Features
Description
• ±100psCycle-to-CycleJitter
• FullyIntegratedPLL
ThePI6C2952isa3.3Vcompatible,PLL-basedclockdriverdevice
targeted for high-performance clock applications. The device fea-
tures a fully integrated PLL with no external components
required. With output frequencies up to 180MHz and eleven low-
skew outputs, the PI6C2952 is well suited for high-performance
designs. The device employs a fully differential PLL design to
optimize jitter and noise rejection performance.
• Output Frequency up to 180MHz
• High-Impedance Disabled Outputs
• CompatiblewithPowerPC,Intel,andHigh-Performance
RISC Microprocessors
The PI6C2952 features three banks of individually configurable
outputs. The banks contain 5 outputs, 4 outputs, and 2 outputs. The
internaldividecircuitryallowsforoutputfrequencyratiosof 1:1,2:1,
3:1,and3:2:1.Theoutputfrequencyrelationshipiscontrolledbythe
fsel frequency control pins. The fsel pins and other inputs are
LVCMOS/LVTTLcompatibleinputs.
• Configurable Output Frequency
• 32-PinLQFPPackage(FB)
PinConfiguration
The PI6C2952 uses external feedback to the PLL. This features
allows the device to be used as a “zero delay” buffer. Any of the
elevenoutputscanbeusedasfeedbacktothePLL.TooptimizePLL
stability and jitter performance,the VCO_Sel pin allows for the
choice of two VCO ranges. For board level test, the MR/OE pin
allows a user to force the outputs into high impedance. For system
debug,thePI6C2952’sPLLcanbebypassed.Whenforcedtoalogic
HIGH, the PL_LEN input routes the signal on the RefClk input
around the PLL directly to the internal dividers. Because the signal
is routed through the dividers, it may take several transitions of the
RefClk to affect a transition on the outputs. This features allows a
designer to single step the design for debug purposes.
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
VCCO
Qa2
VCCO
Qb2
25
26
27
28
29
30
31
32
Qa1
Qb3
32-Pin
FB
GNDO
Qa0
GNDO
GNDO
Qc0
VCCI
VCCA
PLL_En
Qc1
VCCO
1
2
3
4
5
6 7 8
ThePI6C2952’soutputsareLVCMOSwhichareoptimallydesigned
todriveterminatedtransmissionlines.Forapplicationsusingseries-
terminatedtransmissionlines,eachPI6C2952outputcandrivetwo
lines. This capability provides an effective fanout of 22, more than
enough clocks for most clock tree designs.
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PI6C2952
LowVoltagePLLClockDriver
BlockDiagram
(Int Pull Down)
PLL_En
REFCLK
Qa0
Qa1
÷4/÷6
Phase
Detector
÷2
VCO
200-480MHz
FBIn
Qa2
Qa3
LPF
(Int Pull Down)
VCO_Sel
fsela
(Int Pull Down)
Qa4
Qb0
Qb1
÷4/÷2
÷2/÷4
Qb2
Qb3
(Int Pull Down)
fselb
Qc0
"–1" Has ÷2/÷8
"–2" Has ÷4/÷8
Qc1
(Int Pull Down)
(Int Pull Down)
fselc
MR/OE
FunctionTables
fsela
Qan
fselb
Qbn
fselc
Qcn
Pin Name
VCCA
VCCO
VCCI
Description
PLL Power Supply
0
1
÷4
÷6
0
1
÷4
÷2
0
1
÷2
÷4
Output Buffer Power Supply
Internal Core Logic Power Supply
Internal Ground
Control Pin
Logic 'O'
Logic '1'
fVCO/2
High Z
GNDI
VCO_Sel
MR/OE
fVCO
GNDO
Output Buffer Ground
Output Enable
Enable PLL
PLL_En
Disable PLL
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PI6C2952
LowVoltagePLLClockDriver
AbsoluteMaximumRatings*
Symbol
Parameters
Min.
–0.3
–0.3
Max.
Units
V
CC
Supply Voltage
Input Voltage
Input Current
4.6
V
V
I
V
+ 0.3
DD
I
IN
±20
125
mA
°C
T
STOR
Storage Temperature Range
–40
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
DC Characteristics (T = 0°C to 70° C, V = 3.3V± 5%)
A
CC
Symbol
Conditions
Characteristic
Min.
Typ
Max.
3.6
Units
V
IH
Input HIGH Voltage
2.0
V
Input LOW Voltage
0.8
IL
V
V
OH
I
= 20mA (Note1.)
= 20mA (Note1.)
OL
Output HIGH Voltage
Output LOW Voltage
Input Current
2.4
OH
V
I
I
0.5
±120
4.0
OL
Note 2.
μΑ
IN
C
Input Capacitance
2.7
25
IN
pF
C
Power Dissipation Capacitance
Maximum Quiescent Supply Current
PLL Supply Current
PD
I
CC
Total ICC Static Current
160
20
mA
I
15
CCA
Notes:
1. The PI6C2952 outputs can drive series- or parallel-terminated 50 ohms (or 50 ohms to V /2) transmission lines on the incident
CC
edge (see Applications Info section).
2. Inputs have pull–up, pull–down resistors that affect input current.
PLL Input Reference Characteristics (T = 0°C to 70°C)
A
Symbol
Parameters
Min.
Max.
3.0
Units
ns
Condition
tr, tf
TCLK Input Rise/Falls
f
Reference Input Frequency
Reference Input Duty Cycle
Note 3
25
Note 3
75
MHz
%
ref
f
refDC
3. Maximum and minimum input reference is limited by the V lock range and the feedback divider.
CO
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PI6C2952
LowVoltagePLLClockDriver
AC Characteristics (T =0°C to 70°C, V = 3.3V± 5%)
A
CC
Symbol
t , t
Characteristics
Conditions
0.8 to 2.0V
Min.
Typ.
Max.
Units
Output Rise/Fall Time (Note 4.)
Output Pulse Width (Note 4.)
0.10
1.0
ns
r
f
t
/2
t
/2
t
/2
CYCLE
CYCLE
–750
CYCLE
±500
I
PW
+750
ps
Output-to-Output Skew Excluding Qa0 (Note 4.) Same Frequencies
350
450
550
t
OS
All Outputs
All Outputs
Same Frequencies
Different Frequencies
PLL VCO Lock Range Feedback = VCO/4
Feedback = VCO/6
VCO_Sel = 0
VCO_Sel = 0
VCO_Sel = 1
VCO_Sel = 1
200
200
200
200
480
480
480
480
f
VCO
Feedback = VCO/8
Feedback = VCO/12
MHz
Maximum Output Frequency
Qc,Qb (÷2)
Qa,Qb,Qc (÷4)
Qa (÷6)
180
120
80
f
max
(Note 4.)
t
REFCLK to FB Delay
Notes 4 and 5.
–200
0
200
8
ps
ns
pd
IN
t
, t
Output Disable Time
50ohms to V /2
2
2
PLZ PHZ
CC
t
, t
Output Enable Time
50ohms to V /2
10
PZL PZH
CC
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
Maximum PLL Lock Time
Long term Period Jitter
±100
ps
ms
ps
t
Note 5.
10
lock
t
JP
TBD
4. 50 ohms to V /2.
CC
5. t is specified for 50 MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input
pd
reference periods. The t does not include jitter.
pd
ApplicationsInformation
DrivingTransmissionLines
PI6C2952
Output
Buffer
The PI6C2952 clock driver was designed to drive high-speed
signalsinaterminatedtransmissionlineenvironment.Toprovide
the optimum flexibility to the user, the output drivers were
designedtoexhibitthelowestimpedancepossible.Withanoutput
impedance of less than 10 ohms, the drivers can drive either
parallel- or series-terminated transmission lines.
Z
= 50 ohms
O
R = 43 ohms
S
7 ohms
OutA
IN
PI6C2952
Output
Z
= 50 ohms
O
R = 43 ohms
S
Buffer
OutB0
OutB1
7 ohms
IN
Z
= 50 ohms
O
R = 43 ohms
S
Figure 3. Single versus Dual Transmission Lines
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PI6C2952
LowVoltagePLLClockDriver
In most high performance clock networks point–to–point distribu-
tion of signals is the method of choice. In a point–to–point scheme
eitherseriesterminatedorparallelterminatedtransmissionlinescan
be used. The parallel technique terminates the signal at the end of
Sincethisstepiswellabovethethresholdregionitwillnotcauseany
falseclocktriggering,howeverdesignersmaybeuncomfortablewith
unwanted reflections on the line. To better match the impedances
whendrivingmultiplelinesthesituationinFigure5shouldbeused.
In this case the series terminating resistors are reduced such that
when the parallel combination is added to the output buffer imped-
ance the line impedance is perfectly matched.
the line with a 50ohm resistance to V /2. This technique draws a
CC
fairlyhighlevelofDCcurrentandthusonlyasingleterminatedline
can be driven by each output of the PI6C2952 clock driver. For the
seriesterminatedcasehoweverthereisnoDCcurrentdraw,thusthe
outputscandrivemultipleseriesterminatedlines.Figure3illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fanout of
thePI6C2952clockdriveriseffectivelydoubledduetoitscapability
to drive multiple lines.
PI6C2952
Output
Z
= 50 ohms
= 50 ohms
Buffer
R
= 36 ohms
O
S
7ohms
Z
O
R
= 36 ohms
S
The waveform plots of Figure 4 show the simulation results of an
output driving a single line vs two lines. In both cases the drive
capability of the PI6C2952 output buffers is more than sufficient to
drive50-ohmtransmissionlinesontheincidentedge.Notefromthe
delay measurements in the simulations a delta of only 43ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output–to–output skew of the PI6C2952. The output waveform in
Figure 4 shows a step in the waveform, this step is caused by the
impedance mismatch seen looking into the driver. The parallel
combinationofthe43ohm seriesresistor plustheoutputimpedance
doesnotmatchtheparallelcombinationofthelineimpedances.The
voltage wave launched down the two lines will equal:
7 ohms + 36 ohms⏐ 36 ohms = 50 ohms ⏐ 50 ohms
25 ohms = 25 ohms⏐
Figure5.OptimizedDualLineTermination
SPICE level output buffer models are available for engineers who
want to simulate their specific interconnect schemes. In addition IV
characteristics are in the process of being generated to support the
other board level simulators in general use.
Power Supply Filtering
ThePI6C2952isamixedanalog/digitalproductandassuchitexhibits
some sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to random
noise, especially if this noise is seen on the power supply pins. The
PI6C2952 provides separate power supplies for the output buffers
VL=VS(Zo/Rs+Ro+Zo)=3.0(25/53.5)=1.40V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.8V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in this
case 4.0ns).
(V
)andtheinternalPLL(V )ofthedevice.Thepurposeofthis
CCA
CCO
designtechniqueistotryandisolatethehighswitchingnoisedigital
outputs from the relatively sensitive internal analog phase–locked
loop. In a controlled environment such as an evaluation board this
levelofisolationissufficient. However, inadigitalsystemenviron-
mentwhereitismoredifficulttominimizenoiseonthepowersupplies
a second level of isolation may be required. The simplest form of
trip delay (In this example: 4.0ns)
3.0
OutA
= 3.8956
OutB
= 3.9386
t
2.5
2.0
1.5
1.0
0.5
0
D
t
D
isolation is a power supply filter on the V
pin for the PI6C2952.
CCA
3.3V
In
R
S
= 5-15 ohms
VCCA
PI6C2952
0.01µF
22µF
VCC
14
6
8
10
12
2
4
0.01µF
TIME (ns)
Figure4. SingleversusDualWaveforms
Figure6.PowerSupplyFilter
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PI6C2952
LowVoltagePLLClockDriver
32-PinLQFP(FB)Package
9.00
BSC
.354
Square
0.09
0.20
Square
7.00 BSC
.276
.004
.008
GAUGE PLANE
0
7
1.60
Max.
0.45
0.75
.018
.030
.063
1.00 REF
.039
.004
0.10
Seating Plane
1.35
1.45
0.05
0.15
0.30
0.45
0.80 BSC
.032
.012
.018
.053
.057
.002
.006
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
(1,2,3)
OrderingInformation
Part Number
PI6C2952FB
Package
Operating Temperature
PI6C2952FBE
PI6C2952-1FB
PI6C2952-2FB
Notes:
32-LQFP
Commercial
1. Thermal Characteristics can be found on the company website and www.pericom.com/packaging/
2. E = Pb-free and Green
3. X suffix = Tape/Reel
PericomSemiconductorCorporation
2380BeringDrive • SanJose, CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com
PS8542A
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