2N7002KDW_10 [PANJIT]
60V N-Channel Enhancement Mode MOSFET - ESD Protected; 60V N沟道增强型MOSFET - ESD保护
| 型号： | 2N7002KDW_10 |
| 厂家： | 
PAN JIT INTERNATIONAL INC. |
| 描述： | 60V N-Channel Enhancement Mode MOSFET - ESD Protected |
| 文件： | 总5页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2N7002KDW
60V N-Channel Enhancement Mode MOSFET - ESD Protected
SOT-363
Unit: inch (mm)
FEATURES
• RDS(ON), VGS@10V,IDS@500mA=3Ω
• RDS(ON), VGS@4.5V,IDS@200mA=4Ω
0.054(1.35)
0.045(1.15)
• Advanced Trench Process Technology
• High Density Cell Design For Ultra Low On-Resistance
• Very Low Leakage Current In Off Condition
• Specially Designed for Battery Operated Systems, Solid-State Relays
Drivers : Relays, Displays, Lamps, Solenoids, Memories, etc.
• ESD Protected 2KV HBM
0.040(1.00)
0.031(0.80)
• In compliance with EU RoHS 2002/95/EC directives
0.10 MAX.
0.018(0.45)
0.006(0.15)
MECHANICALDATA
0.087(2.20)
0.078(2.00)
• Case: SOT-363 Package
6
1
5
2
4
3
• Terminals : Solderable per MIL-STD-750,Method 2026
• Marking : K27
Maximum RATINGS and Thermal Characteristics (TA=25OC unless otherwise noted )
PARAMETER
Drain-Source Voltage
Symbol
VDS
Limit
60
Units
V
Gate-Source Voltage
VGS
ID
+20
115
800
V
Continuous Drain Current
mA
mA
1)
Pulsed Drain Current
IDM
TA=25OC
TA=75OC
200
120
Maximum Power Dissipation
PD
TJ,TSTG
RθJA
mW
OC
Operating Junction and Storage
Temperature Range
-55 to + 150
625
Junction-to Ambient Thermal
Resistance(PCB mounted)2
OC/W
Note: 1. Maximum DC current limited by the package
2. Surface mounted on FR4 board, t < 5 sec
PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE
May 21.2010-REV.01
PAGE . 1
2N7002KDW
ELECTRICALCHARACTERISTICS
Parameter
Static
Symbol
Test Condition
Min.
Typ.
Max.
Units
Drain-Source Breakdown
Voltage
BVDSS
VGS(th)
RDS(on)
RDS(on)
IDSS
VGS=0V, ID=10uA
VDS=VGS, ID=250uA
VGS=4.5V, I D=200mA
VGS=10V, I D=500mA
VDS=60V, VGS=0V
60
-
-
-
-
-
-
-
-
2.5
4.0
3.0
1
V
V
Gate Threshold Voltage
1
Drain-Source On-State
Resistance
-
Ω
Drain-Source On-State
Resistance
-
Zero Gate Voltage Drain
Current
-
-
uA
uA
Gate Body Leakage
Forward Transconductance
Dynamic
IGSS
VGS=+20V, VDS=0V
VDS=15V, ID=250mA
+10
-
gfS
100
mS
VDS=15V, ID=200mA
VGS=4.5V
Total Gate Charge
Qg
-
-
0.8
nC
ns
Turn-On Delay Time
Turn-Off Delay Time
Input Capacitance
Output Capacitance
ton
toff
-
-
-
-
-
-
-
-
-
-
20
40
35
10
5
VDD=30V , RL=150Ω
ID=200mA , VGEN=10V
RG=10Ω
Ciss
Coss
Crss
VDS=25V, VGS=0V
f=1.0MHZ
pF
Reverse Transfer
Capacitance
Source-Drain Diode
Diode Forward Voltage
VSD
Is
IS=200mA , VGS=0V
-
-
-
0.82
1.3
115
800
V
Continuous Diode Forward
Current
-
-
-
-
mA
mA
Pulsed Diode Forward
Current
IsM
V
DD
V
DD
Switching
Gate Charge
Test Circuit
Test Circuit
RL
RL
V
IN
V
GS
V
OUT
1mA
RG
RG
May 21.2010-REV.01
PAGE . 2
2N7002KDW
Typical CChhaarraacctteerriissttiiccss Curves (TA=25OC,unless otherwise noted)
1.2
1
1.2
V
DS=10V
= 10V ~ 6.0V
GS
5.0V
1
0.8
0.6
0.4
0.2
0
4.0V
0.8
0.6
0.4
0.2
0
4.0V
T
J
=25℃
3.0V
3.0V
0
1
2
3
4
5
6
0
1
2
3
4
5
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
FIG.1-Output
Characteristic
FIG.2- Transfer Characteristic
5
4
3
2
1
0
5
4
3
2
1
0
VGS = 4.5V
ID =500mA
ID=200mA
V
GS=10V
2
3
4
5
6
7
8
9
10
0
0.2
0.4
0.6
0.8
1
VGS - Gate-to-Source Voltage (V)
ID - Drain Current (A)
FIG.3- On Resistance vs Drain Current
FIG.4- On Resistance vs Gate to Source Voltage
1.8
VGS =10V
ID =500mA
1.6
1.4
1.2
1
0.8
0.6
-50 -25
0
25
50
75 100 125 150
TJ - Junction Temperature (oC)
FIG.5- On Resistance vs Junction Temperature
May 21.2010-REV.01
PAGE . 3
2N7002KDW
10
8
V
DS=10V
Vgs
I
D
=250mA
Qg
6
4
2
Qsw
Vgs(th)
Qg(th)
0
0
0.2
0.4
0.6
0.8
1
Qg - Gate Charge (nC)
Qgs
Qgd
Qg
Fig.6 - Gate Charge Waveform
Fig.7 - Gate Charge
1.2
88
ID =250mA
ID = 250uA
86
84
82
80
78
76
74
72
1.1
1
0.9
0.8
0.7
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
TJ - Junction Temperature (oC)
TJ - Junction Temperature (oC)
Fig.8 - Threshold Voltage vs Temperature
Fig.9 - Breakdown Voltage vs Junction Temperature
10
V
GS=0V
1
25
℃
0.1
T
J
=125℃
-55℃
0.01
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VSD - Source-to-Drain Voltage (V)
Fig.10 - Source-Drain Diode Forward Voltage
May 21.2010-REV.01
PAGE . 4
2N7002KDW
MOUNTING PAD LAYOUT
ORDER INFORMATION
• Packing information
T/R - 10K per 13" plastic Reel
T/R - 3K per 7” plastic Reel
LEGAL STATEMENT
Copyright PanJit International, Inc 2010
The information presented in this document is believed to be accurate and reliable. The specifications and information herein
are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit
does not convey any license under its patent rights or rights of others.
May 21.2010-REV.01
PAGE . 5
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