PMS164 [PADAUK]
12 Touch Keys OTP Controller;型号: | PMS164 |
厂家: | PADAUK Technology |
描述: | 12 Touch Keys OTP Controller |
文件: | 总74页 (文件大小:1407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PMS164
12 Touch Keys OTP Controller
Datasheet
Version 0.00 – March 25, 2020
Copyright 2020 by PADAUK Technology Co., Ltd., all rights reserved
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688 www.padauk.com.tw
PMS164
12 Touch Keys OTP Controller
Table of Contents
1. Features...............................................................................................................................6
1.1.
1.2.
1.3.
1.4.
Special Features ...................................................................................................................6
System Features...................................................................................................................6
CPU Features .......................................................................................................................6
Package Information .............................................................................................................6
2. General Description and Block Diagram ..........................................................................7
3. Pin Definition and Functional Description........................................................................8
4. Device Characteristics .....................................................................................................13
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
DC/AC Characteristics ........................................................................................................13
Absolute Maximum Ratings.................................................................................................14
Typical IHRC Frequency vs. VDD (calibrated to 16MHz).....................................................15
Typical ILRC Frequency vs. VDD........................................................................................15
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)........................................16
Typical ILRC Frequency vs. Temperature ...........................................................................16
Typical Operating Current vs. VDD and CLK=IHRC/n.........................................................17
Typical Operating Current vs. VDD and CLK=ILRC/n..........................................................17
Typical IO pull high resistance.............................................................................................18
4.10. Typical IO driving current (IOH) and sink current (IOL) ...........................................................18
4.11. Typical IO input high/ low threshold voltage (VIH/ VIL) ..........................................................20
4.12. Typical power down current (IPD) and power save current (IPS)............................................20
5. Functional Description.....................................................................................................21
5.1.
5.2.
5.3.
5.4.
Program Memory – OTP .....................................................................................................21
Boot Up...............................................................................................................................21
Data Memory – SRAM ........................................................................................................22
Oscillator and clock.............................................................................................................22
5.4.1. Internal High RC oscillator and Internal Low RC oscillator ......................................22
5.4.2. IHRC calibration .....................................................................................................22
5.4.3. IHRC Frequency Calibration and System Clock......................................................23
5.4.4. System Clock and LVR levels.................................................................................24
5.4.5. System Clock Switching..........................................................................................25
Comparator.........................................................................................................................26
5.5.1. Internal reference voltage (Vinternal R)........................................................................27
5.5.2. Using the comparator .............................................................................................29
5.5.
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PMS164
12 Touch Keys OTP Controller
5.5.3. Using the comparator and Bandgap 1.20V .............................................................30
16-bit Timer (Timer16).........................................................................................................31
Watchdog Timer..................................................................................................................32
Interrupt...............................................................................................................................33
Power-Save and Power-Down ............................................................................................36
5.9.1. Power-Save mode (“stopexe”)................................................................................36
5.9.2. Power-Down mode (“stopsys”)................................................................................37
5.9.3. Wake-up.................................................................................................................38
5.6.
5.7.
5.8.
5.9.
5.10. IO Pins................................................................................................................................38
5.11. Reset ..................................................................................................................................39
5.12. 8-bit Timer (Timer2/Timer3) with PWM generation..............................................................40
5.12.1. Using the Timer2 to generate periodical waveform .................................................41
5.12.2. Using the Timer2 to generate 8-bit PWM waveform................................................42
5.12.3. Using the Timer2 to generate 6-bit PWM waveform................................................44
5.13. Touch Function ...................................................................................................................45
6. IO Registers.......................................................................................................................47
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
ACC Status Flag Register (flag), IO address = 0x00 ...........................................................47
Stack Pointer Register (sp), IO address = 0x02...................................................................47
Clock Mode Register (clkmd), IO address = 0x03................................................................47
Interrupt Enable Register (inten), IO address = 0x04...........................................................48
Interrupt Request Register (intrq), IO address = 0x05 .........................................................48
Timer 16 mode Register (t16m), IO address = 0x06............................................................49
MISC Register (misc), IO address = 0x08 ...........................................................................49
External Oscillator setting Register (eoscr, write only), IO address = 0x0a..........................49
Interrupt Edge Select Register (integs), IO address = 0x0c.................................................50
6.10. Port A Digital Input Enable Register (padier), IO address = 0x0d ........................................50
6.11. Port B Digital Input Enable Register (pbdier), IO address = 0x0e ........................................51
6.12. Port A Data Registers (pa), IO address = 0x10 ...................................................................51
6.13. Port A Control Registers (pac), IO address = 0x11..............................................................51
6.14. Port A Pull-High Registers (paph), IO address = 0x12.........................................................51
6.15. Port B Data Registers (pb), IO address = 0x14 ...................................................................51
6.16. Port B Control Registers (pbc), IO address = 0x15..............................................................51
6.17. Port B Pull-High Registers (pbph), IO address = 0x16.........................................................51
6.18. Comparator Control Register (gpcc), IO address = 0x18.....................................................52
6.19. Comparator Selection Register (gpcs), IO address = 0x19..................................................52
6.20. Reset Status Register (rstst), IO address = 0x1b ................................................................53
6.21. Timer2 Control Register (tm2c), IO address = 0x1c.............................................................53
6.22. Timer2 Counter Register (tm2ct), IO address = 0x1d ..........................................................54
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12 Touch Keys OTP Controller
6.23. Timer2 Scalar Register (tm2s), IO address = 0x17..............................................................54
6.24. Timer2 Bound Register (tm2b), IO address = 0x09 .............................................................54
6.25. Timer3 Control Register (tm3c), IO address = 0x32 ............................................................54
6.26. Timer3 Counter Register (tm3ct), IO address = 0x33 ..........................................................55
6.27. Timer3 Scalar Register (tm3s), IO address = 0x34..............................................................55
6.28. Timer3 Bound Register (tm3b), IO address = 0x35 .............................................................55
6.29. Touch Selection Register (ts), IO address = 0x20 ...............................................................55
6.30. Touch Charge Control Register (tcc), IO address = 0x21....................................................56
6.31. Touch Key Enable 2 Register (tke2), IO address = 0x22.....................................................56
6.32. Touch Key Enable 1 Register (tke1), IO address = 0x24.....................................................56
6.33. Touch Key Charge Counter High Register (tkch), IO address = 0x2B .................................56
6.34. Touch Key Charge Counter Low Register (tkcl), IO address = 0x2C...................................56
7. Instructions .......................................................................................................................57
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
Data Transfer Instructions ...................................................................................................58
Arithmetic Operation Instructions ........................................................................................60
Shift Operation Instructions .................................................................................................62
Logic Operation Instructions................................................................................................63
Bit Operation Instructions....................................................................................................65
Conditional Operation Instructions.......................................................................................66
System control Instructions .................................................................................................67
Summary of Instructions Execution Cycle ...........................................................................68
Summary of affected flags by Instructions...........................................................................69
7.10. BIT definition .......................................................................................................................69
8. Code Option Table............................................................................................................70
9. Special Notes ....................................................................................................................71
9.1.
9.2.
Warning...............................................................................................................................71
Using IC..............................................................................................................................71
9.2.1. IO pin usage and setting.........................................................................................71
9.2.2. Interrupt..................................................................................................................71
9.2.3. System clock switching...........................................................................................72
9.2.4. Power down mode, wakeup and watchdog.............................................................72
9.2.5. TIMER time out.......................................................................................................72
9.2.6. IHRC.......................................................................................................................72
9.2.7. LVR ........................................................................................................................73
9.2.8. Programming Writing..............................................................................................73
Using ICE............................................................................................................................74
9.3.
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
Revision History:
Revision
Date
2020/03/25 Preliminary version
Description
0.00
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
1. Features
1.1. Special Features
Not supposed to use in AC RC step-down powered or high EFT requirement applications.
PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.
Operating temperature range: -20°C ~ 70°C
1.2. System Features
1.75KW OTP program memory
128 Bytes data RAM
Maximum 12 IO pins can be selected as TOUCH PAD individually
One hardware 16-bit timer
Two hardware 8-bit timers with 6/7/8-bit PWM generation
One hardware comparator
14 IO pins with optional pull-high resistor
Bandgap circuit to provide 1.20V Bandgap voltage
Clock sources: internal high RC oscillator and internal low RC oscillator
Eight Levels of LVR reset: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V
Three selectable external interrupt pins
1.3. CPU Features
Operating modes: One processing unit mode
82 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer to provide adjustable stack level (Using 2 bytes SRAM for one stack level)
Direct and indirect addressing modes for data and instructions
All data memories are available for use as an index pointer
Separated IO and memory space
1.4. Package Information
PMS164-2N06: DFN (2*2mm)
PMS164-U06: SOT23-6 (60mil)
PMS164-S08A: SOP8 (150mil)
PMS164-S08B: SOP8 (150mil)
PMS164-2N08: DFN (2*2mm)
PMS164-EY10B: ESSOP10 (150mil)
PMS164-S16: SOP16 (150mil)
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
2. General Description and Block Diagram
The PMS164 is a fully static, OTP-based 8 bit CMOS MCU; it employs RISC architecture and most the
instructions are executed in one cycle except that few instructions are two cycles that handle indirect memory
access.
A maximum 12 keys touch controller is built inside PMS164. Besides, PMS164 also includes 1.75KW OTP
program memory, 128 bytes data SRAM, one hardware 16-bit timer and two hardware 8-bit Timer2 & Timer3
with PWM generation.
Fig. 1: PMS164 Block Diagram
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PMS164
12 Touch Keys OTP Controller
3. Pin Definition and Functional Description
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
Pin &
Pin Name
Description
Buffer Type
This pin can be used as:
(1) Bit 6 of port A. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
IO
PA6 /
TK8
ST /
CMOS /
Analog
(2) Touch Key 8
When this pin is configured as analog input, please use bit 6 of register padier to
disable the digital input to prevent leakage current.
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
Pin &
Pin Name
Description
Buffer Type
This pin can be used as:
(1) Bit 5 of port A. It can be configured as digital input or open-drain output , with
pull-high resistor.
PA5 /
INT0 /
PRSTB /
VPP
IO
ST /
(2) Optional external interrupt line 0. Both rising edge and falling edge are
accepted to request interrupt service.
CMOS
(3) External reset pin
(4) VPP for OTP programming
This pin can be used as:
(1) Bit 4 of port A. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) Touch Key 6
IO
PA4 /
TK6 /
CIN-
ST /
CMOS /
Analog
(3) Minus input source of comparator.
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent leakage current.
This pin can be used as:
(1) Bit 3 of port A. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) PWM output of Timer2
IO
PA3 /
PWM1 /
TK5 /
ST /
CMOS /
Analog
(3) Touch Key 5
CIN-
(4) Minus input source of comparator.
When this pin is configured as analog input, please use bit 3 of register padier to
disable the digital input to prevent leakage current.
This pin can be used as:
(1) Bit 0 of port A. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
IO
PA0 /
INT0 /
TK7
ST /
(2) Optional external interrupt line 0. Both rising edge and falling edge are
accepted to request interrupt service.
CMOS /
Analog
(3) Touch Key 7
When this pin is configured as analog input, please use bit 0 of register padier to
disable the digital input to current leakage current.
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
Pin &
Pin Name
Description
Buffer Type
This pin can be used as:
(1) Bit 0 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
IO
PB0 /
INT1 /
TK11
(2) External interrupt line 1. Both rising edge and falling edge are accepted to
request interrupt service.
ST /
CMOS /
Analog
(3) Touch Key 11
When this pin is configured as analog input, please use bit 0 of register pbdier to
disable the digital input to current leakage current.
This pin can be used as:
(1) Bit 1 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
IO
PB1 /
TK12
ST /
CMOS /
Analog
(2) Touch Key 12
When this pin is configured as analog input, please use bit 1 of register pbdier to
disable the digital input to current leakage current.
This pin can be used as:
(1) Bit 2 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) PWM output of Timer2
IO
PB2 /
PWM1 /
TK9
ST /
CMOS /
Analog
(3) Touch Key 9
When this pin is configured as analog input, please use bit 2 of register pbdier to
disable the digital input to prevent leakage current.
This pin can be used as:
(1) Bit 3 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
IO
PB3 /
TK10
ST /
CMOS /
Analog
(2) Touch Key 10
When this pin is configured as analog input, please use bit 3 of register pbdier to
disable the digital input to prevent leakage current.
This pin can be used as:
(1) Bit 4 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) PWM output of Timer2.
IO
PB4 /
PWM1 /
TK1
ST /
CMOS /
Analog
(3) Touch Key 1
When this pin is configured as analog input, please use bit 4 of register pbdier to
disable the digital input to prevent leakage current.
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
Pin &
Pin Name
Description
Buffer Type
This pin can be used as:
(1) Bit 5 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
PB5 /
PWM2 /
TK2
IO
ST / CMOS /
Analog
(2) PWM output of Timer3.
(3) Touch Key 2
When this pin is configured as analog input, please use bit 5 of register pbdier to
disable the digital input to prevent leakage current.
This pin can be used as:
(1) Bit 6 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) PWM output of Timer3.
PB6 /
PWM2 /
TK3 /
IO
ST /
CMOS /
Analog
(3) Touch Key 3
CIN-
(4) Minus input source of comparator.
When this pin is configured as analog input, please use bit 6 of register pbdier to
disable the digital input to prevent leakage current.
This pin can be used as:
(1) Bit 7 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) PWM output of Timer3.
PB7 /
PWM2 /
TK4 /
IO
ST /
CMOS /
Analog
(3) Touch Key 4
CIN-
(4) Minus input source of comparator.
When this pin is configured as analog input, please use bit 7 of register pbdier to
disable the digital input to prevent leakage current.
This pin can be used as:
(1) Bit 7 of port A. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
IO
PA7 /
CS
ST /
CMOS /
Analog
(2) External Capacitor
When this pin is configured as CS, the input function of this pin is disabled to
prevent leakage current regardless of the setting of the bit 7 of register padier.
VDD: Digital positive power
AVDD: Analog positive power
VDD /
AVDD
VDD /
AVDD
VDD is the IC power supply while AVDD is the Analog positive power supply.
AVDD and VDD are double bonding internally and they have the same external
pin.
GND: Digital negative power
GND /
AGND
GND /
AGND
AGND: Analog negative power
GND is the IC ground pin while AGND is the Analog negative ground pin. AGND
and GND are double bonding internally and they have the same external pin.
Notes: IO: Input/Output; ST: Schmitt Trigger input; Analog: Analog input pin; CMOS: CMOS voltage level
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
4. Device Characteristics
4.1. DC/AC Characteristics
All data are acquired under the conditions of VDD=5.0V, fSYS =2MHz unless noted.
Symbol
Description
Operating Voltage
Min.
2.0*
-5
Typ
Max.
5.5
5
Unit
V
Conditions
VDD
* Subject to LVR tolerance
LVR% Low Voltage Reset Tolerance
System clock (CLK)* =
IHRC/2
%
0
0
0
8M
4M
2M
VDD ≧ 3.5V
VDD ≧ 2.5V
VDD ≧ 2.0V
VDD =3V
IHRC/4
IHRC/8
ILRC
fSYS
Hz
61K
0.5
50
mA fSYS=IHRC/16=1MIPS@5.0V
uA fSYS=ILRC=55KHz@5.0V
Operating Current
IOP
IPD
Power Down Current
(by stopsys command)
Power Save Current
(by stopexe command)
*Disable IHRC
1.4
1.0
VDD =5V
uA
VDD =3.3V
V
DD =3.3V
IPS
5
uA
VIL
VIH
Input low voltage for IO lines
0
0.1 VDD
VDD
V
V
0.8 VDD
0.7 VDD
PA5
Input high voltage for IO lines
VDD
Other IO
IO lines sink current (Normal)
PB4/PB5
42
26
19
14
PA7
PA5
Others
IOL
mA VDD=5.0V, VOL=0.5V
IO lines sink current (Low)
PB4/PB5
8
9
PA7
PA5
19
5
Others
IO lines drive current (Normal)
PB5
30
19
0
PA7
PA5
Others
10
IOH
mA VDD=5.0V, VOH=4.5V
IO lines drive current (Low)
PA7
5
0
3
PA5
Others
Input voltage
-0.3
VDD+0.3
V
VIN
1
VDD +0.3≧VIN≧ -0.3
VDD=5.0V
IINJ (PIN) Injected current on pin
uA
110
200
RPH Pull-high Resistance
KΩ
VDD=3.3V
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
Symbol
Description
Min.
Typ
Max.
Unit
Conditions
25oC, VDD =2.2V~5.5V
15.76*
16*
16.24*
V
DD =2.2V~5.5V,
Frequency of IHRC after
15.20*
13.60*
16*
16*
16.80*
18.40*
fIHRC
MHz -20oC <Ta<70oC*
calibration *
VDD =2.0V~5.5V,
-20oC <Ta<70oC
fILRC
tINT
Frequency of ILRC *
Interrupt pulse width
55
KHz
ns
30
VDD = 5.0V
8192
16384
65536
262144
misc[1:0]=00 (default)
misc[1:0]=01
ILRC
clock
tWDT
Watchdog timeout period
misc[1:0]=10
period
misc[1:0]=11
System boot-up period from
power-on
tSBP
tRST
50
ms
us
@ VDD =5V
@ VDD =5V
External reset pulse width
120
*These parameters are for design reference, not tested for every chip.
*The characteristic diagrams are the actual measured values. Considering the influence of production drift and other
factors, the data in the table are within the safety range of the actual measured values.
4.2. Absolute Maximum Ratings
Supply Voltage ............................................
2.0V ~ 5.5V (Maximum Rating: 5.5V)
*If VDD is over the maximum rating, it may lead to a permanent damage of IC.
Input Voltage …………………………………..
Operating Temperature ………………………
Storage Temperature …………………………
Junction Temperature ………………………..
-0.3V ~ VDD + 0.3V
-20°C ~ 70°C
-50°C ~ 125°C
150°C
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PMS164
12 Touch Keys OTP Controller
4.3. Typical IHRC Frequency vs. VDD (calibrated to 16MHz)
4.4. Typical ILRC Frequency vs. VDD
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12 Touch Keys OTP Controller
4.5. Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)
4.6. Typical ILRC Frequency vs. Temperature
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
4.7. Typical Operating Current vs. VDD and CLK=IHRC/n
Conditions:
tog pa0(1s), ON: Bandgap, LVR, IHRC
no t16m, no interrupt, no floating IO pins, disable ILRC, Touch: Disable
4.8. Typical Operating Current vs. VDD and CLK=ILRC/n
Conditions:
tog pa0(1s), ON: Bandgap, LVR, IHRC
no t16m, no interrupt, no floating IO pins, disable ILRC, Touch: Disable
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
4.9. Typical IO pull high resistance
4.10.Typical IO driving current (IOH) and sink current (IOL)
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
4.11.Typical IO input high/ low threshold voltage (VIH/ VIL)
4.12.Typical power down current (IPD) and power save current (IPS)
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
5. Functional Description
5.1. Program Memory – OTP
The OTP (One Time Programmable) program memory is used to store the program instructions to be
executed. The OTP program memory may contains the data, tables and interrupt entry. After reset, the initial
address for FPP0 is 0x000. The interrupt entry is 0x010 if used. The OTP program memory for PMS164 is a
1.75KW that is partitioned as Table 1. The OTP memory from address 0x700 to 0x7FF is for system using,
address space from 0x001 to 0x00F and from 0x011 to 0x6FF is user program space.
Address
0x000
0x001
•
Function
FPP0 reset – goto instruction
User program
•
•
•
0x00F
0x010
0x011
•
User program
Interrupt entry address
User program
•
0x6FF
0x700
•
User program
System Using
•
0x7FF
System Using
Table 1: Program Memory Organization
5.2. Boot Up
POR (Power-On-Reset) is used to reset PMS164 when power up. The boot up time is 3000 ILRC clock cycles.
Customer must ensure the stability of supply voltage after power up no matter which option is chosen, the
power up sequence is shown in the Fig. 2 and tSBP is the boot up time.
Please noted, during Power-On-Reset, the VDD must go higher than VPOR to boot-up the MCU.
Fig. 2: Power Up Sequence
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12 Touch Keys OTP Controller
5.3. Data Memory – SRAM
The access of data memory can be byte or bit operation. Besides data storage, the SRAM data memory is
also served as data pointer of indirect access method and the stack memory.
The stack memory is defined in the data memory. The stack pointer is defined in the stack pointer register; the
depth of stack memory of each processing unit is defined by the user. The arrangement of stack memory fully
flexible and can be dynamically adjusted by the user.
For indirect memory access mechanism, the data memory is used as the data pointer to address the data
byte. All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory
access. All the 128 bytes data memory of PMS164 can be accessed by indirect access mechanism.
5.4. Oscillator and clock
There are two oscillator circuits provided by PMS164: internal high RC oscillator (IHRC) and internal low RC
oscillator (ILRC), and these two oscillators are enabled or disabled by registers clkmd.4 and clkmd.2
independently. User can choose one of these two oscillators as system clock source and use clkmd register
to target the desired frequency as system clock to meet different application.
Oscillator Module
Enable/Disable
clkmd.4
IHRC
ILRC
clkmd.2
Table 2: Oscillator Module
5.4.1. Internal High RC oscillator and Internal Low RC oscillator
After boot-up, only the ILRC oscillators are enabled. The frequency of IHRC can be calibrated to eliminate
process variation by ihrcr register; normally it is calibrated to 16MHz. Please refer to the measurement chart
for IHRC frequency verse VDD and IHRC frequency verse temperature.
The frequency of ILRC will vary by process, supply voltage and temperature, please refer to DC
specification and do not use for accurate timing application.
5.4.2. IHRC calibration
The IHRC frequency may be different chip by chip due to manufacturing variation, PMS164 provide the
IHRC frequency calibration to eliminate this variation, and this function can be selected when compiling
user’s program and the command will be inserted into user’s program automatically. The calibration
command is shown as below:
.ADJUST_IC
SYSCLK=IHRC/(p1), IHRC=(p2)MHz, VDD=(p3)V
Where,
p1=2, 4, 8, 16, 32; In order to provide different system clock.
p2=14 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.
p3=2.3 ~ 5.5; In order to calibrate the chip under different supply voltage.
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12 Touch Keys OTP Controller
5.4.3. IHRC Frequency Calibration and System Clock
During compiling the user program, the options for IHRC calibration and system clock are shown as Table 3:
SYSCLK
○ Set IHRC / 2
○ Set IHRC / 4
○ Set IHRC / 8
○ Set IHRC / 16
○ Set IHRC / 32
○ Set ILRC
CLKMD
IHRCR
Description
= 34h (IHRC / 2)
= 14h (IHRC / 4)
= 3Ch (IHRC / 8)
= 1Ch (IHRC / 16)
= 7Ch (IHRC / 32)
= E4h (ILRC / 1)
No change
Calibrated
Calibrated
Calibrated
Calibrated
Calibrated
Calibrated
No Change
IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)
IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)
IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)
IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)
IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)
IHRC calibrated to 16MHz, CLK=ILRC
○ Disable
IHRC not calibrated, CLK not changed
Table 3: Options for IHRC Frequency Calibration
Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency
whenever stating the system. The program code for IHRC frequency calibration is executed only one time
that occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different
option for IHRC calibration is chosen, the system status is also different after boot. The following shows the
status of PMS164 for different option:
(1) .ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x34:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/2 = 8MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(2) .ADJUST_IC
SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V
After boot, CLKMD = 0x14:
IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled
System CLK = IHRC/4 = 4MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(3) .ADJUST_IC
SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V
After boot, CLKMD = 0x3C:
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/8 = 2MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(4) .ADJUST_IC
SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.3V
After boot, CLKMD = 0x1C:
IHRC frequency is calibrated to 16MHz@VDD=2.3V and IHRC module is enabled
System CLK = IHRC/16 = 1MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(5) .ADJUST_IC
SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V
After boot, CLKMD = 0x7C:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/32 = 500KHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
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12 Touch Keys OTP Controller
(6) .ADJUST_IC
SYSCLK=ILRC, IHRC=16MHz, VDD=5V
After boot, CLKMD = 0XE4:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled
System CLK = ILRC
Watchdog timer is disabled, ILRC is enabled, PA5 is input mode
(7) .ADJUST_IC
DISABLE
After boot, CLKMD is not changed (Do nothing):
IHRC is not calibrated and IHRC module is disabled
System CLK = ILRC
Watchdog timer is enabled, ILRC is enabled, PA5 is input mode
5.4.4. System Clock and LVR levels
The clock source of system clock comes from IHRC or ILRC, the hardware diagram of system clock in the
PMS164 is shown as Fig. 3.
Fig. 3: Options of System Clock
User can choose different operating system clock depends on its requirement; the selected operating
system clock should be combined with supply voltage and LVR level to make system stable. The LVR level
will be selected during compilation, and the lowest LVR levels can be chosen for different operating
frequencies. Please refer to Section 4.1.
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12 Touch Keys OTP Controller
5.4.5. System Clock Switching
After IHRC calibration, user may want to switch system clock to a new frequency or may switch system clock
at any time to optimize the system performance and power consumption. Basically, the system clock of
PMS164 can be switched among IHRC and ILRC by setting the clkmd register at any time; system clock will
be the new one after writing to clkmd register immediately. Please notice that the original clock module can
NOT be turned off at the same time as writing command to clkmd register. The examples are shown as below
and more information about clock switching, please refer to the “Help” -> “Application Note” -> “IC
Introduction” -> “Register Introduction” -> CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/2
…
//
//
//
system clock is ILRC
CLKMD
CLKMD.2
…
=
=
0x34;
0;
switch to IHRC/2,ILRC CAN NOT be disabled here
ILRC CAN be disabled at this time
Case 2: Switching system clock from IHRC/2 to ILRC
…
//
//
//
system clock is IHRC/2
CLKMD
CLKMD.4
…
=
=
0xF4;
0;
switch to ILRC, IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 3: Switching system clock from IHRC/2 to IHRC/4
…
//
//
system clock is IHRC/2, ILRC is enabled here
switch to IHRC/4
CLKMD
…
=
0X14;
Case 4: System may hang if it is to switch clock and turn off original oscillator at the same time
…
//
system clock is ILRC
CLKMD
=
0x30;
//
CAN NOT switch clock from ILRC to IHRC/2 and turn off
ILRC oscillator at the same time
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12 Touch Keys OTP Controller
5.5. Comparator
One hardware comparator is built inside the PMS164; Fig.4 shows its hardware diagram. It can compare
signals between two pins or with either internal reference voltage Vinternal R or internal bandgap reference
voltage. The two signals to be compared, one is the plus input and the other one is the minus input. For the
minus input of comparator can be PA3, PA4, Internal bandgap 1.20 volt, PB6, PB7 or Vinternal R selected by bit
[3:1] of gpcc register, and the plus input of comparator can be PA4 or Vinternal R selected by bit 0 of gpcc
register.
The comparator result can be selected through gpcs.7 to forcibly output to PB0 whatever input or output state.
It can be a direct output or sampled by Timer2 clock (TM2_CLK) which comes from Timer2 module. The
output polarity can be also inverted by setting gpcc.4 register. The comparator output can be used to request
interrupt service or read through gpcc.6.
16 stages
VDD
8R
8R
8R
gpcs.5=1
gpcs.5=0
gpcs.4=0
gpcs.4=1
R
R
R
R
gpcs[3:0]
MUX
Vinternal R
gpcc[3:1]
PA3
PA4
Bandgap
000
001 M
gpcc.4
To request interrupt
gpcc.6
010 U
011 X
100
X
O
R
-
PB6
PB7
M
U
X
101
+
D
F
F
To
PA0
0
Timer 2
clock
MUX
1
PA4/CIN+
gpcc.0
TM2_CLK
gpcc.5
gpcs.7
Fig.4: Hardware diagram of comparator
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12 Touch Keys OTP Controller
5.5.1. Internal reference voltage (Vinternal R
)
The internal reference voltage Vinternal R is built by series resistance to provide different level of reference
voltage, bit 4 and bit 5 of gpcs register are used to select the maximum and minimum values of Vinternal R
and bit [3:0] of gpcs register are used to select one of the voltage level which is deivided-by-16 from the
defined maximum level to minimum level. Fig.5 to Fig.8 shows four conditions to have different reference
voltage Vinternal R. By setting the gpcs register, the internal reference voltage Vinternal R can be ranged from
(1/32)*VDD to (3/4)*VDD.
Case 1 : gpcs.5=0 & gpcs.4=0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/4) VDD ~ (1/4) VDD + (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
4
(n+1)
32
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.5: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=0
Case 2 : gpcs.5=0 & gpcs.4= 1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (2/3) VDD ~ (1/24) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
24
Fig.6: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=1
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12 Touch Keys OTP Controller
Case 3 : gpcs.5=1 & gpcs.4= 0
16 stages
VDD
8R
8R
8R
gpcs.5=1
gpcs.4=0
gpcs.4=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/5) VDD ~ (1/5) VDD + (1/40) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
5
(n+1)
40
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.7: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=0
Case 4 : gpcs.5=1 & gpcs.4=1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (1/2) VDD ~ (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
32
Fig.8: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=1
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12 Touch Keys OTP Controller
5.5.2. Using the comparator
Case I:
Choosing PA3 as minus input and Vinternal R with (18/32)*VDD voltage level as plus input, Vinternal R is
configured as the above Figure “gpcs[5:4] = 2b’00” and gpcs [3:0] = 4b’1001 (n=9) to have Vinternal R
(1/4)*VDD + [(9+1)/32]*VDD = [(9+9)/32]*VDD = (18/32)*VDD.
=
gpcs = 0b1_0_00_1001;
gpcc = 0b1_0_0_0_000_0;
padier = 0bxxxx_0_xxx;
// Vinternal R = VDD*(18/32)
// enable comp, - input: PA3, + input: Vinternal R
// disable PA3 digital input to prevent leakage current
or
$ GPCS VDD*18/32;
$ GPCC Enable, N_PA3, P_R;
PADIER = 0bxxxx_0_xxx;
// - input: N_xx,+ input: P_R(Vinternal R)
Case 2:
Choosing Vinternal R as minus input with (22/40)*VDD voltage level and PA4 as plus input, the comparator
result will be inversed and then output to PA0. Vinternal R is configured as the above Figure “gpcs[5:4] =
2b’10” and gpcs [3:0] = 4b’1101 (n=13) to have Vinternal R = (1/5)*VDD + [(13+1)/40]*VDD = [(13+9)/40]*VDD
= (22/40)*VDD.
gpcs = 0b1_0_1_0_1101;
gpcc = 0b1_0_0_1_011_1;
padier = 0bxxx_0_xxxx;
// output to PA0,Vinternal R = VDD*(22/40)
// Inverse output, - input: Vinternal R, + input: PA4
// disable PA4 digital input to prevent leakage current
or
$ GPCS Output, VDD*22/40;
$ GPCC Enable, Inverse, N_R, P_PA4; // - input: N_R(Vinternal R),+ input: P_xx
PADIER = 0bxxx_0_xxxx;
Note: When selecting output to PA0 output, GPCS will affect the PA3 output function in ICE. Though the IC
is fine, be careful to avoid this error during emulation.
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12 Touch Keys OTP Controller
5.5.3. Using the comparator and Bandgap 1.20V
The internal bandgap module can provide 1.20 volt, it can measure the external supply voltage level. The
bandgap 1.20 volt is selected as minus input of comparator and Vinternal R is selected as plus input, the
supply voltage of Vinternal R is VDD, the VDD voltage level can be detected by adjusting the voltage level of
Vinternal R to compare with bandgap. If N (gpcs[3:0] in decimal) is the number to let Vinternal R closest to
bandgap 1.20 volt, the supply voltage VDD can be calculated by using the following equations:
For using Case 1: VDD = [ 32 / (N+9) ] * 1.20 volt ;
For using Case 2:
For using Case 3:
For using Case 4:
VDD = [ 24 / (N+1) ] * 1.20 volt ;
VDD = [ 40 / (N+9) ] * 1.20 volt ;
VDD = [ 32 / (N+1) ] * 1.20 volt ;
More information and sample code, please refer to IDE utility.
Case 1:
$ GPCS
VDD*12/40;
// 4.0V * 12/40 = 1.2V
$ GPCC Enable, BANDGAP, P_R; // - input: BANDGAP, + input: P_R(Vinternal R
)
….
if (GPC_Out)
// or GPCC.6
{
// when VDD﹥4V
}
else
{
}
// when VDD﹤4V
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12 Touch Keys OTP Controller
5.6. 16-bit Timer (Timer16)
PMS164 provide a 16-bit hardware timer (Timer16) and its clock source may come from system clock (CLK),
internal high RC oscillator (IHRC), internal low RC oscillator (ILRC), PA0 or PA4. Before sending clock to the
16-bit counter, a pre-scaling logic with divided-by-1, 4, 16 or 64 is selectable for wide range counting. The
16-bit counter performs up-counting operation only, the counter initial values can be stored from data memory
by issuing the stt16 instruction and the counting values can be loaded to data memory by issuing the ldt16
instruction. The interrupt request from Timer16 will be triggered by the selected bit which comes from bit[15:8]
of this 16-bit counter, rising edge or falling edge can be optional chosen by register integs.4. The hardware
diagram of Timer16 is shown as Fig. 9.
stt16 command
DATA Memory
t16m[7:5]
t16m[4:3]
ldt16 command
CLK
IHRC
ILRC
PA0
M
U
X
Pre-
scalar
÷
1, 4,
16, 64
16-bit
up
counter
Bit[15:0]
Data Bus
PA4
Bit[15:8]
M
U
X
To set
interrupt
request flag
or
t16m[2:0]
integs.4
Fig. 9: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three
parameters to define the Timer16 using; 1st parameter is used to define the clock source of Timer16, 2nd
parameter is used to define the pre-scalar and the 3rd one is to define the interrupt source.
T16M IO_RW
0x06
$ 7~5:
$ 4~3:
$ 2~0:
STOP, SYSCLK, X, PA4_F, IHRC, X, ILRC, PA0_F
/1, /4, /16, /64
BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
// 1st par.
// 2nd par.
// 3rd par.
User can choose the proper parameters of T16M to meet system requirement, examples as below:
$
T16M
SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if system clock SYSCLK = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 8 uS, about every 524 mS to generate INTRQ.2=1
$
$
T16M
PA0, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
T16M
STOP;
// stop Timer16 counting
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12 Touch Keys OTP Controller
5.7. Watchdog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC. There are four different timeout periods
of watchdog timer can be chosen by setting the misc register, it is:
8k ILRC clocks period if register misc[1:0]=00 (default)
16k ILRC clocks period if register misc[1:0]=01
64k ILRC clocks period if register misc[1:0]=10
256k ILRC clocks period if register misc[1:0]=11
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature;
user should reserve guard band for safe operation. Besides, the watchdog period will also be shorter than
expected after Reset or Wakeup events. It is suggested to clear WDT by wdreset command after these
events to ensure enough clock periods before WDT timeout.
When WDT is timeout, PMS164 will be reset to restart the program execution. The relative timing diagram of
watchdog timer is shown as Fig.10.
VDD
t
SBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig. 10: Sequence of Watch Dog Time Out
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12 Touch Keys OTP Controller
5.8. Interrupt
There are eight interrupt lines for PMS164:
External interrupt PA0 / PA5
External interrupt PB0
Timer16 interrupt
Timer2 interrupt
Timer3 interrupt
GPC interrupt
Two touch key interrupts (TK_OV and TK_END)
Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the
hardware diagram of interrupt function is shown as Fig. 11. All the interrupt request flags are set by hardware
and cleared by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both,
depending on the setting of register integs. All the interrupt request lines are also controlled by engint
instruction (enable global interrupt) to enable interrupt operation and disgint instruction (disable global
interrupt) to disable it. The stack memory for interrupt is shared with data memory and its address is specified
by stack register sp. Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0.
Moreover, user can use pushaf / popaf instructions to store or restore the values of ACC and flag register to
/ from stack memory.
Since the stack memory is shared with data memory, user should manipulate the memory using carefully. By
adjusting the memory location of stack point, the depth of stack pointer could be fully specified by user to
achieve maximum flexibility of system.
Inten.7
Timer3
Detect
Intrq.7
output
event
Inten.6
Timer2
Intrq.6
Detect
event
output
Interrupt
to FPP0
Inten.5
Intrq.5
GPC output
Detect
event
Inten.4
Intrq.4
engint / disgint
TK_OV
TK_END
T16 output
Detect
rising
edge
Note: “engint” and
“disgint” are instructions
Inten.3
Intrq.3
OR
Detect
rising
edge
Inten.2
Intrq.2
Detect
rising
edge
Inten.1
Intrq.1
PB0
Detect
both
edge
Inten.0
Intrq.0
PA0/PA5
Detect
both
edge
Fig. 11: Hardware diagram of Interrupt controller
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12 Touch Keys OTP Controller
Once the interrupt occurs, its operation will be:
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x010.
During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four
bytes for two levels interrupt. For interrupt operation, the following sample program shows how to handle the
interrupt, noticing that it needs four bytes stack memory to handle one level interrupt and pushaf.
void
{
FPPA0
(void)
...
$
INTEN PA0;
// INTEN =1; interrupt request when PA0 level changed
// clear INTRQ
INTRQ
ENGINT
...
=
0;
// global interrupt enable
DISGINT
...
// global interrupt disable
}
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12 Touch Keys OTP Controller
void Interrupt (void)
// interrupt service routine
{
PUSHAF
// store ALU and FLAG register
// If INTEN.PA0 will be opened and closed dynamically,
// user can judge whether INTEN.PA0 =1 or not.
// Example: If (INTEN.PA0 && INTRQ.PA0) {…}
// If INTEN.PA0 is always enable,
// user can omit the INTEN.PA0 judgement to speed up interrupt service routine.
If (INTRQ.PA0)
{
// Here for PA0 interrupt service routine
INTRQ.PA0 = 0;
...
// Delete corresponding bit (take PA0 for example)
}
...
// X : INTRQ = 0;
// It is not recommended to use INTRQ = 0 to clear all at the end of
the
// interrupt service routine.
// It may accidentally clear out the interrupts that have just occurred
// and are not yet processed.
POPAF
// restore ALU and FLAG register
}
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12 Touch Keys OTP Controller
5.9. Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-Save mode (“stopexe”) is the
state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used
to save power deeply. Therefore, Power-Save mode is used in the system which needs low operating power
with wake-up occasionally and Power-Down mode is used in the system which needs power down deeply
with seldom wake-up. Table 4 shows the differences in oscillator modules between Power-Save mode
(“stopexe”) and Power-Down mode (“stopsys”).
Differences in oscillator modules between STOPSYS and STOPEXE
IHRC
Stop
ILRC
Stop
STOPSYS
STOPEXE
No Change
No Change
Table 4: Differences in oscillator modules between STOPSYS and STOPEXE
5.9.1. Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all the
oscillator modules be active. For CPU, it stops executing; however, for Timer16, counter keep counting if its
clock source is not the system clock. The wake-up sources for “stopexe” can be IO-toggle or Timer16
counts to set values when the clock source of Timer16 is IHRC or ILRC modules, or wake-up by comparator
when setting GPCC.7=1 and GPCS.6=1 to enable the comparator wake-up function at the same time.
Wake-up from input pins can be considered as a continuation of normal execution, the detail information for
Power-Save mode shows below:
IHRC oscillator modules: No change, keep active if it was enabled
ILRC oscillator modules: must remain enabled, need to start with ILRC when be wakening up
System clock: Disable, therefore, CPU stops execution
OTP memory is turned off
Timer counter: Stop counting if system clock is selected by clock source or the corresponding oscillator
module is disabled; otherwise, it keeps counting. (The Timer contains TM16, TM2, TM3)
Wake-up sources:
a. IO toggle wake-up: IO toggling in digital input mode (PxC bit is 1 and PxDIER bit is 1).
b. Timer wake-up: If the clock source of Timer is not the SYSCLK, the system will be awakened when
the Timer counter reaches the set value.
c. Comparator wake-up: It need setting GPCC.7=1 and GPCS.6=1 to enable the comparator wake-up
function at the same time.
The watchdog timer must be disabled before issuing the “stopexe” command, the example is shown as
below:
CLKMD.En_WatchDog
stopexe;
….
Wdreset;
=
=
0;
1;
// disable watchdog timer
// power saving
CLKMD.En_WatchDog
// enable watchdog timer
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12 Touch Keys OTP Controller
Another example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M IHRC, /1, BIT8
…
// Timer16 setting
WORD
STT16
count
count;
=
0;
stopexe;
…
The initial counting value of Timer16 is zero and the system will be waken up after the Timer16 counts 256
IHRC clocks.
5.9.2. Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using
the “stopsys” instruction, this chip will be put on Power-Down mode directly. It is recommend to set
GPCC.7=0 to disable the comparator before the command “stopsys”.The following shows the internal status
of PMS164 in detail when “stopsys” command is issued:
All the oscillator modules are turned off
OTP memory is turned off
The contents of SRAM and registers remain unchanged
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1)
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CMKMD
CLKMD.4 =
=
0xF4;
0;
//
//
Change clock from IHRC to ILRC, disable watchdog timer
disable IHRC
…
while (1)
{
STOPSYS;
if (…) break;
//
//
//
enter power-down
if wakeup happen and check OK, then return to high speed,
else stay in power-down mode again.
}
CLKMD
=
0x34;
//
Change clock from ILRC to IHRC/2
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12 Touch Keys OTP Controller
5.9.3. Wake-up
After entering the Power-Down or Power-Save modes, the PMS164 can be resumed to normal operation by
toggling IO pins, Timer wake-up is available for Power-Save mode ONLY. Table 5 shows the differences in
wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
Yes
Timer wake-up
STOPSYS
STOPEXE
No
Yes
Yes
Table 5: Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the PMS164, registers padier and pbdier should be properly set to
enable the wake-up function for every corresponding pin. The time for normal wake-up is about 2048 ILRC
clocks counting from wake-up event.
Suspend mode
Wake-up mode
Wake-up time (tWUP) from IO toggle
2048 * TILRC
,
STOPEXE suspend
normal wake-up
Where TILRC is the clock period of ILRC
2048 * TILRC
,
STOPSYS suspend
normal wake-up
Where TILRC is the clock period of ILRC
Table 6: Suspend mode / Wake-up mode / Wake-up time from IO toggle
5.10.IO Pins
All the IO pins have the same structure except PA5 which has ONLY an open-drain output (without Q1 in
Fig12) but its pull high is still functional by setting paph.5. When PMS164 is put in power-down or power-save
mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins needed to
wake-up system must be set to input mode and set the corresponding bits of registers padier to high. The
same reason, padier.0 should be set to high when PA0 is used as external interrupt pin.
All these pins have Schmitt-trigger input buffer and output driver with CMOS level. When it is set to output low,
the pull-up resistor is turned off automatically. If user wants to read the pin state, please notice that it should
be set to input mode before reading the data port; if user reads the data port when it is set to output mode, the
reading data comes from data register, NOT from IO pad. As an example, Table 7 shows the configuration
table of bit 0 of port A. The hardware diagram of IO buffer is also shown as Fig. 12.
pa.0 pac.0 paph.0
Description
X
X
0
1
1
0
0
1
1
1
0
1
X
0
1
Input without pull-up resistor
Input with pull-up resistor
Output low without pull-up resistor
Output high without pull-up resistor
Output high with pull-up resistor
Table 7: PA0 Configuration Table
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12 Touch Keys OTP Controller
Fig. 12: Hardware diagram of IO buffer
Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output
mode (without Q1). When PMS164 is put in power-down or power-save mode, every pin can be used to
wake-up system by toggling its state. Therefore, those pins needed to wake-up system must be set to input
mode and set the corresponding bits of registers padier to high. The same reason, padier.0 should be set to
high when PA0 is used as external interrupt pin.
5.11. Reset
There are many causes to reset the PMS164, once reset is asserted, all the registers in PMS164 will be set
to default values, system should be restarted once abnormal cases happen, or by jumping program counter
to address ’h0. The data memory is in uncertain state when reset comes from power-up and LVR; however,
the content will be kept when reset comes from PRSTB pin or WDT timeout.
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12 Touch Keys OTP Controller
5.12. 8-bit Timer (Timer2/Timer3) with PWM generation
Two 8-bit hardware timers (Timer2 and Timer3) with PWM generation is implemented in the PMS164, The
following descriptions thereinafter are for Timer2 only. It is because Timer3 have same structure with Timer2.
Please refer to Fig. 13 shown its hardware diagram, the clock sources of Timer2 may come from system
clock, internal high RC oscillator (IHRC), internal low RC oscillator (ILRC), comparator, PB0, PA0 and PA4,
bit [7:4] of register tm2c are used to select the clock of Timer2. Please notice that if IHRC is selected for
Timer2 clock source, the clock sent to Timer2 will keep running when using ICE in halt state. According to
the setting of register tm2c[3:2], Timer2 output can be selectively output to PA1 or PA2 or PA3. At this point,
regardless of whether PX.x is the input or output state, Timer2 signal will be forced to output. A clock
pre-scaling module is provided with divided-by-1, 4, 16, and 64 options, controlled by bit [6:5] of tm2s
register; one scaling module with divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s register.
In conjunction of pre-scaling function and scaling function, the frequency of Timer2 clock (TM2_CLK) can be
wide range and flexible.
The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back
by tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound
register, the upper bound register is used to define the period of timer or duty of PWM. There are two
operating modes for Timer2: period mode and PWM mode; period mode is used to generate periodical
output waveform or interrupt event; PWM mode is used to generate PWM output waveform with optional
6-bit to 8-bit PWM resolution, Fig. 14 shows the timing diagram of Timer2 for both period mode and PWM
mode.
TM2_CLK
tm2s.7
tm2c.1
tm2c[7:4]
tm2s[6:5] tm2s[4:0]
edge to
interrupt
M
U
X
Pre-
scalar
÷
1, 4,
16, 64
Scalar
8-bit
up
counter
CLK,
IHRC,
ILRC,
tm2ct[7:0]
÷
1 ~ 31
Comparator
PA0,
X
O
R
D
E
M
U
X
PB2
PA3
PB4
~PA0,
PA4,
~PA4
PB0
upper
bound
register
~PB0
tm2c.0
tm2b[7:0]
tm2c[3:2]
Fig. 13: Timer2 hardware diagram
The output of Timer3 can be sent to pin PB5, PB6 or PB7.
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PMS164
12 Touch Keys OTP Controller
Time out and
Time out and
Time out and
Interrupt request
Interrupt request
Interrupt request
Counter
0xFF
bound
Counter
0xFF
Counter
0x3F
bound
bound
Time
Time
Time
Time
Time
Event Trigger
Event Trigger
Event Trigger
Output-pin
Output-pin
Output-pin
Time
Mode 0 – Period Mode
Mode 1 – 8-bit PWM Mode
Mode 1 – 6-bit PWM Mode
Fig. 14: Timing diagram of Timer2 in period mode and PWM mode (tm2c.1=1)
A Code Option GPC_PWM is for the applications which need the generated PWM waveform to be controlled
by the comparator result. If the Code Option GPC_PWM is selected, the PWM output stops while the
comparator output is 1 and then the PWM output turns on while the comparator output goes back to 0, as
shown in Fig. 15.
PWM Output
Comparator
Output
Fig. 15: Comparator controls the output of PWM waveform
5.12.1. Using the Timer2 to generate periodical waveform
If periodical mode is selected, the duty cycle of output is always 50%; its frequency can be summarized as
below:
Frequency of Output = Y ÷ [2 × (K+1) × S1 × (S2+1) ]
Where, Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (S1= 1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2= 0 ~ 31)
Example 1:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ [ 2 × (127+1) × 1 × (0+1) ] = 31.25kHz
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12 Touch Keys OTP Controller
Example 2:
Example 3:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s[7:0] = 0b0_11_11111, S1=64 , S2 = 31
frequency = 8MHz ÷ ( 2 × (127+1) × 64 × (31+1) ) =15.25Hz
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_1111, K=15
tm2s = 0b0_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (15+1) × 1 × (0+1) ) = 250kHz
Example 4:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_0001, K=1
tm2s = 0b0_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (1+1) × 1 × (0+1) ) =2MHz
The sample program for using the Timer2 to generate periodical waveform to PA3 is shown as below:
void FPPA0 (void)
{
. ADJUST_IC
…
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
tm2c = 0b0001_10_0_0;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, period mode
while(1)
{
nop;
}
}
5.12.2. Using the Timer2 to generate 8-bit PWM waveform
If 8-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=0, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [256 × S1 × (S2+1) ]
Duty of Output = ( K+1 ) ÷ 256 × 100%
Where, Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1= tm2s[6:5] : pre-scalar (S1= 1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2= 0 ~ 31)
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12 Touch Keys OTP Controller
Example 1:
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25kHz
duty of output = [(127+1) ÷ 256] × 100% = 50%
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_11_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 256 × 64 × (31+1) ) = 15.25Hz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b1111_1111, K=255
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25kHz
duty of output = [(255+1) ÷ 256] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_1001, K = 9
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25kHz
duty of output = [(9+1) ÷ 256] × 100% = 3.9%
The sample program for using the Timer2 to generate PWM waveform from PA3 is shown as below:
void
{
FPPA0 (void)
.ADJUST_IC SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
wdreset;
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, PWM mode
tm2c = 0b0001_10_1_0;
while(1)
{
nop;
}
}
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12 Touch Keys OTP Controller
5.12.3. Using the Timer2 to generate 6-bit PWM waveform
If 6-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=1, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [64 × S1 × (S2+1) ]
Duty of Output = [( K+1 ) ÷ 64] × 100%
Where, tm2c[7:4] = Y : frequency of selected clock source
tm2b[7:0] = K : bound register in decimal
tm2s[6:5] = S1 : pre-scalar (S1= 1, 4, 16, 64)
tm2s[4:0] = S2 : scalar register in decimal (S2= 0 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125kHz
duty = [(31+1) ÷ 64] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1_11_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 64 × 64 × (31+1) ) = 61.03 Hz
duty of output = [(31+1) ÷ 64] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0011_1111, K=63
tm2s = 0b1_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125kHz
duty of output = [(63+1) ÷ 64] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_0000, K=0
tm2s = 0b1_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125kHz
duty = [(0+1) ÷ 64] × 100% =1.5%
©Copyright 2020, PADAUK Technology Co. Ltd
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12 Touch Keys OTP Controller
5.13.Touch Function
A touch detecting circuit is included in PMS164. Its functional block diagram is shown as Fig.16.
Fig. 16: Functional block diagram of the touch detecting circuit
The Touch detecting circuit in PMS164 applies the method of capacitive sensing, detecting the
capacitive virtual ground effect of a finger, or the capacitance between sensors.
An accurate, low-leakage external capacitor CS is required to be connect between PA7/CS pin and GND. In
the mean time, user should set the code option PA7_Sel to be “As CS” to configure it as CS pin, instead of
PA7.
For starting touch detecting process, user should follow the procedures below:
1. Selecting the touch pad to be measure by setting TKE1 & TKE2 registers. Only one pad should be
selected a time.
2. Issuing a Touch START command by writing “0x10” into TCC register. The capacitor CS will be
automatically discharged to VSS firstly. The discharging time is selectable from 32, 64 and 128 Touch
clocks by TS[1:0].
3. The larger the CS capacitance value, the longer the discharge time is needed to fully discharge the
capacitor to VSS. However, in some cases, 128 Touch clocks may still be not long enough to fully
discharge the CS capacitor. At this time, user should do it manually by writing “0x30” into TCC register
instead of “0x10”. After a certain discharge time decided by the user, user can issue a Touch START
(0x10) command to continue this touch conversion progress. Or user can also abort the conversion
progress by writing “0x00” into TCC register.
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12 Touch Keys OTP Controller
4. After discharging, the CS will be charged toward VCC per Touch clock (TK_CLK). The charging speed
is determined by the capacitance value of the selected Touch pad.
5. The charging progress will be stopped automatically when its voltage reaches the internal generated
threshold voltage (VREF). The program determines whether the charging process is stopped by
reading TCC[6:4] or INTRQ[3].
The VREF voltage is selectable from 0.2*VCC, 0.3*VCC, 0.4*VCC and 0.5*VCC by TS[3:2].
6. By reading the Touch Counter value from TKCH & TKCL registers, user can monitor the capacitance
value change of the Touch pad. The value reads from Touch Counter is related to the ratio of CS and
CP, while CP represents the total capacitance that is the combination of PCB, wire and touch pad
whose capacitance can be varied by human finger’s touch. Once the CP value is altered, the periods
required to charge the CS to VREF shorten. By counting the discrepancy of clock periods, the circuitry
can decide if the touch pad is enabled.
Fig. 17: Timing diagram of Touch converting progress
Note: When the VREF voltage is first set or the reference voltage option is switched midway, please discard
the first TKCH and TKCL data read after that.
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12 Touch Keys OTP Controller
6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit
7 - 4
3
Reset R/W
Description
Reserved. These four bits are “1” when read.
-
-
-
R/W OV (Overflow). This bit is set whenever the sign operation is overflow.
AC (Auxiliary Carry). There are two conditions to set this bit, the first one is carry out of low
R/W nibble in addition operation, and the other one is borrow from the high nibble into low nibble
in subtraction operation.
2
-
C (Carry). There are two conditions to set this bit, the first one is carry out in addition
R/W operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
1
0
-
-
Z (Zero). This bit will be set when the result of arithmetic or logic operation is zero;
R/W
Otherwise, it is cleared.
6.2. Stack Pointer Register (sp), IO address = 0x02
Bit
Reset R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer. Please notice that bit 0 should be kept 0 due to program counter is 16 bits.
7 - 0
-
R/W
6.3. Clock Mode Register (clkmd), IO address = 0x03
Bit
Reset R/W
Description
System clock selection:
Type 0, clkmd[3]=0
Type 1, clkmd[3]=1
000: IHRC/16
000: IHRC/4
001: IHRC/2
01x: reserved
100: reserved
101: reserved
001: IHRC/8
010: ILRC/16 (ICE doesn’t support)
011: IHRC/32
7 - 5
111 R/W
100: IHRC/64
110: ILRC/4
110: ILRC/64 (ICE doesn’t support)
1x1: reserved.
111: ILRC (default)
4
3
0
0
R/W IHRC oscillator Enable. 0 / 1: disable / enable
Clock Type Select. This bit is used to select the clock type in bit [7:5].
0 / 1: Type 0 / Type 1
R/W
R/W
ILRC Enable. 0 / 1: disable / enable
2
1
If ILRC is disabled, watchdog timer is also disabled.
1
0
1
0
R/W Watch Dog Enable. 0 / 1: disable / enable
R/W Pin PA5/PRST# function. 0 / 1: PA5 / PRSTB
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12 Touch Keys OTP Controller
6.4. Interrupt Enable Register (inten), IO address = 0x04
Bit
7
Reset R/W
Description
0
0
0
0
0
0
0
0
R/W Enable interrupt from Timer3. 0 / 1: disable / enable
R/W Enable interrupt from Timer2. 0 / 1: disable / enable
R/W Enable interrupt from comparator. 0 / 1: disable / enable
R/W Enable interrupt from Touch Key TK_OV. 0 / 1: disable / enable
R/W Enable interrupt from Touch Key TK_END. 0 / 1: disable / enable
R/W Enable interrupt from Timer16 overflow. 0 / 1: disable / enable
R/W Enable interrupt from PB0. 0 / 1: disable / enable
6
5
4
3
2
1
0
R/W Enable interrupt from PA0 / PA5. 0 / 1: disable / enable
6.5. Interrupt Request Register (intrq), IO address = 0x05
Bit
Reset R/W
Description
Interrupt Request from Timer3, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
7
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt Request from Timer2, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
6
5
4
3
2
1
0
Interrupt Request from comparator, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from Touch Key TK_OV, this bit is set by hardware and cleared by
software. 0 / 1: No request / Request
Interrupt Request from Touch Key TK_END, this bit is set by hardware and cleared by
software. 0 / 1: No request / Request
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PB0, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PA0 / PA5, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
©Copyright 2020, PADAUK Technology Co. Ltd
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12 Touch Keys OTP Controller
6.6. Timer 16 mode Register (t16m), IO address = 0x06
Bit
Reset R/W
Description
Timer Clock source selection
000: Timer 16 is disabled
001: CLK (system clock)
010: reserved
7 - 5
000 R/W 011: PA4 falling edge (from external pin)
100: IHRC
101: reserved
110: ILRC
111: PA0 falling edge (from external pin)
Internal clock divider.
00: ÷1
4 - 3
00
R/W 01: ÷4
10: ÷16
11: ÷64
Interrupt source selection. Interrupt event happens when selected bit is changed.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2 : bit 10 of Timer16
2 - 0
000 R/W 3 : bit 11 of Timer16
4 : bit 12 of Timer16
5 : bit 13 of Timer16
6 : bit 14 of Timer16
7 : bit 15 of Timer16
6.7. MISC Register (misc), IO address = 0x08
Bit
Reset R/W
Description
7 - 3
-
-
Reserved
Disable LVR function.
0 / 1 : Enable / Disable
Watchdog time out period
00: 8K ILRC clock period
2
0
WO
1 - 0
00
WO 01: 16K ILRC clock period
10: 64K ILRC clock period
11: 256K ILRC clock period
6.8. External Oscillator setting Register (eoscr, write only), IO address = 0x0a
Bit
7 - 1
0
Reset R/W
Description
-
-
Reserved. Please keep 0.
0
WO Power-down the Bandgap and LVR hardware modules. 0 / 1: normal / power-down.
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12 Touch Keys OTP Controller
6.9. Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset R/W
Description
7 - 5
-
-
Reserved. Please keep 0.
Timer16 edge selection.
4
0
WO 0 : rising edge to trigger interrupt
1 : falling edge to trigger interrupt
PB0 edge selection.
00 : both rising edge and falling edge to trigger interrupt
WO 01 : rising edge to trigger interrupt
10 : falling edge to trigger interrupt
11 : reserved.
3 - 2
00
00
PA0 / PA5 edge selection.
00 : both rising edge and falling edge to trigger interrupt
WO 01 : rising edge to trigger interrupt
10 : falling edge to trigger interrupt
11 : reserved.
1 - 0
6.10.Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset R/W
Description
Enable PA7~PA6 digital input and wake up event. 1 / 0 : enable / disable
These bits can be set to low to disable wake up from PA7~PA6 toggling.
Enable PA5 digital input, wake up event and interrupt request. 1 / 0 : enable / disable
7 - 6
11
1
WO
5
WO This bit can be set to low to disable wake up from PA5 toggling and interrupt request from
this pin.
Enable PA4~PA3 digital input and wake up event. 1 / 0 : enable / disable
4 - 3
2 - 1
11
-
WO
These bits can be set to low to disable wake up from PA4~PA3 toggling.
-
Reserved.
Enable PA0 digital input, wake up event and interrupt request. 1 / 0 : enable / disable
0
1
WO This bit can be set to low to disable wake up from PA0 toggling and interrupt request from
this pin.
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PMS164
12 Touch Keys OTP Controller
6.11.Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset
R/W
Description
Enable PB7 ~ PB1 digital input and wake-up event. 1 / 0 : enable / disable.
These bit can be set to low to disable wake-up from PB7 ~ PB1 toggling.
Enable PB0 digital input, wake-up event and interrupt request. 1 / 0 : enable / disable.
7 - 1
WO
0xFF
0
WO This bit can be set to low to disable wake up from PB0 toggling and interrupt request from
this pin.
6.12.Port A Data Registers (pa), IO address = 0x10
Bit
Reset R/W
Description
7 - 0 8’h00 R/W Data registers for Port A.
6.13.Port A Control Registers (pac), IO address = 0x11
Bit
Reset R/W
Description
Port A control registers. This register is used to define input mode or output mode for each
corresponding pin of port A. 0 / 1: input / output.
7 - 0 8’h00 R/W
6.14.Port A Pull-High Registers (paph), IO address = 0x12
Bit
Reset R/W
Description
Port A pull-high registers. This register is used to enable the internal pull-high device on
each corresponding pin of port A. 0 / 1 : disable / enable
7 - 0 8’h00 R/W
6.15.Port B Data Registers (pb), IO address = 0x14
Bit
Reset R/W
Description
7 - 0 0’h00 R/W Data registers for Port B.
6.16.Port B Control Registers (pbc), IO address = 0x15
Bit
Reset R/W
Description
Port B control registers. This register is used to define input mode or output mode for each
corresponding pin of port B. 0 / 1: input / output
7 - 0 0’h00 R/W
6.17.Port B Pull-High Registers (pbph), IO address = 0x16
Bit
Reset R/W
Description
Port B pull-high registers. This register is used to enable the internal pull-high device on
each corresponding pin of port B. 0 / 1 : disable / enable
7 - 0 8’h00 R/W
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12 Touch Keys OTP Controller
6.18.Comparator Control Register (gpcc), IO address = 0x18
Bit
Reset
R/W
Description
Enable comparator. 0 / 1 : disable / enable
When this bit is set to enable, please also set the corresponding analog input pins to be
digital disable to prevent IO leakage.
Comparator result of comparator.
0: plus input < minus input
7
0
R/W
6
5
4
-
RO
R/W
R/W
1: plus input > minus input
Select whether the comparator result output will be sampled by TM2_CLK?
0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
0: polarity is NOT inversed.
0
0
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PA3
001 : PA4
010 : Internal 1.20 volt bandgap reference voltage
011 : Vinternal R
3 - 1
000
R/W
R/W
100 : PB6 (not for EV5)
101 : PB7 (not for EV5)
11X: reserved
Selection the plus input (+) of comparator.
0 : Vinternal R
0
0
1 : PA4
6.19. Comparator Selection Register (gpcs), IO address = 0x19
Bit
Reset
R/W
Description
Comparator output enable (to PA0).
0 / 1 : disable / enable
7
0
WO
Wakeup by comparator output enable.
0 / 1 : disable / enable
6
0
WO
5
4
0
0
WO Selection of high range of comparator.
WO Selection of low range of comparator.
Selection the voltage level of comparator.
0000 (lowest) ~ 1111 (highest)
3 - 0
0000
WO
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
6.20.Reset Status Register (rstst), IO address = 0x1b
Reset
Bit
7
R/W
R/W
Description
(POR only)
The reset flag for the Watch-Dog time-out. This bit is 1 when Watch-Dog reset occurs.
Write 0 to clear this flag or POR clear.
The reset flag for the invalid code. This bit is 1 when invalid code reset occurs.
Write 0 to clear this flag or POR clear.
0
0
6
R/W
Reserved. Please keep 0.
5
4
0
-
-
-
Reserved. Please keep 1.
The reset flag for the external reset pin (PA5). This bit is 1 when PA5 reset occurs.
Write 0 to clear this flag.
3
-
R/W
VDD below 4V flag. This bit is 1 when the VDD voltage is lower than 4V.
Write 0 to clear this flag.
Please note that this bit will be 1 automatically when VDD is powered slowly. If necessary,
it is recommended to clear this flag during the program initialization.
VDD below 3V flag. This bit is 1 when the VDD voltage is lower than 3V.
Write 0 to clear this flag.
Please note that this bit will be 1 automatically when VDD is powered slowly. If necessary,
it is recommended to clear this flag during the program initialization.
VDD below 2V flag. This bit is 1 when the VDD voltage is lower than 2V.
Write 0 to clear this flag.
Please note that this bit will be 1 automatically when VDD is powered slowly. If necessary,
it is recommended to clear this flag during the program initialization.
2
-
R/W
1
0
-
-
R/W
R/W
6.21.Timer2 Control Register (tm2c), IO address = 0x1c
Bit
Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : system clock
0010 : internal high RC oscillator (IHRC)
0011 : reserved
0100 : ILRC
0101 : comparator output
011x : reserved
7 - 4
0000
R/W
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does
NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
01 : PB2
3 - 2
00
R/W
10 : PA3
11 : PB4
Timer2 mode selection.
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer2 output.
0 / 1: disable / enable
1
0
0
0
R/W
R/W
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
6.22.Timer2 Counter Register (tm2ct), IO address = 0x1d
Bit
Reset R/W
RO Bit [7:0] of Timer2 counter register.
Description
7 - 0 0’h00
Note: Timer2 is designed for PWM mode and Period mode, so do not read tm2ct register.
6.23.Timer2 Scalar Register (tm2s), IO address = 0x17
Bit
Reset R/W
Description
PWM resolution selection.
WO 0 : 8-bit
7
0
1 : 6-bit or 7-bit (by code option TMx_bit)
Timer2 clock pre-scalar.
00 : ÷ 1
6 - 5
00
WO 01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4 - 0 00000 WO Timer2 clock scalar.
6.24.Timer2 Bound Register (tm2b), IO address = 0x09
Bit
Reset R/W
Description
7 - 0 0’h00 WO Timer2 bound register.
6.25.Timer3 Control Register (tm3c), IO address = 0x32
Bit Reset
R/W
Description
Timer3 clock selection.
0000 : disable
0001 : system clock
0010 : internal high RC oscillator (IHRC)
0011 : reserved
0100 : ILRC
0101 : comparator output
011x : reserved
1000 : PA0 (rising edge)
7 - 4
0000 R/W
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer3 clock, the clock sent to Timer3 does
NOT be stopped, Timer3 will keep counting when ICE is in halt state.
Timer3 output selection.
00 : disable
3 - 2
00
R/W 01 : PB5
10 : PB6
11 : PB7
Timer3 mode selection.
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer3 output.
0 / 1: disable / enable
1
0
0
0
R/W
R/W
©Copyright 2020, PADAUK Technology Co. Ltd
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12 Touch Keys OTP Controller
6.26.Timer3 Counter Register (tm3ct), IO address = 0x33
Bit
Reset R/W
Description
7 - 0 0’h00 R/W Bit [7:0] of Timer3 counter register.
6.27.Timer3 Scalar Register (tm3s), IO address = 0x34
Bit
Reset R/W
Description
PWM resolution selection.
WO 0 : 8-bit
7
0
1 : 6-bit or 7-bit (by code option TMx_bit)
Timer3 clock pre-scalar.
00 : ÷ 1
6 - 5
00
WO 01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4 - 0 00000 WO Timer3 clock scalar.
6.28.Timer3 Bound Register (tm3b), IO address = 0x35
Bit
Reset R/W
Description
7 - 0 0’h00 WO Timer3 bound register.
6.29.Touch Selection Register (ts), IO address = 0x20
Bit
Reset R/W
Description
Touch clock selection (TK_CLK)
0010: IHRC/4
0011: IHRC/8
0100: IHRC/16
0101: IHRC/32
0110: IHRC/64
0111: IHRC/128
1000: ILRC
7 - 4
-
R/W
Others: reserved
Touch VREF selection
00: 0.5 * VCC
01: 0.4 * VCC
3 - 2
00
R/W
R/W
10: 0.3 * VCC
11: 0.2 * VCC
Select the discharge time before starting the touch function (TK_DISCHG)
00: reserved
01: 32 * CLK
10: 64 * CLK
11: 128 * CLK
1 - 0
-
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS164
12 Touch Keys OTP Controller
6.30.Touch Charge Control Register (tcc), IO address = 0x21
Bit
7
Reset R/W
Description
-
-
-
-
R/W
-
Reserved
Touch control and status
Data
Command (W)
TK_STOP
Status (R)
Ready / End
Running
000
(Touch module power down)
TK_RUN
6 - 4
001
011
Discharge
Discharging
Reserved
(Discharge CS capacitor)
Reserved
Others
3 - 0
reserved
6.31.Touch Key Enable 2 Register (tke2), IO address = 0x22
Bit
7 - 5
4
Reset R/W
Description
-
-
Reserved
0
0
0
0
0
R/W Enable PB1/TK12. 0/1: disable/enable
R/W Enable PB0/TK11. 0/1: disable/enable
R/W Enable PB3/TK10. 0/1: disable/enable
R/W Enable PB2/TK9. 0/1: disable/enable
R/W Enable PA6/TK8. 0/1: disable/enable
3
2
1
0
6.32.Touch Key Enable 1 Register (tke1), IO address = 0x24
Bit
7
Reset R/W
Description
0
0
0
0
0
0
0
-
R/W Enable PA0/TK7. 0/1: disable/enable
6
R/W Enable PA4/TK6. 0/1: disable/enable
R/W Enable PA3/TK5. 0/1: disable/enable
R/W Enable PB7/TK4. 0/1: disable/enable
R/W Enable PB6/TK3. 0/1: disable/enable
R/W Enable PB5/TK2. 0/1: disable/enable
R/W Enable PB4/TK1. 0/1: disable/enable
5
4
3
2
1
0
-
reserved
6.33.Touch Key Charge Counter High Register (tkch), IO address = 0x2B
Bit
Reset R/W
Description
7 - 4
3 - 0
-
-
-
Reserved
RO tkc [11:8] of touch key charge counter.
6.34.Touch Key Charge Counter Low Register (tkcl), IO address = 0x2C
Bit
Reset R/W
RO tkc [7:0] of touch key charge counter.
Description
7 - 0
-
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
7. Instructions
Symbol
Description
ACC
a
Accumulator ( Abbreviation of accumulator )
Accumulator ( Symbol of accumulator in program )
sp
flag
I
Stack pointer
ACC status flag register
Immediate data
&
Logical AND
|
Logical OR
←
^
Movement
Exclusive logic OR
+
Add
-
〜
〒
OV
Z
Subtraction
NOT (logical complement, 1’s complement)
NEG (2’s complement)
Overflow (The operational result is out of range in signed 2’s complement number system)
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction in
unsigned number system)
C
AC
Auxiliary Carry (If there is a carry out from low nibble after the result of ALU operation, this bit is set to 1)
Only addressed in 0~0x3F (0~63) is allowed
M.n
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
7.1. Data Transfer Instructions
mov
mov
mov
mov
mov
a, I
Move immediate data into ACC.
Example: mov a, 0x0f;
Result: a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M, a
a, M
a, IO
IO, a
Move data from ACC into memory
Example: mov
MEM, a;
Result: MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result: a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from IO into ACC
Example: mov
a, pa ;
Result: a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from ACC into IO
Example: mov
Result: pa ← a
pa, a;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
ldt16 word
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
clear
clear
stt16
…
lb@ T16val ;
hb@ T16val ;
T16val ;
// clear T16val (LSB)
// clear T16val (MSB)
// initial T16 with 0
set1
…
t16m.5 ;
// enable Timer16
set0
ldt16
….
t16m.5 ;
T16val ;
// disable Timer 16
// save the T16 counting value to T16val
------------------------------------------------------------------------------------------------------------------------
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
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12 Touch Keys OTP Controller
stt16 word
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
mov
mov
mov
mov
stt16
…
a, 0x34 ;
lb@ T16val , a ; // move 0x34 to T16val (LSB)
a, 0x12 ;
hb@ T16val , a ; // move 0x12 to T16val (MSB)
T16val ;
// initial T16 with 0x1234
----------------------------------------------------------------------------------------------------------------------
idxm a, index Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
idxm
a, RAMIndex ; // move memory data in address 0x5B to ACC
------------------------------------------------------------------------------------------------------------------------
Idxm index, a Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
mov
idxm
a, 0xA5 ;
RAMIndex, a ;
// move 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
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12 Touch Keys OTP Controller
xch
M
Exchange data between ACC and memory
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
pushaf
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
.romadr 0x10 ;
// ISR entry address
pushaf ;
…
// put ACC and flag into stack memory
// ISR program
…
// ISR program
popaf ;
reti ;
// restore ACC and flag from stack memory
------------------------------------------------------------------------------------------------------------------------
Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
popaf
Result:
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sp ← sp - 2
;
7.2. Arithmetic Operation Instructions
add
add
add
a, I
Add immediate data with ACC, then put result into ACC
Example: add a, 0x0f ;
Result: a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
M, a
Add data in memory with ACC, then put result into ACC
Example: add
a, MEM ;
Result: a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result: MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc a, M
addc M, a
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result: a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
Result: MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM, a ;
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
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12 Touch Keys OTP Controller
addc
addc
sub
a
Add carry with ACC, then put result into ACC
Example: addc a ;
Result: a ← a + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result: MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, I
a, M
M, a
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result: a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
Subtraction data in memory from ACC, then put result into ACC
Example: sub
a, MEM ;
Result: a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
Subtraction data in ACC from memory, then put result into memory
Example: sub
MEM, a;
Result: MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc a, M
subc M, a
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
a, MEM;
Result: a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result: MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc
subc
inc
a
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result: a ← a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Subtraction carry from the content of memory, then put result into memory
Example: subc
MEM;
Result: MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment the content of memory
Example: inc
MEM ;
Result: MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dec
M
Decrement the content of memory
Example: dec
MEM;
Result: MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
clear
M
Clear the content of memory
Example: clear
Result: MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
MEM ;
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Page 61 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
7.3. Shift Operation Instructions
sr
a
Shift right of ACC, shift 0 to bit 7
Example: sr a ;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry bit 7 to flag
src
sr
a
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory, shift 0 to bit 7
Example: sr MEM ;
M
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry bit 7 to flag
src
sl
M
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC shift 0 to bit 0
a
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry bit 0 to flag
slc
sl
a
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory, shift 0 to bit 0
M
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry bit 0 to flag
slc
M
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
swap
a
Example: swap
Result: a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
a ;
©Copyright 2020, PADAUK Technology Co. Ltd
Page 62 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
7.4. Logic Operation Instructions
and
and
and
or
a, I
a, M
M, a
a, I
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and a, 0x0f ;
Result: a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result: a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result: MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result: a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
a, M
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result: a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
M, a
a, I
Perform logic OR on ACC and memory, then put result into memory
Example: or
MEM, a ;
Result: MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
xor
xor
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
a, 0x0f ;
Result: a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
Perform logic XOR on ACC and IO register, then put result into IO register
Example: xor
pa, a ;
Result: pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
xor
xor
not
a, M
M, a
a
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result: a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform 1’s complement (logical complement) of ACC
Example: not
Result: a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a ;
©Copyright 2020, PADAUK Technology Co. Ltd
Page 63 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
not
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC7
------------------------------------------------------------------------------------------------------------------------
Perform 1’s complement (logical complement) of memory
not
M
Example: not
MEM ;
Result: MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC7
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of ACC
neg
a
Example: neg
a;
Result: a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
neg
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC8
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of memory
neg
M
Example: neg
MEM;
Result: MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
Page 64 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
7.5. Bit Operation Instructions
set0 IO.n
set1 IO.n
set0 M.n
set1 M.n
swapc IO.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of IO port to high
Example: set1 pa.5 ;
Result: set bit 5 of port A to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to low
Example: set0 MEM.5 ;
Result: set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Swap the nth bit of IO port with carry bit
Example: swapc
IO.0;
Result: C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Application Example1 (serial output) :
...
set1
...
pac.0 ;
// set PA.0 as output
set0
swapc
set1
swapc
...
flag.1 ;
pa.0 ;
// C=0
// move C to PA.0 (bit operation), PA.0=0
// C=1
flag.1 ;
pa.0 ;
// move C to PA.0 (bit operation), PA.0=1
Application Example2 (serial input) :
...
set0
...
pac.0 ;
// set PA.0 as input
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift C to bit 7 of ACC
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift new C to bit 7, old C
...
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
Page 65 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
7.6. Conditional Operation Instructions
ceqsn a, I
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a - I)
Example: ceqsn
a, 0x55 ;
MEM ;
error ;
inc
goto
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
ceqsn a, M
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
cneqsn a, M
cneqsn a, I
Example: cneqsn
a, MEM;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example: cneqsn
a,0x55 ;
MEM ;
error ;
inc
goto
Result: If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low
t0sn IO.n
t1sn IO.n
t0sn M.n
t1sn M.n
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high
Example: t1sn
pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
Example: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
izsn
a
Increment ACC and skip next instruction if ACC is zero
Example: izsn
Result:
a;
a
←
a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 66 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
dzsn
izsn
a
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn a;
Result: A - 1,skip next instruction if a = 0
A
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment memory and skip next instruction if memory is zero
Example: izsn
Result: MEM
MEM;
MEM + 1, skip next instruction if MEM= 0
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dzsn
M
Decrement memory and skip next instruction if memory is zero
Example: dzsn
Result: MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM;
←
MEM - 1, skip next instruction if MEM = 0
7.7. System control Instructions
call
label
Function call, address can be full range address space
Example: call
function1;
pc + 1
Result: [sp]
←
pc
sp
←
←
function1
sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
goto label
Go to specific address which can be full range address space
Example: goto
error;
Result: Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Place immediate data to ACC, then return
Example: ret 0x55;
ret
ret
I
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program which had function call
Example: ret;
Result:
sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
reti
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
No operation
nop
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Next program counter is current program counter plus ACC.
Example: pcadd a;
pcadd
a
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 67 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
Application Example:
------------------------------------------------------------------------------------------------------------------------
…
mov
pcadd
goto
goto
goto
goto
…
a, 0x02 ;
a ;
// PC <- PC+2
// jump here
err1 ;
correct ;
err2 ;
err3 ;
correct:
// jump here
…
------------------------------------------------------------------------------------------------------------------------
Enable global interrupt enable
engint
Example: engint;
Result: Interrupt request can be sent to FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Disable global interrupt enable
disgint
stopsys
stopexe
Example: disgint ;
Result: Interrupt request is blocked from FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
System halt.
Example: stopsys;
Result: Stop the system clocks and halt the system
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
CPU halt. The oscillator module is still active to output clock, however, system clock is disabled
to save power.
Example: stopexe;
Result: Stop the system clocks and keep oscillator modules active.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset the whole chip, its operation will be same as hardware reset.
Example: reset;
reset
Result: Reset the whole chip.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset Watchdog timer.
wdreset
Example: wdreset ;
Result: Reset Watchdog timer.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7.8. Summary of Instructions Execution Cycle
goto, call, pcadd, ret, reti , idxm
2T
2T
1T
1T
Condition is fulfilled.
ceqsn, cneqsn, t0sn, t1sn, dzsn, izsn
Condition is not fulfilled.
Others
©Copyright 2020, PADAUK Technology Co. Ltd
Page 68 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
7.9. Summary of affected flags by Instructions
Instruction
mov a, I
Z
-
C
-
AC OV Instruction
Z
-
C
-
AC OV Instruction
Z
Y
-
C
-
AC OV
-
-
-
-
mov M, a
mov IO, a
idxm a, index
pushaf
-
-
-
-
mov a, M
ldt16 word
idxm index, a
popaf
-
-
-
-
mov a, IO
stt16 word
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
xch
M
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, I
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, M
addc M, a
sub a, I
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
add M, a
addc a, M
addc
a
addc
M
sub a, M
sub M, a
subc a, M
subc M, a
subc
dec
src
a
subc
clear
M
M
inc
sr a
src
sl
M
M
M
a
sr
M
-
Y
Y
-
-
-
-
-
-
sl
a
-
-
-
slc
a
-
-
-
M
-
-
-
slc
and
M
-
-
-
swap
and
a
-
-
-
and
a, I
Y
Y
Y
Y
Y
-
-
-
a, M
Y
Y
-
-
-
M, a
Y
Y
Y
Y
-
-
-
-
or a, I
-
-
-
or a, M
-
-
-
or M, a
-
-
-
xor
xor
neg
a, I
-
-
-
xor
not
neg
IO, a
-
-
-
xor
not
a, M
-
-
-
M, a
a
-
-
-
a
Y
Y
-
-
-
-
M
-
-
-
-
-
-
M
-
-
-
set0 IO.n
set1 M.n
t0sn IO.n
t1sn M.n
-
-
-
set1 IO.n
ceqsn a, I
t1sn IO.n
-
-
-
set0 M.n
ceqsn a, M
t0sn M.n
-
-
-
-
-
-
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
-
-
-
-
-
-
-
-
izsn
dzsn
ret
a
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
dzsn
call
a
Y
-
Y
-
Y
-
Y
-
izsn
M
Y
-
Y
-
Y
-
Y
-
M
label
goto label
reti
I
ret
-
-
-
-
-
-
-
-
nop
-
-
-
-
pcadd
a
-
-
-
-
engint
-
-
-
-
disgint
-
-
-
-
stopsys
-
-
-
-
-
-
-
-
stopexe
-
-
-
-
-
-
-
reset
-
-
-
-
swapc IO.n
ceqsn a, I
wdreset
Y
Y
Y
Y
Y
cneqsn a, M
Y
Y
Y
Y
7.10. BIT definition
Bit access of RAM is only available for address from 0x00 to 0x3F.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 69 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
8. Code Option Table
Option
Selection
Description
Enable
Disable
4.0V
OTP content is protected and program connot be read back
OTP content is not protected so program can be read back
LVR typical range 4.0V
Security
3.5V
LVR typical range 3.5V
3.0V
LVR typical range 3.0V
2.75V
2.5V
LVR typical range 2.75V
LVR
LVR typical range 2.5V
2.2V
LVR typical range 2.2V
2.0V
LVR typical range 2.0V
1.8V
LVR typical range 1.8V
IO Drive/Sink current is Low
IO Drive/Sink current is Normal
Low
Drive
Normal
When tm2c[7:4]= 0010, TM2 clock source = IHRC = 16MHZ
When tm3c[7:4]= 0010, TM3 clock source = IHRC = 16MHZ
16MHZ
32MHZ
6 Bit
TMx_Source
When tm2c[7:4]= 0010, TM2 clock source = IHRC*2 = 32MHZ
When tm3c[7:4]= 0010, TM3 clock source = IHRC*2 = 32MHZ
(ICE doesn’t support.)
When tm2s.7=1, TM2 PWM resolution is 6 Bit
When tm3s.7=1, TM3 PWM resolution is 6 Bit
TMx_Bit
When tm2s.7=1, TM2 PWM resolution is 7 Bit
When tm3s.7=1, TM3 PWM resolution is 7 Bit
(ICE doesn’t support.)
7 Bit
All Edge
GPC INT both Rising & Falling edge trigger
Comparator Edge Rising_Edge GPC INT both Rising edge trigger
Falling_Edge GPC INT both Falling edge trigger
Disable
Enable
PA.0
Comparator does not control all PWM outputs
GPC_PWM
Interrupt Src0
PA7_Sel
Comparator controls all PWM outputs (ICE doesn’t support.)
INTEN/INTRQ.Bit0 is from PA.0
PA.5
INTEN/INTRQ.Bit0 is from PA.5 (ICE doesn’t support.)
Configure pad PA7/CS as CS pad of Touch
Configure pad PA7/CS as normal PA7 IO pad
Disable EMI optimize option
As_CS
As_IO
Disable
Enable
EMI
The system clock will be slightly vibrated for better EMI performance
Table 8: Code Option
©Copyright 2020, PADAUK Technology Co. Ltd
Page 70 of 74
PDK-DS-PMS164-EN-V000 – Mar. 25, 2020
PMS164
12 Touch Keys OTP Controller
9. Special Notes
This chapter is to remind user who use PMS164 IC in order to avoid frequent errors upon operation.
9.1. Warning
User must read all application notes of the IC by detail before using it. Please download the related
application notes from the company website.
9.2. Using IC
9.2.1. IO pin usage and setting
(1) IO pin is set to be digital input
When IO is as digital input, the level of Vih and Vil would changes with the voltage and temperature.
Please follow the minimum value of Vih and the maximum value of Vil.
The value of internal pull high resistor would also changes with the voltage, temperature and pin
voltage. It is not the fixed value.
(2) IO pin is set to be digital input and enable wakeup function
Configure IO pin as input
Set PADIER and PBDIER registers to set the corresponding bit to 1.
(3) PA5 is set to be output pin
PA5 can be set to be Open-Drain output pin only, output high requires adding pull-up resistor.
(4) PA5 is set to be PRSTB input pin
Configure PA5 as input
Set CLKMD.0=1 to enable PA5 as PRSTB input pin
(5) PA5 is set to be input pin and to connect with a push button or a switch by a long wire
Needs to put a >33Ω resistor in between PA5 and the long wire
Avoid using PA5 as input in such application.
9.2.2. Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit.
Step2: Clear INTRQ register.
Step3: In the main program, using ENGINT to enable CPU interrupt function.
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine.
Step5: After the Interrupt Service Routine being executed, return to the main program.
*Use DISGINT in the main program to disable all interrupts.
*When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG register.
POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service routine
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12 Touch Keys OTP Controller
{
}
// enter DISGINT status automatically, no more interrupt is accepted
PUSHAF;
…
POPAF;
// RETI will be added automatically. After RETI being executed, ENGINT status will be restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function.
9.2.3. System clock switching
System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock and
turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Switch system clock from ILRC to IHRC/2
CLKMD
=
0x36;
0;
// switch to IHRC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
ERROR. Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD 0x50; // MCU will hang
=
9.2.4. Power down mode, wakeup and watchdog
Watchdog will be inactive once ILRC is disabled.
9.2.5. TIMER time out
When select $ INTEGS BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M
counts from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the
second interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8 as
1 to generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M counter
is restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
If select $ INTEGS BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the T16M
counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences with
setting INTEGS methods.
9.2.6. IHRC
(1) The IHRC frequency calibration is performed when IC is programmed by the writer.
(2) Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the IHRC
frequency (either for package or COB), if the calibration is done before molding process, the actual IHRC
frequency after molding may be deviated or becomes out of spec. Normally , the frequency is getting
slower a bit.
(3) It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not take
any responsibility for this situation.
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12 Touch Keys OTP Controller
(4) Users can make some compensatory adjustments according to their own experiences. For example, users
can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
9.2.7. LVR
User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working
voltage of chip; Otherwise IC may work abnormally.
9.2.8. Programming Writing
There are 6 signals for programming PMS164: PA3, PA4, PA5, PA6, VDD, and GND.
If using 3S-P-002 to program PMS164, please put the jumper over CN39. For S16 package, please put the
IC at the very top of the Textool. For S08A package, please put the IC downwards by four spaces from the
top of the Textool. Other packages could be programmed by appropriate connection by the users. All the
signals on the left side pins of the jumper are identical and same as the labeled on CN42 at left bottom
corner: they are VDD, PA0 (not required), PA3, PA4, PA5, PA6, PA7(not required), and GND.
If user use 5S-P-003 or above to program, please follow the instruction displayed at the software to connect
the jumper.
Special notes about voltage and current while Multi-Chip-Package(MCP) or On-Board Programming
(1) PA5 (VPP) may be higher than 11V.
(2) VDD may be higher than 6.5V, and its maximum current may reach about 20mA.
(3) All other signal pins level (except GND) are the same as VDD.
User should confirm when using this product in MCP or On-Board Programming, the peripheral circuit or
components will not be destroyed or limit the above voltages.
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12 Touch Keys OTP Controller
9.3. Using ICE
(1) The following items should be noted when using 5S-I-S01/2(B) to emulate PMS164:
5S-I-S01/2(B) doesn’t support SYSCLK=ILRC/16 and ILRC/64.
5S-I-S01/2(B) doesn’t support PA5 as the interrupt source.
5S-I-S01/2(B) doesn’t support the code options: GPC_PWM, TMx_source, TMx_bit.
5S-I-S01/2(B) doesn’t support ALL touch function.
The PA3 output function will be affected when GPCS selects output to PA0 output.
When simulating PWM waveform, please check the waveform during program running. When the
ICE is suspended or single-step running, its waveform may be inconsistent with the reality.
The ILRC frequency of the PDK5S-I-S01/2(B) simulator is different from the actual IC and is
uncalibrated, with a frequency range of about 34K~38KHz.
Fast Wakeup time is different from 5S-I-S01/2(B): 128 SysClk, PMS164: 45 ILRC.
Watch dog time out period is different from 5S-I-S01/2(B).
WDT period
misc[1:0]=00
misc[1:0]=01
misc[1:0]=10
misc[1:0]=11
5S-I-S01/2(B)
2048 * TILRC
4096 * TILRC
16384 * TILRC
256 * TILRC
PMS164
8192 * TILRC
16384 * TILRC
65536 * TILRC
262144 * TILRC
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