P2040CF-08ST [ONSEMI]
2040 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8;
| 型号： | P2040CF-08ST |
| 厂家： | 
ONSEMI |
| 描述： | 2040 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总7页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P2040C
LCD Panel EMI Reduction IC
Description
The P2040C is a selectable spread spectrum frequency modulator
designed specifically for digital flat panel applications. The P2040C
reduces electromagnetic interference (EMI) at the clock source which
provides system wide reduction of EMI of all clock dependent signals.
The P2040C allows significant system cost savings by reducing the
number of circuit board layers and shielding that are traditionally
required to pass EMI regulations.
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The P2040C uses the most efficient and optimized modulation
profile approved by the FCC and is implemented in a proprietary
all−digital method. The P2040C modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock and, more
importantly, decreases the peak amplitudes of its harmonics. This
results in a significantly lower system EMI compared to the typical
narrow band signal produced by oscillators and most frequency
generators. Lowering EMI by increasing a signal’s bandwidth is called
‘spread spectrum clock generation.’
SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
PIN CONFIGURATION
1
Applications
VDD
CLKIN
MRA
SR1
The P2040C is targeted towards digital flat panel applications for
Notebook PCs, Palm−size PCs, Office Automation Equipments, and
LCD Monitors.
SR0
P2040C
ModOUT
SSON#
VSS
Features
(Top View)
• FCC Approved Method of EMI Attenuation
• Provides up to 15 dB of EMI Suppression
• Generates a Low EMI Spread Spectrum Clock of the Input
Frequency
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
• 50 MHz to 173 MHz Input Frequency Range
• Optimized for 54 MHz, 65 MHz, 81 MHz, 140 MHz, and 162 MHz
Pixel Clock Frequencies
• Internal Loop Filter Minimizes External Components and Board
Space
• 8 Selectable Spread Ranges, up to 2.2%
• SSON# Control Pin for Spread Spectrum Enable and Disable Options
• 2 Selectable Modulation Rates
• Low Cycle−to−Cycle Jitter
• 3.3 V Operating Voltage
• Ultra Low Power CMOS Design
• Supports Most Mobile Graphic Accelerator and LCD Timing
Controller Specifications
• Available in 8−pin SOIC and TSSOP Packages
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
August, 2011 − Rev. 3
P2040C/D
P2040C
VDD
SR0 SR1 MRA SSON#
PLL
Modulation
CLKIN
Frequency
Divider
Output
Divider
Loop
Filter
Phase
Detector
VCO
Feedback
Divider
ModOUT
VSS
Figure 1. Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Unit
V
VDD, V
Voltage on any pin with respect to Ground
−0.5 to +4.6
−65 to +125
−40 to +125
260
IN
T
STG
Storage temperature
°C
T
A
Operating temperature
°C
T
s
Max. Soldering Temperature (10 sec)
°C
q
Thermal Resistance from Junction to Ambient
(No Air Flow)
For SOIC Package
156.5
°C/W
JA
For TSSOP Package
124
T
J
Junction Temperature
150
°C
T
DV
Static Discharge Voltage (As per JEDEC STD22− A114−B)
2
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 2. PIN DESCRIPTION
Pin#
Pin Name
CLKIN
MRA
Type
Description
1
2
3
4
5
I
I
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull−up resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor.
Ground to entire chip. Connect to system ground.
SR1
I
VSS
P
I
SSON#
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function
enabled when LOW, disabled when HIGH. This pin has an internal pull−low resistor.
6
7
8
ModOUT
SR0
O
I
Spread spectrum Clock Output.
Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor.
Power supply for the entire chip.
VDD
P
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2
P2040C
Table 3. MODULATION SELECTION (Commercial)
Spreading Range
81 MHz
1.0%
54 MHz
1.4%
2.0%
1.1%
1.8%
1.3%
2.2%
1.4%
2.1%
65 MHz
1.2%
1.9%
0.9%
1.5%
1.3%
2.1%
1.3%
2.1%
140 MHz
0.6%
162 MHz
0.4%
0.8%
0.3%
0.4%
1.1%
1.8%
0.9%
1.4%
MRA
SR1
0
SR0
0
Modulation Rate
(Fin/80) * 62.49 KHz
(Fin/80) * 62.49 KHz
(Fin/80) * 62.49 KHz
(Fin/80) * 62.49 KHz
(Fin/80) * 20.83 KHz
(Fin/80) * 20.83 KHz
(Fin/80) * 20.83 KHz
(Fin/80) * 20.83 KHz
0
0
0
0
1
1
1
1
0
1
1.6%
1.0%
1
0
0.5%
0.3%
1
1
1.0%
0.54%
1.25%
2.0%
0
0
1.3%
0
1
2.1%
1
0
1.4%
1.2%
1
1
2.1%
1.9%
Spread Spectrum Selection
Example:
Table 3 illustrates the possible spread spectrum options.
The optimal setting should minimize system EMI to the
fullest without affecting system performance. The spreading
is described as a percentage deviation of the center
frequency (Note: The center frequency is the frequency of
the external reference input on CLKIN, Pin 1).
P2040C is designed for high resolution flat panel
applications and is able to support panel frequencies from
50 MHz to 173 MHz. For a 65 MHz pixel clock frequency,
a spreading selection of MRA = 0, SR1 = 1 and SR0 = 1
provides a percentage deviation of 1.50% (see Table 3).
This result in frequency on ModOUT being swept from
64.03 MHz to 65.98 MHz at a modulation rate of 50.77 KHz
(see Table 3). This particular example (see figure below)
given here is a common EMI reduction method for notebook
LCD panel and has already been implemented by most of the
leading OEM and mobile graphic accelerator
manufacturers.
+3.3 V
Modulated 65 MHz signal with
1.5% deviation and modulation
rate of 50.77 KHz. This signal is
connected back to the spread
spectrum input pin (SSIN) of the
graphics accelerator.
65 MHz from graphics accelerator.
1
2
3
4
VDD
SR0
8
7
6
5
CLKIN
MRA
SR1
0.1 mF
ModOUT
VSS
SSON#
P2040C
Digital control for the SS
enable or disable.
Figure 2. Application Schematic for Mobile LCD Graphics Controllers
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3
P2040C
Table 4. DC ELECTRICAL CHARACTERISTICS
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated.)
Symbol
Parameter
Min
Typ
−
Max
Unit
V
V
Input low voltage
Input high voltage
VSS−0.3
0.8
IL
IH
IL
V
2.0
−
−
VDD+0.3
V
I
Input low current (pull−up resistor on inputs SR0, SR1 and MRA)
Input high current (pull−down resistor on input SSON#)
−
−40
40
0.4
−
mA
mA
V
I
IH
−
−
V
Output low voltage (VDD = 3.3 V, I = 20 mA)
−
−
OL
OH
DD
CC
OL
V
Output high voltage (VDD = 3.3 V, I = 20 mA)
2.5
−
−
V
OL
I
I
Static supply current standby mode
Dynamic supply current (3.3 V and 10 pF loading)
Operating Voltage
0.7
16
3.3
0.18
50
−
mA
mA
V
9
22
3.6
−
VDD
3.0
−
t
Power−up time (first locked cycle after power up)
Clock output impedance
mS
W
ON
Z
OUT
−
−
Table 5. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min
50
0.3
0.3
−
Typ
Max
173
1.0
1.0
360
55
Unit
MHz
nS
f
IN
Input frequency
t
t
(Note 1)
(Note 1)
Output rise time (measured at 0.8 V to 2.0 V)
Output fall time (measured at 2.0 V to 0.8 V)
Jitter (cycle−to−cycle)
0.7
0.7
−
LH
nS
HL
t
JC
pS
t
D
Output duty cycle
45
50
%
1. t and t are measured into a capacitive load of 15 pF.
LH
HL
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4
P2040C
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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5
P2040C
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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6
P2040C
Table 6. ORDERING INFORMATION
Part Number
P2040CF−08ST
P2040CF−08SR
P2040CF−08TT
P2040CF−08TR
I2040CF−08ST
I2040CF−08SR
I2040CF−08TT
I2040CF−08TR
X2040CF−08ST
X2040CF−08SR
X2040CF−08TT
X2040CF−08TR
P2040CG−08ST
P2040CG−08SR
P2040CG−08TT
P2040CG−08TR
I2040CG−08ST
I2040CG−08SR
I2040CG−08TT
I2040CG−08TR
X2040CG−08ST
X2040CG−08SR
X2040CG−08TT
X2040CG−08TR
Marking
P2040CF
P2040CF
P2040CF
P2040CF
I2040CF
I2040CF
I2040CF
I2040CF
X2040CF
X2040CF
X2040CF
X2040CF
P2040CG
P2040CG
P2040CG
P2040CG
I2040CG
I2040CG
I2040CG
I2040CG
X2040CG
X2040CG
X2040CG
X2040CG
Package Type
Temperature
Commercial
Commercial
Commercial
Commercial
Industrial
8−Pin SOIC, TUBE, Pb Free
8−Pin SOIC, TAPE & REEL, Pb Free
8−Pin TSSOP, TUBE, Pb Free
8−Pin TSSOP, TAPE & REEL, Pb Free
8−Pin SOIC, TUBE, Pb Free
8−Pin SOIC, TAPE & REEL, Pb Free
8−Pin TSSOP, TUBE, Pb Free
8−Pin TSSOP, TAPE & REEL, Pb Free
8−Pin SOIC, TUBE, Pb Free
Industrial
Industrial
Industrial
Automotive
Automotive
Automotive
Automotive
Commercial
Commercial
Commercial
Commercial
Industrial
8−Pin SOIC, TAPE & REEL, Pb Free
8−Pin TSSOP, TUBE, Pb Free
8−Pin TSSOP, TAPE & REEL, Pb Free
8−Pin SOIC, TUBE, Green
8−Pin SOIC, TAPE & REEL, Green
8−Pin TSSOP, TUBE, Green
8−Pin TSSOP, TAPE & REEL, Green
8−Pin SOIC, TUBE, Green
8−Pin SOIC, TAPE & REEL, Green
8−Pin TSSOP, TUBE, Green
Industrial
Industrial
8−Pin TSSOP, TAPE & REEL, Green
8−Pin SOIC, TUBE, Green
Industrial
Automotive
Automotive
Automotive
Automotive
8−Pin SOIC, TAPE & REEL, Green
8−Pin TSSOP, TUBE, Green
8−Pin TSSOP, TAPE & REEL, Green
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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P2040C/D
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