NTHD5903T1_05 [ONSEMI]
Power MOSFET -20 V, -3.0 A, Dual P-Channel ChipFET; 功率MOSFET -20 V， -3.0 A，双P沟道ChipFET
| 型号： | NTHD5903T1_05 |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET -20 V, -3.0 A, Dual P-Channel ChipFET |
| 文件： | 总6页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTHD5903
Power MOSFET
−20 V, −3.0 A, Dual P−Channel ChipFETE
Features
• Low R
for Higher Efficiency
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DS(on)
• Logic Level Gate Drive
• Miniature ChipFET Surface Mount Package Saves Board Space
• Pb−Free Package is Available
V
R
DS(on)
TYP
I MAX
D
(BR)DSS
130 mW @ −4.5 V
215 mW @ −2.5 V
−20 V
−3.0 A
Applications
• Power Management in Portable and Battery−Powered Products;
S
S
1
2
i.e., Cellular and Cordless Telephones and PCMCIA Cards
G
G
2
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Steady
State
D
D
Rating
Drain−Source Voltage
Gate−Source Voltage
Continuous Drain Current
Symbol
5 secs
Unit
V
2
1
V
DS
V
GS
−20
P−Channel MOSFET
P−Channel MOSFET
"12
"10
V
I
A
D
ChipFET
CASE 1206A
STYLE 2
(T = 150°C) (Note 1)
J
T = 25°C
A
"3.0
"2.2
"2.2
"1.6
A
T = 85°C
Pulsed Drain Current
I
A
A
DM
PIN
MARKING
DIAGRAM
Continuous Source Current
(Diode Conduction) (Note 1)
I
−3.0
−2.2
S
CONNECTIONS
Maximum Power Dissipation
(Note 1)
P
W
D
8
7
6
5
1
2
3
4
D
1
D
1
D
2
D
2
S
1
2
3
4
8
7
6
5
1
T = 25°C
2.1
1.1
1.1
0.6
A
G
S
T = 85°C
1
A
Operating Junction and Storage
Temperature Range
T , T
J
−55 to +150
°C
stg
2
G
2
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
A7 = Specific Device Code
M
G
= Month Code
= Pb−Free Package
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
ORDERING INFORMATION
†
Device
Package
Shipping
NTHD5903T1
NTHD5903T1G
ChipFET
3000/Tape & Reel
3000/Tape & Reel
ChipFET
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
November, 2005 − Rev. 4
NTHD5903/D
NTHD5903
THERMAL CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Maximum Junction−to−Ambient (Note 2)
t v 5 s
Steady State
R
q
JA
°C/W
50
90
60
110
Maximum Junction−to−Foot (Drain) Steady State
R
q
JF
30
40
°C/W
2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
Static
Gate Threshold Voltage
Gate−Body Leakage
V
V
= V , I = −250 mA
−0.6
V
GS(th)
DS
GS
D
I
V
= 0 V, V = "12 V
"100
−1.0
nA
mA
GSS
DSS
DS
GS
Zero Gate Voltage Drain Current
I
V
= −16 V, V = 0 V
GS
DS
DS
V
= −16 V, V = 0 V,
−5.0
GS
T = 85°C
J
On−State Drain Current (Note 3)
I
V
v −5.0 V, V = −4.5 V
−10
A
D(on)
DS
GS
Drain−Source On−State Resistance (Note 3)
r
V
V
V
= −4.5 V, I = −2.2 A
0.130
0.150
0.215
5.0
0.155
0.180
0.260
W
DS(on)
GS
GS
GS
D
= −3.6 V, I = −2.0 A
D
= −2.5 V, I = −1.7 A
D
Forward Transconductance (Note 3)
Diode Forward Voltage (Note 3)
g
fs
V
= −10 V, I = −2.2 A
S
V
DS
D
V
I
= −2.2 A, V = 0 V
−0.8
−1.2
7.4
SD
S
GS
Dynamic (Note 4)
Total Gate Charge
Q
3.7
0.8
1.3
13
35
25
25
40
nC
ns
g
V
= −10 V, V = −4.5 V,
GS
DS
Gate−Source Charge
Gate−Drain Charge
Turn−On Delay Time
Rise Time
Q
gs
Q
gd
I
= −2.2 A
D
t
20
55
40
40
80
d(on)
V
= −10 V, R = 10 W
L
t
DD
r
I
^ −1.0 A, V
= −4.5 V,
D
GEN
Turn−Off Delay Time
Fall Time
t
d(off)
R = 6 W
G
t
f
Source−Drain Reverse Recovery Time
t
I = −2.2 A, di/dt = 100 A/ms
F
rr
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
4. Guaranteed by design, not subject to production testing.
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2
NTHD5903
TYPICAL ELECTRICAL CHARACTERISTICS
10
8
10
V
= −4 V − 10 V
GS
−3.6 V
125°C
8
6
4
−3.4 V
−3 V
25°C
T
= −55°C
C
T = 25°C
J
6
−2.8 V
−2.6 V
−2.4 V
4
V
= −1.4 V
GS
2
0
2
0
−2.2 V
−1.8 V
0
1
2
3
4
5
6
0
1
2
3
4
5
−V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
−V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.4
4
3
2
T = 25°C
J
I
= −2.2 A
D
0.35
0.3
T = 25°C
J
V
= −2.5 V
GS
0.25
0.2
V
= −3.6 V
= −4.5 V
GS
0.15
1
0
V
GS
0.1
0.05
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
−V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
−I DRAIN CURRENT (AMPS)
D,
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.6
1.4
1.2
1
1.0E−6
1.0E−7
I
V
= −2.2 A
V
= 0 V
GS
D
= −4.5 V
GS
T = 150°C
J
T = 100°C
J
1.0E−8
1.0E−9
T = 25°C
J
1.0E−10
1.0E−11
0.8
0.6
−50 −25
0
25
50
75
100
125 150
0
4
8
12
16
20
T , JUNCTION TEMPERATURE (°C)
J
−V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTHD5903
TYPICAL ELECTRICAL CHARACTERISTICS
5
11
10
9
600
500
400
300
200
Q
g
V
= 0 V
V
= 0 V
GS
DS
C
C
T = 25°C
J
iss
4
3
2
1
0
8
7
rss
6
5
Q
gd
Q
gs
4
3
C
oss
I = −2.2 A
D
T = 25°C
J
2
100
0
1
0
0
1
2
3
4
−12 −8
−4
0
4
8
12
16
20
−V
GS
−V
DS
Q , TOTAL GATE CHARGE (nC)
g
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
100
5
4
3
2
V
I
V
= −10 V
= −1.0 A
= −4.5 V
V
= 0 V
DD
GS
t
d(off)
T = 25°C
J
D
t
f
GS
t
r
t
d(on)
10
1
0
1
1
10
R , GATE RESISTANCE (OHMS)
100
0
0.2
0.4
0.6
0.8
1
1.2
−V , SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
2
1
Duty Cycle = 0.5
0.2
Notes:
P
DM
t
1
0.1
t
2
0.1
t
0.05
0.02
1
1. Duty Cycle, D =
t
2
thJA
(t)
2. Per Unit Base = R
= 90°C/W
3. T
T = P
A
Z
JM −
DM thJA
Single Pulse
4. Surface Mounted
0.01
−4
−3
10
−2
10
−1
10
10
1
10
100
600
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient
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4
NTHD5903
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
1.092
0.043
0.635
0.025
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.254
0.010
0.66
0.026
0.66
mm
inches
ǒ
Ǔ
SCALE 20:1
0.026
Figure 12. Basic
Figure 13. Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
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5
NTHD5903
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
NOTES:
D
q
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
L
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
H
E
E
MILLIMETERS
INCHES
NOM
0.041
0.012
0.006
DIM
A
b
c
D
MIN
1.00
0.25
0.10
2.95
1.55
NOM
1.05
MAX
MIN
MAX
0.043
0.014
0.008
0.122
0.067
e1
b
1.10
0.35
0.20
3.10
1.70
0.039
0.010
0.004
0.116
0.061
c
0.30
e
0.15
3.05
0.120
0.065
E
1.65
e
e1
L
0.65 BSC
0.55 BSC
0.35
1.90
5° NOM
0.025 BSC
0.022 BSC
0.014
0.075
5° NOM
0.28
1.80
0.42
2.00
0.011
0.071
0.017
0.079
A
H
E
q
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
0.05 (0.002)
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHD5903/D
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