NTHD5905T1 [ETC]

TRANSISTOR | MOSFET | MATCHED PAIR | P-CHANNEL | 8V V(BR)DSS | 3A I(D) | LLCC ; 晶体管| MOSFET |匹配对| P- CHANNEL | 8V V( BR ) DSS | 3A I( D) | LLCC\n
NTHD5905T1
型号: NTHD5905T1
厂家: ETC    ETC
描述:

TRANSISTOR | MOSFET | MATCHED PAIR | P-CHANNEL | 8V V(BR)DSS | 3A I(D) | LLCC
晶体管| MOSFET |匹配对| P- CHANNEL | 8V V( BR ) DSS | 3A I( D) | LLCC\n

晶体 晶体管 开关
文件: 总8页 (文件大小:57K)
中文:  中文翻译
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NTHD5905T1  
Power MOSFET  
Dual P-Channel ChipFETt  
3.0 Amps, 8 Volts  
Features  
http://onsemi.com  
Low R  
for Higher Efficiency  
DS(on)  
Logic Level Gate Drive  
Miniature ChipFET Surface Mount Package  
DUAL P–CHANNEL  
3.0 AMPS, 8 VOLTS  
RDS(on) = 90 mW  
Applications  
Power Management in Portable and Battery–Powered Products; i.e.,  
Cellular and Cordless Telephones and PCMCIA Cards  
S
S
2
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
G
G
2
1
Steady  
State  
Rating  
Symbol  
5 secs  
–8.0  
"8.0  
Unit  
V
Drain–Source Voltage  
Gate–Source Voltage  
Continuous Drain Current  
V
DS  
V
GS  
V
D
D
2
1
I
D
A
(T = 150°C) (Note 1)  
J
P–Channel MOSFET  
P–Channel MOSFET  
T = 25°C  
"4.1  
"2.9  
"3.0  
"2.2  
A
T = 85°C  
A
Pulsed Drain Current  
I
"10  
A
A
DM  
Continuous Source Current  
(Diode Conduction) (Note 1)  
I
S
–1.8  
–0.9  
Maximum Power Dissipation  
(Note 1)  
P
D
W
ChipFET  
T = 25°C  
T = 85°C  
A
2.1  
1.1  
1.1  
0.6  
CASE 1206A  
STYLE 2  
A
Operating Junction and Storage  
Temperature Range  
T , T  
–55 to +150  
°C  
J
stg  
MARKING  
DIAGRAM  
1. Surface Mounted on 1x 1FR4 Board.  
PIN CONNECTIONS  
8
7
6
5
1
2
3
4
D
S
G
S
1
2
3
4
8
7
6
5
1
1
2
2
1
1
2
2
D
D
D
G
A9 = Specific Device Code  
ORDERING INFORMATION  
Device  
NTHD5905T1  
Package  
Shipping  
3000/Tape & Reel  
ChipFET  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
March, 2002 – Rev. 2  
NTHD5905T1/D  
NTHD5905T1  
THERMAL CHARACTERISTICS  
Characteristic  
Symbol  
Typ  
Max  
Unit  
Maximum Junction–to–Ambient (Note 2)  
R
°C/W  
thJA  
t v 5 sec  
Steady State  
50  
90  
60  
110  
Maximum Junction–to–Foot (Drain)  
Steady State  
R
30  
40  
°C/W  
thJF  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
J
Characteristic  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Static  
Gate Threshold Voltage  
V
V
= V , I = –250 mA  
–0.45  
V
GS(th)  
DS  
GS  
D
Gate–Body Leakage  
I
V
DS  
= 0 V, V = "8.0 V  
"100  
–1.0  
–5.0  
nA  
mA  
GSS  
GS  
Zero Gate Voltage Drain Current  
I
V
= –6.4 V, V = 0 V  
GS  
DSS  
DS  
DS  
V
= –6.4 V, V = 0 V,  
GS  
T = 85°C  
J
On–State Drain Current (Note 3)  
I
V
v –5.0 V, V = 4.5 V  
–10  
A
D(on)  
DS  
GS  
Drain–Source On–State Resistance (Note 3)  
r
V
V
V
V
= –4.5 V, I = 3.0 A  
0.075  
0.110  
0.150  
7.0  
0.090  
0.130  
0.180  
W
DS(on)  
GS  
GS  
GS  
DS  
D
= –2.5 V, I = 2.5 A  
D
= –1.8 V, I = 1.0 A  
D
Forward Transconductance (Note 3)  
Diode Forward Voltage (Note 3)  
g
fs  
= –5.0 V, I = 3.0 A  
S
V
D
V
I
= –0.9 A, V = 0 V  
–0.8  
–1.2  
SD  
S
GS  
Dynamic (Note 4)  
Total Gate Charge  
Q
5.5  
0.5  
1.5  
10  
45  
30  
10  
30  
9.0  
nC  
ns  
g
V
= –4.0 V, V = 4.5 V,  
GS  
DS  
Gate–Source Charge  
Gate–Drain Charge  
Turn–On Delay Time  
Rise Time  
Q
gs  
Q
gd  
I
D
= –3.0 A  
t
15  
70  
45  
15  
60  
d(on)  
V
= –4.0 V, R = 4 W  
L
DD  
t
r
I
D
^ –1.0 A, V  
= –4.5 V,  
GEN  
Turn–Off Delay Time  
Fall Time  
t
d(off)  
R
= 6 W  
G
t
f
I = –0.9 A, di/dt = 100 A/ms  
F
Source–Drain Reverse Recovery Time  
t
rr  
2. Surface Mounted on 1x 1FR4 Board.  
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.  
4. Guaranteed by design, not subject to production testing.  
http://onsemi.com  
2
NTHD5905T1  
TYPICAL ELECTRICAL CHARACTERISTICS  
10  
8
10  
T
C
= –55°C  
2.5 V  
V
= 5  
GS  
thru 3 V  
25°C  
8
2 V  
125°C  
6
4
2
0
6
4
1.5 V  
2
1 V  
0
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
0
0
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
10  
6
–V , Drain–to–Source Voltage (V)  
–V , Gate–to–Source Voltage (V)  
DS  
GS  
Figure 1. Output Characteristics  
Figure 2. Transfer Characteristics  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0
1000  
800  
600  
400  
200  
0
V
GS  
= 1.8 V  
C
iss  
V
GS  
= 2.5 V  
V
GS  
= 4.5 V  
C
oss  
C
rss  
2
4
6
8
0
4
8
12  
16  
20  
–V , Drain–to–Source Voltage (V)  
DS  
–I , Drain Current (A)  
D
Figure 3. On–Resistance vs. Drain Current  
Figure 4. Capacitance  
5
1.6  
1.4  
1.2  
1.0  
0.8  
V
GS  
= 4.5 V  
= 3 A  
I
D
4
3
2
1
0
0.6  
–50  
1
2
3
4
5
–25  
0
25  
50  
75  
100  
125 150  
Q
Total Gate Charge (nC)  
T , Junction Temperature (°C)  
J
g,  
Figure 5. Gate Charge  
Figure 6. On–Resistance vs.  
Junction Temperature  
http://onsemi.com  
3
NTHD5905T1  
TYPICAL ELECTRICAL CHARACTERISTICS  
0.25  
10  
0.20  
0.15  
0.10  
0.05  
I
D
= 3 A  
T = 150°C  
J
T = 25°C  
J
0
1
0
1
2
3
4
5
0
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
–V , Gate–to–Source Voltage (V)  
GS  
–V , Drain–to–Source Voltage (V)  
DS  
Figure 7. Source Diode Forward Voltage  
Figure 8. On–Resistance vs. Gate–to–Source  
Voltage  
0.4  
0.3  
50  
40  
30  
I
D
= 250 mA  
0.2  
0.1  
20  
10  
0
0.0  
–0.1  
–0.2  
–4  
–3  
10  
–2  
10  
–1  
–50  
–25  
0
25  
50  
75  
100  
125  
150  
10  
10  
1
10  
100 600  
T , Temperature (°C)  
J
Time (sec)  
Figure 9. Threshold Voltage  
Figure 10. Single Pulse Power  
http://onsemi.com  
4
NTHD5905T1  
TYPICAL ELECTRICAL CHARACTERISTICS  
2
1
Duty Cycle = 0.5  
Notes:  
P
DM  
0.2  
t
1
0.1  
t
2
1
2
0.1  
t
0.05  
0.02  
1. Duty Cycle, D =  
t
2. Per Unit Base = R  
= 90°C/W  
thJA  
(t)  
3. T  
T = P  
A
Z
JM –  
DM thJA  
Single Pulse  
4. Surface Mounted  
0.01  
–4  
–3  
10  
–2  
10  
–1  
10  
10  
1
10  
100  
600  
Square Wave Pulse Duration (sec)  
Figure 11. Normalized Thermal Transient Impedance, Junction–to–Ambient  
2
1
Duty Cycle = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
Single Pulse  
0.01  
–4  
–3  
10  
–2  
10  
–1  
10  
10  
Square Wave Pulse Duration (sec)  
1
10  
Figure 12. Normalized Thermal Transient Impedance, Junction–to–Foot  
http://onsemi.com  
5
NTHD5905T1  
Notes  
http://onsemi.com  
6
NTHD5905T1  
PACKAGE DIMENSIONS  
ChipFET  
CASE 1206A–03  
ISSUE D  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM  
PER SIDE.  
4. LEADFRAME TO MOLDED BODY OFFSET IN  
HORIZONTAL AND VERTICAL SHALL NOT EXCEED  
0.08 MM.  
A
M
K
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
S
B
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE  
BURRS.  
6. NO MOLD FLASH ALLOWED ON THE TOP AND  
BOTTOM LEAD SURFACE.  
7. 1206A-01 AND 1206A-02 OBSOLETE. NEW  
STANDARD IS 1206A-03.  
L
D
J
G
MILLIMETERS  
INCHES  
DIM MIN  
MAX  
MIN  
0.116  
MAX  
0.122  
0.067  
0.043  
0.014  
A
B
C
D
G
J
2.95  
1.55  
1.00  
0.25  
3.10  
STYLE 2:  
1.70 0.061  
1.10 0.039  
0.35 0.010  
PIN 1. SOURCE 1  
2. GATE 1  
C
3. SOURCE 2  
4. GATE 2  
5. DRAIN 2  
6. DRAIN 2  
7. DRAIN 1  
8. DRAIN 1  
0.65 BSC  
0.025 BSC  
0.05 (0.002)  
0.10  
0.28  
0.20 0.004  
0.42 0.011  
0.008  
0.017  
0.022 BSC  
K
L
0.55 BSC  
5 ° NOM  
1.80 2.00  
M
S
5 ° NOM  
0.072  
0.080  
http://onsemi.com  
7
NTHD5905T1  
ChipFET is a trademark of Vishay Siliconix.  
ON Semiconductor is a trademark and  
is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right  
to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products  
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any  
and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets  
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must  
be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.  
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death  
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC  
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees  
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.  
PUBLICATION ORDERING INFORMATION  
Literature Fulfillment:  
JAPAN: ON Semiconductor, Japan Customer Focus Center  
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031  
Phone: 81–3–5740–2700  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada  
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada  
Email: ONlit@hibbertco.com  
Email: r14525@onsemi.com  
ON Semiconductor Website: http://onsemi.com  
For additional information, please contact your local  
Sales Representative.  
N. American Technical Support: 800–282–9855 Toll Free USA/Canada  
NTHD5905T1/D  

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