NTBS2D7N06M7 [ONSEMI]
功率 MOSFET，N 沟道，标准门极，60 V，110 A，2.7 mΩ;
| 型号： | NTBS2D7N06M7 |
| 厂家： | 
ONSEMI |
| 描述： | 功率 MOSFET，N 沟道，标准门极，60 V，110 A，2.7 mΩ |
| 文件： | 总7页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTBS2D7N06M7
N‐Channel PowerTrench)
MOSFET
60 V, 110 A, 2.7 mW
Features
www.onsemi.com
• Typical R
• Typical Q
• UIS Capability
= 2.2 mW at V = 10 V, I = 80 A
GS D
DS(on)
= 80 nC at V = 10 V, I = 80 A
g(tot)
GS
D
D
• These Devices are Pb−Free and are RoHS Compliant
Applications
• Industrial Motor Drive
• Industrial Power Supply
• Industrial Automation
• Battery Operated Tools
• Battery Protection
• Solar Inverters
G
S
• UPS and Energy Inverters
• Energy Storage
• Load Switch
2
D PAK−3
TO−263
CASE 418AJ
ABSOLUTE MAXIMUM RATINGS (T = 25°C, Unless otherwise noted)
J
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
60
Unit
V
V
DSS
MARKING DIAGRAM
V
GS
20
V
Drain Current − Continuous (T = 25°C)
GS
I
D
110
A
C
NTB
S2D7N06M7
AYWWG
(V = 10) (Note 1)
Pulsed Drain Current (T = 25°C)
See
Figure 4
C
Single Pulse Avalanche Energy (Note 2)
Power Dissipation
E
193
176
1.2
mJ
W
AS
P
D
Derate Above 25°C
W/°C
°C
NTBS2D7N06M7= Specific Device Code
Operating and Storage Temperature
Range
T , T
−55 to
+175
A
Y
= Assembly Location
= Year
J
STG
WW
G
= Work Week
= Pb-Free Package
Thermal Resistance, Junction to Case
R
0.85
43
_C/W
_C/W
q
q
JC
Maximum Thermal Resistance, Junction
to Ambient (Note 3)
R
JA
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
1. Current is limited by bondwire configuration.
2. Starting T = 25°C, L = 50 mH, I = 88 A, V = 60 V during inductor
J
AS
DD
charging and V = 0 V during time in avalanche.
DD
3. R
is the sum of the junction−to−case and case−to−ambient thermal
q
JA
resistance, where the case thermal reference is defined as the solder
mounting surface of the drain pins. R is guaranteed by design, while
q
JC
R
is determined by the board design. The maximum rating presented here
q
JA
2
is based on mounting on a 1 in pad of 2oz copper.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
December, 2017 − Rev. 0
NTBS2D7N06M7/D
NTBS2D7N06M7
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Reel Size
Tape Width
Quantity
2
NTBS2D7N06M7
NTBS2D7N
D PAK (TO−263)
330 mm
24 mm
800 Units
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
I
Drain−to−Source Breakdown Voltage
Drain−to−Source Leakage Current
V
V
V
= 0 V, I = 250 mA
60
−
−
−
−
−
1
1
V
DSS
GS
DS
DS
D
= 60 V, V = 0 V, T = 25_C
mA
mA
DSS
GS
J
= 60 V, V = 0 V, T = 175_C
−
GS
J
(Note 4)
I
Gate−to−Source Leakage Current
V
GS
=
20 V
−
−
100
nA
GSS
ON CHARACTERISTICS
V
R
Gate−to−Source Threshold Voltage
Drain−to−Source On Resistance
V
V
V
= V , I = 250 mA
2.0
−
3.2
2.2
4.1
4.0
2.7
5.0
V
GS(th)
GS
GS
GS
DS
D
= 10 V, I = 80 A, T = 25_C
mW
mW
DS(on)
D
J
= 10 V, I = 80 A, T = 175_C
−
D
J
(Note 4)
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 30 V, V = 0 V, f = 1 MHz
−
−
−
−
−
−
−
−
6655
1745
57
−
−
pF
pF
pF
W
iss
DS
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
Gate Resistance
−
rss
R
f = 1 MHz
2.2
80
−
g
Q
Total Gate Charge at 10 V
Threshold Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
V
DD
V
DD
V
DD
V
DD
= 30 V, I = 80 A, V = 0 to 10 V
110
−
nC
nC
nC
nC
g(tot)
D
GS
Q
= 30 V, I = 80 A, V = 0 to 2 V
12
g(th)
D
GS
Q
= 30 V, I = 80 A
35
−
gs
D
Q
= 30 V, I = 80 A
10
−
gd
D
SWITCHING CHARACTERISTICS
t
Turn-On Time
Turn-On Delay
Rise Time
V
DD
V
GS
= 30 V, I = 80 A,
−
−
−
−
−
−
−
115
−
ns
ns
ns
ns
ns
ns
(on)
D
= 10 V, R
= 6 W
GEN
t
36
52
36
13
−
d(on)
t
r
−
t
Turn-Off Delay
Fall Time
−
d(off)
t
f
−
t
Turn-Off Time
64
off
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source−to−Drain Diode Voltage
V
V
V
= 0 V, I = 80 A
−
−
−
−
−
−
1.25
1.2
V
V
SD
GS
GS
DD
SD
= 0 V, I = 40 A
SD
t
Reverse−Recovery Time
Reverse−Recovery Charge
= 48 V, I = 80 A,
78
100
102
130
ns
nC
rr
F
dI /dt = 100 A/ms
SD
Q
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The maximum value is specified by design at T = 175°C. Product is not tested to this condition in production.
J
www.onsemi.com
2
NTBS2D7N06M7
TYPICAL PERFORMANCE CHARACTERISTICS
200
1.2
1.0
0.8
0.6
0.4
0.2
0.0
CURRENT LIMITED
BY SILICON
VGS = 10V
CURRENT LIMITED
BY PACKAGE
150
100
50
0
25
50
75 100 125 150 175 200
TC, CASE TEMPERATURE(oC)
0
25
50
75 100 125 150 175
TC, CASE TEMPERATURE(oC)
Figure 1. Normalized Power Dissipation vs.
Case Temperature
Figure 2. Maximum Continuous Drain Current
vs. Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
1
D = 0.50
0.20
0.10
P
DM
0.05
0.02
t
0.1
1
0.01
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P x Z
x R
+ T
J
DM
qJC
qJC C
0.01
10−5
10−4
10−3
10−2
10−1
100
101
t, RECTANGULAR PULSE DURATION(s)
Figure 3. Normalized Maximum Transient Thermal Impedance
10000
1000
100
VGS = 10V
o
= 25 C
T
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 − T
150
C
I = I
2
SINGLE PULSE
10
10−5
10−4
10−3
10−2
10−1
100
101
t, RECTANGULAR PULSE DURATION(s)
Figure 4. Peak Current Capability
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3
NTBS2D7N06M7
TYPICAL PERFORMANCE CHARACTERISTICS
1000
If R = 0
AV
1000
100
10
t
= (L)(I )/(1.3*RATED BV
− V
)
DD
AS
DSS
0
If R
AV
0
t
= (L/R)ln[(I *R)/(1.3*RATED BV
− V ) +1]
AS
DSS DD
100
STARTING T = 25oC
100us
J
STARTING TJ = 150 oC
10
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
1ms
DS(on)
1
SINGLE PULSE
T
10ms
100ms
= MAX RATED
o
J
T
C
= 25
C
0.001 0.01
0.1
1
10
100 1000
0.1
tAV, TIME IN AVALANCHE (ms)
0.1
1
10
100 200
NOTE: Refer to ON Semiconductor Application Notes AN7514
and AN7515
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
300
300
PULSE DURATION = 250 ms
DUTY CYCLE = 0.5% MAX
VGS = 0 V
100
250
200
150
100
50
VDD = 5V
10
1
TJ = 175oC
TJ = 25oC
TJ = 25 oC
J = 175oC
TJ = −55 o
C
T
0
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
2
3
4
5
6
7
8
VSD, BODY DIODE FORWARD VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Forward Diode Characteristics
300
250
200
150
100
50
300
250
200
150
100
50
VGS
15V Top
VGS
15V Top
10V
8V
10V
8V
7V
6V
7V
6V
250ms PULSE WIDTH
Tj=25oC
250ms PULSE WIDTH
Tj=175oC
5.5V
5V Bottom
5.5V
5V Bottom
0
0
0
1
2
3
4
5
0
1
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Saturation Characteristics
Figure 10. Saturation Characteristics
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4
NTBS2D7N06M7
TYPICAL PERFORMANCE CHARACTERISTICS
50
40
30
20
10
0
2.4
PULSE DURATION = 250 ms
DUTY CYCLE = 0.5% MAX
ID = 80A
PULSE DURATION = 250 ms
DUTY CYCLE = 0.5% MAX
2.0
1.6
1.2
0.8
0.4
TJ = 25oC
T
J = 175oC
I
D = 80A
VGS = 10V
−80 −40
0
40
80 120 160 200
4
5
6
7
8
9
10
TJ, JUNCTION TEMPERATURE(oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 11. RDS(on) vs. Gate Voltage
Figure 12. Normalized RDS(on) vs. Junction Temperature
1.5
1.2
0.9
0.6
0.3
0.0
1.10
VGS = VDS
ID = 5mA
I
D
= 250mA
1.05
1.00
0.95
0.90
−80 −40
0
40
80 120 160 200
TJ, JUNCTION TEMPERATURE(oC)
−80 −40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
Figure 13. Normalized Gate Threshold Voltage vs.
Temperature
Figure 14. Normalized Drain−to−Source Breakdown
Voltage vs. Junction Temperature
10000
10
ID = 80A
Ciss
VDD = 30V
8
VDD = 36V
VDD =24V
1000
Coss
6
4
2
0
100
Crss
f = 1MHz
VGS = 0V
10
0.1
0
15
30
45
60
75
90
1
10
DS, DRAIN TO SOURCE VOLTAGE (V)
100
Qg, GATE CHARGE(nC)
V
Figure 15. Capacitance vs. Drain−to−Source Voltage
Figure 16. Gate Charge vs. Gate−to−Source Voltage
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
DATE 11 MAR 2021
SCALE 1:1
XXXXXX = Specific Device Code
A
= Assembly Location
WL
Y
= Wafer Lot
= Year
GENERIC MARKING DIAGRAMS*
WW
W
M
G
AKA
= Work Week
= Week Code (SSG)
= Month Code (SSG)
= Pb−Free Package
= Polarity Indicator
XX
AYWW
XXXXXXXXG
AKA
XXXXXXXXG
AYWW
XXXXXX
XXYMW
XXXXXXXXX
AWLYWWG
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
IC
Standard
Rectifier
SSG
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON56370E
D2PAK−3 (TO−263, 3−LEAD)
PAGE 1 OF 1
DESCRIPTION:
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2018
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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