NTBV45N06LT4G [ONSEMI]
Single N-Channel Logic Level Power MOSFET 60V, 45A, 28 mΩ;
| 型号： | NTBV45N06LT4G |
| 厂家： | 
ONSEMI |
| 描述： | Single N-Channel Logic Level Power MOSFET 60V, 45A, 28 mΩ |
| 文件： | 总9页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTB45N06L, NTBV45N06L
MOSFET – Power,
N-Channel, Logic Level,
D2PAK
45 A, 60 V, 28 mW
http://onsemi.com
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
45 AMPERES, 60 VOLTS
RDS(on) = 28 mW
Features
• Higher Current Rating
N−Channel
D
• Lower R
DS(on)
• Lower V
DS(on)
• Lower Capacitances
G
• Lower Total Gate Charge
• Tighter V Specification
SD
S
• Lower Diode Reverse Recovery Time
• Lower Reverse Recovery Stored Charge
• AEC−Q101 Qualified and PPAP Capable − NTBV45N06L
• These Devices are Pb−Free and are RoHS Compliant
4
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
1
2
3
2
D PAK
CASE 418B
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT1
4
Drain
NTx
45N06LG
AYWW
1
2
3
Gate Drain Source
NTx45N06L = Device Code
x
= B or P
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2019 − Rev. 1
NTB45N06L/D
NTB45N06L, NTBV45N06L
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
60
Unit
Vdc
Vdc
Vdc
Drain−to−Source Voltage
V
DSS
DGR
Drain−to−Gate Voltage (R = 10 MW)
V
60
GS
Gate−to−Source Voltage
− Continuous
V
V
"15
"20
GS
GS
− Non−Repetitive (t v10 ms)
p
Drain Current
− Continuous @ T = 25°C
I
I
45
30
150
Adc
Apk
A
D
D
− Continuous @ T = 100°C
A
− Single Pulse (t v10 ms)
I
p
DM
Total Power Dissipation @ T = 25°C
Derate above 25°C
P
D
125
0.83
3.2
W
W/°C
W
A
Total Power Dissipation @ T = 25°C (Note 1)
A
Total Power Dissipation @ T = 25°C (Note 2)
2.4
W
A
Operating and Storage Temperature Range
T , T
−55 to +175
°C
J
stg
Single Pulse Drain−to−Source Avalanche Energy − Starting T = 25°C
E
AS
240
mJ
J
(V = 50 Vdc, V = 5.0 Vdc, L = 0.3 mH
DD
GS
I
= 40 A, V = 60 Vdc, R = 25 W)
L(pk)
DS G
Thermal Resistance
°C/W
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
R
R
R
1.2
46.8
63.2
q
JC
JA
JA
q
q
Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds
T
L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2
1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in ).
2
2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in ).
ORDERING INFORMATION
†
Device
Package
Shipping
2
NTB45N06LG
D PAK
50 Units / Rail
(Pb−Free)
2
NTB45N06LT4G
NTBV45N06LT4G
D PAK
800 / Tape & Reel
800 / Tape & Reel
(Pb−Free)
2
D PAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
2
NTB45N06L, NTBV45N06L
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(V = 0 Vdc, I = 250 mAdc)
V
Vdc
(BR)DSS
60
−
67
67.2
−
−
GS
D
Temperature Coefficient (Positive)
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
DSS
(V = 60 Vdc, V = 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V = 60 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V
=
15 Vdc, V = 0 Vdc)
I
−
−
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage (Note 4)
V
GS(th)
(V = V , I = 250 mAdc)
Threshold Temperature Coefficient (Negative)
1.0
−
1.8
4.7
2.0
−
DS
GS
D
mV/°C
mW
Static Drain−to−Source On−Resistance (Note 4)
R
V
DS(on)
(V = 5.0 Vdc, I = 22.5 Adc)
−
23
28
GS
D
Static Drain−to−Source On−Voltage (Note 4)
(V = 5.0 Vdc, I = 45 Adc)
Vdc
DS(on)
−
−
1.03
0.93
1.51
−
GS
D
(V = 5.0 Vdc, I = 22.5 Adc, T = 150°C)
GS
D
J
Forward Transconductance (Note 4) (V = 8.0 Vdc, I = 12 Adc)
g
FS
−
22.8
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
1212
352
90
1700
480
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
Transfer Capacitance
C
oss
f = 1.0 MHz)
C
180
rss
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
−
−
−
−
−
−
−
13
341
36
30
680
75
320
32
−
ns
d(on)
Rise Time
t
r
(V = 30 Vdc, I = 45 Adc,
DD
D
V
GS
= 5.0 Vdc, R = 9.1 W) (Note 4)
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
158
23
Gate Charge
Q
T
Q
1
Q
2
nC
(V = 48 Vdc, I = 45 Adc,
DS
D
4.6
14.1
V
GS
= 5.0 Vdc) (Note 4)
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I = 45 Adc, V = 0 Vdc) (Note 4)
V
SD
−
−
1.01
0.92
1.15
−
Vdc
ns
S
GS
(I = 45 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
Reverse Recovery Time
t
rr
−
−
−
−
56
30
−
−
−
−
(I = 45 Adc, V = 0 Vdc,
S
GS
t
a
dI /dt = 100 A/ms) (Note 4)
S
t
b
26
Reverse Recovery Stored Charge
Q
0.09
mC
RR
2
3. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in ).
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
3
NTB45N06L, NTBV45N06L
80
70
60
50
40
30
20
10
0
80
V
= 5.5 V
GS
V
GS
= 10 V
V
> = 10 V
DS
70
60
50
40
30
20
10
0
V
GS
= 5 V
V
= 6 V
GS
V
= 4.5 V
GS
V
= 7 V
GS
V
GS
= 4 V
T = 25°C
J
V
= 8 V
GS
V
= 3.5 V
GS
T = 100°C
J
V
GS
= 9 V
T = −55°C
J
0
1
2
3
4
1.8
2.6
3.4
4.2
5
5.8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.046
0.042
0.038
0.034
0.03
0.046
0.042
0.038
0.034
0.03
V
GS
= 5 V
T = 100°C
J
T = 25°C
J
V
GS
= 5 V
0.026
0.022
0.018
0.014
0.026
0.022
0.018
T = −55°C
J
V
GS
= 10 V
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
10000
1000
100
2
I
V
= 22.5 A
V
GS
= 0 V
D
= 5 V
GS
1.8
T = 150°C
J
1.6
1.4
1.2
1
T = 125°C
J
T = 100°C
J
0.8
10
0.6
−50 −25
0
25
50
75 100 125 150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
http://onsemi.com
4
NTB45N06L, NTBV45N06L
6
4000
3600
3200
V
= 0 V
V
= 0 V
T = 25°C
DS
GS
J
C
C
Q
Q
iss
T
5
V
GS
Q
1
2
2800
2400
rss
4
3
2
1
0
2000
1600
1200
800
400
0
C
iss
C
oss
I
D
= 45 A
C
T = 25°C
J
rss
V
GS
V
DS
10
5
0
5
10
15
20
25
0
4
8
12
16
20
24
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
Q , TOTAL GATE CHARGE (nC)
g
(VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
48
40
32
24
16
V
= 30 V
= 45 A
= 5 V
DS
V
GS
= 0 V
I
D
T = 25°C
J
V
GS
t
t
r
f
100
t
d(off)
8
0
t
d(on)
10
1
10
R , GATE RESISTANCE (W)
100
0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96
1
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
280
240
V
= 15 V
GS
I
D
= 45 A
SINGLE PULSE
= 25°C
T
C
100
10
1
200
160
120
80
dc
10 ms
1 ms
100 ms
R
Limit
Thermal Limit
Package Limit
DS(on)
40
0.1
0.10
0
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
5
NTB45N06L, NTBV45N06L
1
Normalized to R
at Steady State
q
JC
0.1
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t, TIME (s)
Figure 13. Thermal Response
10
Normalized to R
1″ square Cu Pad, Cu Area 1.127 in ,
at Steady State,
q
JA
2
3 x 3 inch FR4 board
1
0.1
0.01
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, TIME (s)
Figure 14. Thermal Response
http://onsemi.com
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
C
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
E
V
W
−B−
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
MAX
A
B
C
D
E
F
G
H
J
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
4.83
0.89
1.40
8.89
A
S
1
2
3
2.54 BSC
0.080
0.018 0.025
0.090 0.110
0.110
2.03
0.46
2.29
1.32
7.11
5.00 REF
2.00 REF
0.99 REF
2.79
0.64
2.79
1.83
8.13
−T−
SEATING
PLANE
K
W
J
K
L
G
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625 14.60 15.88
0.045 0.055
M
N
P
R
S
V
H
D 3 PL
M
M
T B
0.13 (0.005)
1.14
1.40
VARIABLE
CONFIGURATION
ZONE
N
P
R
U
L
L
L
M
M
M
F
F
F
VIEW W−W
VIEW W−W
VIEW W−W
1
2
3
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
STYLE 5:
PIN 1. CATHODE
2. ANODE
STYLE 6:
PIN 1. NO CONNECT
2. CATHODE
PIN 1. BASE
PIN 1. GATE
PIN 1. ANODE
2. CATHODE
3. ANODE
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. DRAIN
3. SOURCE
4. DRAIN
2. COLLECTOR
3. EMITTER
4. COLLECTOR
3. CATHODE
4. ANODE
3. ANODE
4. CATHODE
4. CATHODE
MARKING INFORMATION AND FOOTPRINT ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
AYWW
xxxxxxxxG
AKA
xxxxxxxxG
AYWW
IC
Standard
Rectifier
xx
A
WL
Y
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
WW
G
AKA
= Work Week
= Pb−Free Package
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
10.49
8.38
16.155
3.25X04
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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