NLAS3699BMN1R2G [ONSEMI]

Dual DPDT Ultra−Low RON Switch; 双DPDT超低RON开关
NLAS3699BMN1R2G
型号: NLAS3699BMN1R2G
厂家: ONSEMI    ONSEMI
描述:

Dual DPDT Ultra−Low RON Switch
双DPDT超低RON开关

开关 光电二极管
文件: 总10页 (文件大小:98K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
NLAS3699B  
Dual DPDT Ultra−Low RON  
Switch  
The NLAS3699B is a dual independent ultra−low R  
DPDT  
ON  
analog switch. This device is designed for low operating voltage, high  
current switching of speaker output for cell phone applications. It can  
switch a balanced stereo output. The NLAS3699B can handle a  
balanced microphone/speaker/ring−tone generator in a monophone  
mode. The device contains a break−before−make feature.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
16  
Single Supply Operation  
1
QFN−16  
CASE 485AE  
1.65 to 4.5 V V  
CC  
NLAB  
3699  
ALYWG  
G
Function Directly from LiON Battery  
1
Maximum Breakdown Voltage: 5.5 V  
Tiny 3 x 3 mm QFN Pb−Free Package  
Meet JEDEC MO−220 Specifications  
Low Static Power  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
This is a Pb−Free Device*  
= Work Week  
= Pb−Free Package  
(Note: Microdot may be in either location)  
Typical Applications  
Cell Phone Speaker/Microphone Switching  
Ringtone−Chip/Amplifier Switching  
Four Unbalanced (Single−Ended) Switches  
Stereo Balanced (Push−Pull) Switching  
D1 1S1 Vcc 4S2  
16  
15  
14  
13  
Important Information  
1
2
3
4
12  
11  
10  
9
1S2  
1−2IN  
2S1  
D4  
ESD Protection:  
4S1  
3−4IN  
3S2  
HBM (Human Body Model) > 8000 V  
MM (Machine Model) > 400 V  
Continuous Current Rating Through each Switch 300 mA  
Conforms to: JEDEC MO−220, Issue H, Variation VEED−6  
Pin for Pin Compatible with STG3699  
D2  
5
6
7
8
2S2 GND 3S1 D3  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
March, 2006 − Rev. 0  
NLAS3699B/D  
NLAS3699B  
D
S2  
S1  
IN  
Figure 1. Input Equivalent Circuit  
PIN DESCRIPTION  
QFN PIN #  
Symbol  
Name and Function  
1, 3, 5, 7, 9, 11, 13, 15  
1S1 to 4S1, 1S2 to 4S2  
1−2IN, 3−4IN  
D1 to D4  
Independent Channels  
Controls  
2, 10  
4, 8, 12, 16  
Common Channels  
Ground (V)  
6
GND  
14  
V
Positive Supply Voltage  
CC  
TRUTH TABLE  
IN  
H
L
S1  
S2  
ON  
OFF(*)  
ON  
OFF(*)  
*High impedance.  
http://onsemi.com  
2
NLAS3699B  
MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
V
V
V
Positive DC Supply Voltage  
*0.5 to )5.5  
CC  
IS  
Analog Input Voltage (V , V , or V  
)
*0.5 v V v V  
CC  
V
NO  
NC  
COM  
IS  
Digital Select Input Voltage  
*0.5 v V v)5.5  
V
IN  
I
I
I
I
Continuous DC Current from COM to NC/NO  
Peak Current from COM to NC/NO, 10 duty cycle (Note 1)  
Continuous DC Current into COM/NO/NC with respect to V or GND  
$300  
$500  
$100  
mA  
mA  
mA  
ns/V  
anl1  
anl−pk 1  
clmp  
CC  
t , t  
Input Rise or Fall Time, SELECT  
V
V
= 1.6 V − 2.7 V  
= 3.0 V − 4.5 V  
0
0
20  
10  
r
f
CC  
CC  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. Defined as 10% ON, 90% off duty cycle.  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
1.65  
GND  
GND  
*40  
Max  
Unit  
V
V
V
V
T
DC Supply Voltage  
4.5  
CC  
IN  
Digital Select Input Voltage  
V
V
V
CC  
CC  
Analog Input Voltage (NC, NO, COM)  
Operating Temperature Range  
V
IS  
)85  
°C  
ns/V  
A
t , t  
r
Input Rise or Fall Time, SELECT  
V
V
= 1.6 V − 2.7 V  
= 3.0 V − 4.5 V  
0
0
20  
10  
f
CC  
CC  
http://onsemi.com  
3
 
NLAS3699B  
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)  
Guaranteed Limit  
*405C to 255C  
t855C  
Symbol  
Parameter  
Condition  
V
Unit  
CC  
V
Minimum High−Level Input  
Voltage, Select Inputs  
1.8  
2.5  
3.6  
4.3  
1.2  
1.7  
2.2  
2.6  
1.2  
1.7  
2.2  
2.6  
V
IH  
V
Maximum Low−Level Input  
Voltage, Select Inputs  
1.8  
2.5  
3.6  
4.3  
0.4  
0.5  
0.7  
0.9  
0.4  
0.5  
0.7  
0.9  
V
IL  
I
Maximum Input Leakage  
Current, Select Inputs  
V
V
= V or GND  
4.3  
$0.1  
$1.0  
A  
IN  
IN  
CC  
I
I
Power Off Leakage Current  
= V or GND  
0
$0.5  
$1.0  
$2.0  
$2.0  
A  
A  
OFF  
CC  
IN  
CC  
Maximum Quiescent Supply  
Current (Note 2)  
Select and V = V or GND  
1.65 to 4.5  
IS  
CC  
DC ELECTRICAL CHARACTERISTICS − Analog Section  
Guaranteed Maximum Limit  
−405C to 255C  
t855C  
Min  
Max  
Min  
Max  
Symbol  
Parameter  
NC/NO On−Resistance  
Condition  
v V or V w V  
IH  
V
Unit  
CC  
R
ON  
V
V
2.5  
3.0  
4.3  
0.65  
0.6  
0.75  
0.75  
0.70  
IN  
IS  
IL  
IN  
(Note 2)  
= GND to V  
CC  
I
I v 100 mA  
0.55  
IN  
R
NC/NO On−Resistance Flatness  
(Notes 2, 4)  
I
= 100 mA  
2.5  
3.0  
4.3  
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
FLAT  
COM  
V
= 0 to V  
IS  
CC  
R
On−Resistance Match Between Channels  
(Notes 2 and 3)  
V
I
= 1.3 V;  
= 100 mA  
= 1.5 V;  
2.5  
3.0  
4.3  
0.06  
0.05  
0.05  
0.06  
0.05  
0.05  
ON  
IS  
COM  
V
I
IS  
COM  
= 100 mA  
V
= 2.2 V;  
IS  
I
= 100 mA  
COM  
I
I
NC or NO Off Leakage Current (Note 2)  
V
= V or V  
IH  
4.3  
4.3  
−10  
−10  
10  
10  
−100  
−100  
100  
100  
nA  
nA  
NC(OFF)  
NO(OFF)  
IN  
IL  
V
V
or V = 0.3 V  
NC  
NO  
= 4.0 V  
COM  
I
COM ON  
V
= V or V  
IL IH  
COM(ON)  
IN  
Leakage Current  
(Note 2)  
V
V
0.3 V or 4.0 V with  
floating or  
NO  
NC  
V
V
0.3 V or 4.0 V with  
floating  
NC  
NO  
V
= 0.3 V or 4.0 V  
COM  
2. Guaranteed by design. Resistance measurements do not include test circuit or package resistance.  
3. R − R between nS1 or nS2.  
R
ON = ON(MAX)  
ON(MIN)  
4. Flatness is defined as the difference between the maximum and minimum value of on−resistance as measured over the specified analog  
signal ranges.  
http://onsemi.com  
4
 
NLAS3699B  
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)  
r
f
Guaranteed Maximum Limit  
*405C to 255C  
t855C  
V
(V)  
V
IS  
CC  
(V) Min Typ* Max Min Max  
Symbol  
Parameter  
Turn−On Time  
Test Conditions  
R = 50 ꢁ ꢃ C = 35 pF  
Unit  
t
t
t
2.3 − 4.5  
1.5  
50  
30  
60  
40  
ns  
ON  
L
L
(Figures 3 and 4)  
Turn−Off Time  
R = 50 ꢁ ꢃ C = 35 pF  
2.3 − 4.5  
3.0  
1.5  
ns  
ns  
OFF  
BBM  
L
L
(Figures 3 and 4)  
V = 3.0  
IS  
Minimum Break−Before−Make Time  
1.5  
2
15  
R = 50 ꢁ ꢃ C = 35 pF  
L
L
(Figure 2)  
Typical @ 25, V = 4.5 V  
CC  
C
IN  
C
SN  
C
D
Control Pin Input Capacitance  
SN Port Capacitance  
7.0  
72  
pF  
pF  
pF  
D Port Capacitance When Switch is Enabled  
230  
*Typical Characteristics are at 25°C.  
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)  
255C  
V
(V)  
CC  
Typical  
Symbol  
Parameter  
Condition  
centered between V and GND  
Unit  
BW  
Maximum On−Channel −3dB  
V
1.65 − 4.5  
20  
MHz  
IN  
CC  
Bandwidth or Minimum Frequency (Figure 5)  
Response (Figure 12)  
V
V
Maximum Feed−through On Loss  
V
V
= 0 dBm @ 100 kHz to 50 MHz  
1.65 − 4.5  
1.65 − 4.5  
1.65 − 4.5  
4.5  
−0.06  
−62  
50  
dB  
dB  
pC  
%
ONL  
ISO  
IN  
IN  
centered between V and GND (Figure 5)  
CC  
Off−Channel Isolation (Figure 13)  
f = 100 kHz; V = 1 V RMS; C = 5 pF  
IS  
L
V
centered between V and GND(Figure 5)  
CC  
IN  
Q
Charge Injection Select Input to  
Common I/O (Figure 8)  
V
V
GND, R = 0 , C = 1 nF  
IN = CC to  
IS  
L
Q = C x V  
(Figure 6)  
OUT  
L
THD  
VCT  
Total Harmonic Distortion THD +  
Noise (Figure 7)  
F
= 20 Hz to 20 kHz, R = R  
= 600 , C = 50 pF  
0.01  
−62  
IS  
L
gen  
L
V
= 2 V  
PP  
IS  
Channel−to−Channel Crosstalk  
f = 100 kHz; V = 1 V RMS, C = 5 pF, R = 50 ꢁ  
1.65 − 4.5  
dB  
IS  
L
L
V
centered between V and GND (Figure 5)  
CC  
IN  
5. Off−Channel Isolation = 20log10 (Vcom/Vno), Vcom = output, Vno = input to off switch.  
http://onsemi.com  
5
NLAS3699B  
V
CC  
DUT  
Input  
GND  
V
Output  
CC  
V
OUT  
0.1 F  
t
BMM  
50 ꢁ  
35 pF  
90%  
90% of V  
OH  
Output  
Switch Select Pin  
GND  
Figure 2. tBBM (Time Break−Before−Make)  
V
CC  
Input  
50%  
50%  
90%  
DUT  
0 V  
V
Output  
CC  
V
OUT  
V
0.1 F  
OH  
Open  
90%  
50 ꢁ  
35 pF  
Output  
V
OL  
Input  
t
t
OFF  
ON  
Figure 3. tON/tOFF  
V
V
CC  
CC  
Input  
50%  
50%  
DUT  
0 V  
50 ꢁ  
Output  
V
OUT  
V
OH  
Open  
35 pF  
Output  
V
10%  
10%  
OL  
Input  
t
t
ON  
OFF  
Figure 4. tON/tOFF  
http://onsemi.com  
6
NLAS3699B  
50 ꢁ  
DUT  
Reference  
Input  
50 Generator  
Transmitted  
Output  
50 ꢁ  
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is  
the bandwidth of an On switch. V , Bandwidth and V are independent of the input signal direction.  
ISO  
ONL  
V
OUT  
= Off Channel Isolation = 20 Log ǒ Ǔ  
V
V
for V at 100 kHz  
IN  
ISO  
V
IN  
OUT  
V
= On Channel Loss = 20 Log ǒ Ǔ  
for V at 100 kHz to 50 MHz  
ONL  
IN  
V
IN  
Bandwidth (BW) = the frequency 3 dB below V  
ONL  
V
= Use V  
setup and test to all other switch analog input/outputs terminated with 50 ꢁ  
ISO  
CT  
Figure 5. Off Channel Isolation/On Channel Loss (BW)/Crosstalk  
(On Channel to Off Channel)/VONL  
DUT  
V
CC  
V
Open  
Output  
IN  
GND  
C
L
Output  
Off  
V  
OUT  
Off  
On  
V
IN  
Figure 6. Charge Injection: (Q)  
1
5
0
3.0 V  
2.5 V  
−5  
1.65 V  
0.1  
0.01  
−10  
−15  
−20  
−25  
−30  
3.6 V  
0.001  
10  
100  
1000  
FREQUENCY (Hz)  
10000  
100000  
0
0.5  
1
1.5  
2
2.5  
(V)  
3
3.5  
4
4.5  
5
V
IN  
Figure 7. Total Harmonic Distortion Plus Noise  
Versus Frequency  
Figure 8. Charge Injection versus Vis  
http://onsemi.com  
7
NLAS3699B  
2
1.6  
1.2  
0.8  
0.4  
0
1.2  
1.8 V  
85°C  
0.8  
0.4  
0
25°C  
2.5 V  
−40°C  
3.6 V  
3.0 V  
0.0  
0.5  
1.0  
1.5  
(V)  
2.0  
2.5  
3.0  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
V
V
(V)  
IN  
COM  
Figure 10. RON vs. VIN vs. Temperature  
@ VCC = 3.0 V  
Figure 9. On−Resistance vs. COM Voltage  
0
0.8  
0.7  
0.6  
0.5  
0.4  
−2  
−4  
85°C  
25°C  
−6  
−8  
−10  
−12  
−14  
−16  
−18  
−20  
−40°C  
0.3  
0.2  
0.1  
0.0  
0.0  
0.5  
1.0  
1.5  
2.0  
(V)  
2.5  
3.0  
3.5  
4.0  
0.1  
1
10  
100  
1000  
V
FREQUENCY (MHz)  
IN  
Figure 11. RON vs. VIN vs. Temperature  
@ VCC = 3.6 V  
Figure 12. Bandwidth vs. Frequency  
@ VCC = 1.65 V to 3.6 V  
40  
30  
0
−10  
20  
−20  
−30  
−40  
−50  
−60  
−70  
10  
0
−10  
−20  
−30  
−40  
−50  
0.1  
1
10  
100  
1000  
0.1  
1
10  
100  
1000  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Figure 13. Off−Isolation vs. Frequency  
@ VCC = 1.65 V to 3.6 V  
Figure 14. Phase Angle vs. Frequency  
@ VCC = 1.65 V to 3.6 V  
http://onsemi.com  
8
NLAS3699B  
DEVICE ORDERING INFORMATION  
Device Nomenclature  
Circuit  
Indicator  
Device  
Function  
Package Tape & Reel  
Device Order  
Number  
Suffix  
Suffix  
Technology  
Package Type  
Tape & Reel Size  
NLAS3699BMN1R2G  
NL  
AS  
3699B  
MN1  
R2G  
QFN  
(Pb−Free)  
3000 Unit / Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
http://onsemi.com  
9
NLAS3699B  
PACKAGE DIMENSIONS  
QFN−16 (3 x 3 x 0.85 mm)  
CASE 485AE−01  
ISSUE O  
D
A
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M, 1994.  
B
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION b APPLIES TO PLATED  
TERMINAL AND IS MEASURED BETWEEN  
0.25 AND 0.30 MM FROM TERMINAL.  
4. COPLANARITY APPLIES TO THE EXPOSED  
PAD AS WELL AS THE TERMINALS.  
5. OUTLINE MEETS JEDEC DIMENSIONS PER  
MO−220, VARIATION VEED−6.  
PIN 1  
LOCATION  
E
MILLIMETERS  
DIM MIN  
0.800 0.900 1.000  
A1 0.000 0.025 0.050  
NOM  
MAX  
A
0.15  
C
TOP VIEW  
A3  
b
D
0.200 REF  
0.180 0.250 0.300  
3.00 BSC  
0.15  
C
D2 1.250  
E
1.40 1.550  
3.00 BSC  
(A3)  
E2 1.250  
e
1.40 1.550  
0.500 BSC  
0.10  
0.08  
C
C
K
L
0.200  
−−−  
−−−  
A
0.300 0.400 0.500  
SEATING  
PLANE  
16 X  
SIDE VIEW  
A1  
C
D2  
e
16X  
L
EXPOSED PAD  
5
8
NOTE 5  
4
9
E2  
K
16X  
12  
1
16  
13  
16X b  
0.10  
0.05  
C
C
A
B
BOTTOM VIEW  
NOTE 3  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
ON Semiconductor Website: http://onsemi.com  
Order Literature: http://www.onsemi.com/litorder  
Literature Distribution Center for ON Semiconductor  
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA  
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada  
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
Japan: ON Semiconductor, Japan Customer Focus Center  
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051  
Phone: 81−3−5773−3850  
For additional information, please contact your  
local Sales Representative.  
NLAS3699B/D  

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