NFAP1060L3TT [ONSEMI]
Intelligent Power Module (IPM), 600 V 10 A with advanced SIP package;
| 型号： | NFAP1060L3TT |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module (IPM), 600 V 10 A with advanced SIP package 局域网 电动机控制 |
| 文件： | 总14页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intelligent Power Module (IPM)
600 V, 10 A
NFAP1060L3TT
The NFAP1060L3TT is a fully−integrated inverter power stage
consisting of a high−voltage driver, six IGBT’s and a thermistor,
suitable for driving permanent magnet synchronous (PMSM) motors,
brushless−DC (BLDC) motors and AC asynchronous motors. The
IGBT’s are configured in a 3−phase bridge with separate emitter
connections for the lower legs for maximum flexibility in the choice of
control algorithm. The power stage has a full range of protection
functions including cross−conduction protection, external shutdown
and under−voltage lockout functions. An internal comparator and
reference connected to the over−current protection circuit allows the
designer to set the over−current protection level.
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Features
• Three−phase 10 A/600 V IGBT Module with Integrated Drivers
• Compact 44 mm x 20.9 mm Single In−line Package
• Built−in Under Voltage Protection
SIP29
CASE 127FB
• Cross−conduction Protection
• ITRIP Input to Shut Down All IGBTs
• Integrated Bootstrap Diodes and Resistors
• Thermistor for Substrate Temperature Measurement
• UL1557 Certification (File number: E339285)
MARKING DIAGRAM
NFAP1060L3TT
ZZZATYWW
Typical Applications
• Industrial Drives
• Industrial Pumps
• Industrial Fans
• Industrial Automation
NFAP1060L3TT = Specific Device Code
ZZZ
A
T
= Assembly Lot Code
= Assembly Location
= Test Location
= Year
Y
WW
= Work Week
HIN(U)
LIN(U)
HIN(V)
LIN(V)
HIN(W)
LIN(W)
HS1
LS1
HS2
LS2
HS3
LS3
Device marking is on package top side
HS1
LS1
HS2
LS2
HS3
LS3
Three channel
half−bridge
driver
with
protection
circuits
ORDERING INFORMATION
Device
Package
Shipping
NFAP1060L3TT
SIP29
120 / Box
(Pb−Free)
Figure 1. Functional Diagram
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
March, 2020 − Rev. 1
NFAP1060L3TT/D
NFAP1060L3TT
NFAP1060L3TT
VPN
P:13
RC filtering for
HINx and LINx
not shown.
+
C1
CS
Recommended
HV Ground
From Op−amp
circuit
in noisy
RSU
environments.
NU:17
NV:19
NW:21
ITRIP:16
From HV
Power
Source
RSV
HIN(U):20
HIN(V):22
HIN(W):23
LIN(U):24
LIN(V):25
LIN(W):26
RSW
To Op−amp
circuit
VB(U):9
+
+
Pull−up
VS(U), U:10
VB(V):5
RP
RTH
Controller
FLTEN:18
TH:27
Motor
VS(V), V:6
VB(W):1
VDD=15V
from
external
regulator
VDD:28
VSS:29
CD4
+
+
VS(W), W:2
LV Ground
Star connection to HV Ground
Figure 2. Application Schematic
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2
NFAP1060L3TT
Bootstrap
Bootstrap
Bootstrap
VB(U) (9)
VB(V) (5)
VB(W) (1)
P (13)
VDD (28)
VSS (29)
TH (27)
VS(W), W (2)
VS(V), V (6)
VS(U), U (10)
NU (17)
NV (19)
NW (21)
Level
Shifter
Level
Shifter
Level
Shifter
HIN(U) (20)
HIN(V) (22)
HIN(W) (23)
LIN(U) (24)
LIN(V) (25)
LIN(W) (26)
Logic
Logic
Logic
VDD
VDD
undervoltage
shutdown
FLTEN (18)
ITRIP (16)
Over current
protection
Internal Voltage
reference
Figure 3. Simplified Block Diagram
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3
NFAP1060L3TT
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
Name
VB(W)
VS(W), W
VB(V)
VS(V), V
VB(U)
VS(U), U
P
Description
High−Side Bias Voltage for W phase IGBT Driving
High−Side Bias Voltage GND for W phase IGBT Driving, Output for W Phase
High−Side Bias Voltage for V phase IGBT Driving
High−Side Bias Voltage GND for V phase IGBT Driving, Output for V Phase
High−Side Bias Voltage for U phase IGBT Driving
High−Side Bias Voltage GND for U phase IGBT Driving, Output for U Phase
Positive DC−Link Input
2
5
6
9
10
13
16
17
18
19
20
21
22
23
24
25
26
27
28
29
ITRIP
NU
Input for Over Current Protection
Negative DC−Link Input for U Phase
FLTEN
NV
Fault Output, Enable Input
Negative DC−Link Input for V Phase
HIN(U)
NW
Signal Input for High−Side U Phase
Negative DC−Link Input for W Phase
HIN(V)
HIN(W)
LIN(U)
LIN(V)
LIN(W)
TH
Signal Input for High−Side V Phase
Signal Input for High−Side W Phase
Signal Input for Low−Side U Phase
Signal Input for Low−Side V Phase
Signal Input for Low−Side W Phase
Series Resister for Thermistor (Temperature Detection)
Low−Side Bias Voltage for IC and IGBTs Driving
Low−Side Common Supply Ground
VDD
VSS
NOTE: Pins 3, 4, 7, 8, 11, 12, 14 and 15 are not present
Table 2. ABSOLUTE MAXIMUM RATINGS at Tc = 25°C (Note 1)
Parameter
Symbol
VPN
Vces
Ic
Conditions
P−NU,NV,NW, VPN (surge) < 500 V (Note 2)
P−U,V,W; U−NU; V−NV; W−NW
P,U,V,W,NU,NV,NW terminal current
Tc = 25°C, Under 1ms Pulse Width
Tc = 25°C, Per One Chip
Rating
Unit
V
Supply Voltage
450
Collector − Emitter Voltage
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
Corrector Dissipation
600
V
10
20
A
Icp
A
Pc
19
W
V
High−Side Control Bias voltage
Control Supply Voltage
VBS
VDD
VIN
VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W) (Note 3)
VDD−VSS
−0.3 to +20.0
−0.3 to +20.0
V
Input Signal Voltage
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V), LIN(W)−VSS
FLTEN−VSS
−0.3 to V
−0.3 to V
V
DD
DD
FLTEN Terminal Voltage
Current Sensing Input Voltage
Operating Junction Temperature
Storage Temperature
VFLTEN
VITRIP
Tj
V
ITRIP−VSS
−0.3 to +7.0
150
V
°C
°C
°C
Nm
Vrms
Tstg
Tc
−40 to +125
−40 to +125
0.9
Module Case Operation Temperature
Tightening Torque
MT
Case mounting screws
Isolation Voltage
Viso
50 Hz sine wave AC 1 minute (Note 4)
2000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal.
3. VBS = VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W)
4. Test conditions: AC2500V, 1 s
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4
NFAP1060L3TT
Table 3. RECOMMENDED OPERATING RANGES
Parameter
Supply voltage
Symbol
VPN
Conditions
Min
0
Typ
280
15
Max
450
Unit
V
P−NU,NV,NW
High−Side Control Bias voltage
VBS
VB(U)−VS(U), VB(V)−VS(V),
VB(W)−VS(W)
13.0
17.5
V
Control Supply Voltage
ON−state Input Voltage
OFF−state Input Voltage
PWM Frequency
VDD
VIN(ON)
VIN(OFF)
fPWM
VDD−VSS
14.0
3.0
0
15
−
16.5
5.0
0.3
20
−
V
V
HIN(U), HIN(V), HIN(W), LIN(U),
LIN(V), LIN(W)−VSS
−
V
1
−
kHz
ms
ms
Nm
Dead Time
DT
Turn−off to Turn−on (external)
ON and OFF
0.5
1
−
Allowable Input Pulse Width
Tightening Torque
PWIN
−
−
‘M3’ type screw
0.6
−
0.9
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. ELECTRICAL CHARACTERISTICS at Tc = 25°C, V
(VBS, VDD) = 15 V unless otherwise noted.
BIAS
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
POWER OUTPUT SECTION
Collector−Emitter Leakage Current
Bootstrap Diode Reverse Current
Collector−Emitter Saturation Voltage
Vce = 600 V
Ices
−
−
−
−
−
1
1
mA
mA
V
VR(DB) = 600 V
IR(DB)
VCE(sat)
VDD = VBS = 15 V, IN = 5 V, Ic = 10 A,
Tj = 25°C
2.1
2.7
VDD = VBS = 15 V, IN = 5 V, Ic = 5 A,
Tj = 100°C
−
1.8
−
V
FWDi Forward Voltage
IN = 0 V, Ic = −10 A, Tj = 25°C
IN = 0 V, Ic = −5 A, Tj = 100°C
Inverter IGBT Part (per 1/6 Module)
Inverter FRD Part (per 1/6 Module)
VF
−
−
−
−
2.2
1.7
−
2.8
−
V
V
Junction to Case Thermal Resistance
Rth(j−c)Q
Rth(j−c)F
6.3
11.6
°C/W
°C/W
−
DRIVER SECTION
Quiescent VBS Supply Current
Quiescent VDD Supply Current
ON Threshold voltage
OFF Threshold voltage
Logic 1 Input Current
VBS = 15 V, HIN = 0 V, per driver
IQBS
IQDDL
VIN(ON)
VIN(OFF)
IIN+
−
−
0.07
0.85
−
0.4
3.0
2.5
−
mA
mA
V
VDD = 15 V, HIN = 0 V, VDD−VSS
HIN(U), HIN(V), HIN(W), LIN(U),
LIN(V), LIN(W)−VSS
−
0.8
−
−
V
VIN = +3.3 V
660
−
−
mA
mA
mA
ms
V
Logic 0 Input Current
VIN = 0 V
IIN−
−
2
FLTEN Terminal Sink Current
Fault−Output Pulse Width
Enable Threshold
FAULT: ON / VFLTEN = 0.1 V
FLTEN−VSS
IoSD
−
2
−
tFOD
20
−
−
FLTEN−VSS
VEN+
−
−
2.5
−
VEN−
0.8
0.44
10.3
10.1
10.3
10.1
−
V
Short Circuit Trip Level
ITRIP−VSS
VSC(ref)
UVBSR
UVBSD
UVDDR
UVDDD
0.49
11.1
10.9
11.1
10.9
0.54
11.9
11.7
11.7
11.5
V
High−Side Control Bias Voltage Under−
Voltage Protection
Reset Level
V
Detection Level
Reset Level
V
Supply Voltage Under−Voltage Protection
V
Detection Level
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
NFAP1060L3TT
Table 5. ELECTRICAL CHARACTERISTICS
at Tc = 25°C, V
(VBS, VDD) = 15 V, VCC = 300 V, L = 3.0 mH unless otherwise noted.
BIAS
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
SWITCHING CHARACTER
Switching Time
IC = 10 A, Tj = 25°C
t
−
−
−
−
−
−
−
−
−
−
0.5
0.5
1.0
1.0
−
ms
ms
mJ
mJ
mJ
mJ
mJ
mJ
mJ
ns
ON
t
OFF
Turn−on Switching Loss
IC = 5 A, Tj = 25°C
IC = 5 A, Tj = 100°C
IC = 5 A, Tj = 100°C
E
114
ON
Turn−off Switching Loss
E
OFF
E
TOT
65
−
Total Switching Loss
179
136
75
−
Turn−on Switching Loss
E
−
ON
OFF
TOT
REC
Turn−off Switching Loss
E
E
−
Total Switching Loss
211
−
Diode Reverse Recovery Energy
Diode Reverse Recovery Time
Reverse Bias Safe Operating Area
Short Circuit Safe Operating Area
E
27
−
t
174
Full Square
−
−
RR
IC = 20 A, V = 450 V
RBSOA
SCSOA
CE
V
CE
= 400 V, Tj = 100°C
5
−
ms
TYPICAL CHARACTERISTICS INV SECTION
Figure 4. VCE vs. IC for Different Temperatures
(VDD = 15 V)
Figure 5. VF vs. IF for Different Temperatures
Figure 6. EON vs. IC for Different Temperatures
Figure 7. EOFF vs. IC for Different Temperatures
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6
NFAP1060L3TT
TYPICAL CHARACTERISTICS INV SECTION
Figure 8. Thermal Impedance Plot
Figure 10. Turn−off Waveform
Tj = 100°C, VCC = 300 V
Figure 9. Turn−on Waveform
Tj = 100°C, VCC = 300 V
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7
NFAP1060L3TT
APPLICATIONS INFORMATION
VBS undervoltage protection reset signal
HIN
LIN
(Note 6)
VDD undervoltage protection reset voltage
VDD
VBS undervoltage protection reset voltage
(Note 7)
Voltage w0.54V
(Note 8)
VB(U), VB(V), VB(W)
Voltage < 0.44V
ITRIP
FLTEN driven
output
FLTEN driven
input
Cross−conduction prevention period
(Note 5)
Upper IGBT
Gate Drive
Lower IGBT
Gate Drive
Automatic reset after protection (Fault−Output PulseWidth)
Figure 11. Input / Output Timing Chart
5. This section of the timing diagram shows the effect of cross−conduction prevention.
6. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low, switching
off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume.
7. This section shows that when the bootstrap voltage on VB(U) (VB(V), VB(W)) drops, the corresponding high side output U (V, W) is switched
off. When the voltage on VB(U) (VB(V), VB(W)) rises sufficiently, normal operation will resume.
8. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes later after
the over−current condition is removed.
Table 6. INPUT / OUTPUT LOGIC TABLE
INPUT
OUTPUT
Low side IGBT
HIN
H
LIN
L
ITRIP
High side IGBT
U,V,W
P
FAULT
OFF
OFF
OFF
OFF
ON
L
L
L
L
H
ON
OFF
ON
L
H
OFF
OFF
OFF
OFF
NU, NV, NW
High Impedance
High Impedance
High Impedance
L
L
OFF
OFF
OFF
H
H
X
X
Table 7. THERMISTOR CHARACTERISTICS
Parameter
Resistance
Symbol
Condition
Tth=25℃
Tth=125℃
Min
45.59
1.34
3953
−40
Typ
47
Max
Unit
kW
kW
K
R
48.41
1.59
25
R
1.45
4021
125
B−Constant (25 to 50℃)
B
4033
+125
Temperature Range
°C
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8
NFAP1060L3TT
Figure 12. Thermistor Resistance vs. Thermistor Temperature
Figure 13. Thermistor Voltage vs. Thermistor Temperature
Conditions: RTH = 4.7 kW, pull−up voltage 5.0 V (see Figure 12)
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9
NFAP1060L3TT
FLTEN Pin
Minimum Input Pulse Width
The FLTEN pin is connected to an open−drain FAULT
output and an ENABLE input, it is required a pull−up
resistor. If the pull−up voltage is 5 V, use a pull−up resistor
with a value of 6.8 kW or higher. If the pull−up voltage is
15 V, use a pull−up resistor with a value of 20 kW or higher.
The pulled up voltage in normal operation for the FLTEN
pin should be above 2.5 V, noting that it is connected to an
internal ENABLE input. The FAULT output is triggered if
there is a VDD under−voltage or an overcurrent condition.
Driving the FLTEN terminal pin is used to enable or shut
down the built−in driver. If the voltage on the FLTEN pin
rises above the positive going ENABLE threshold, the
output drivers are enabled. If the voltage on the FLTEN pin
falls below the negative going ENABLE threshold, the
drivers are disabled.
When input pulse width is less than 1 ms, an output may
not react to the pulse. (Both ON signal and OFF signal)
Calculation of Bootstrap Capacitor Value
The bootstrap capacitor value CB is calculated using the
following approach. The following parameters influence the
choice of bootstrap capacitor:
• VBS: Bootstrap power supply.
15 V is recommended.
• QG: Total gate charge of IGBT at VBS = 15 V.
17 nC
• UVLO: Falling threshold for UVLO.
Specified as 12 V.
• IDMAX: High−side drive power dissipation.
• Specified as 0.4 mA
Under−voltage Protection
• TONMAX: Maximum ON pulse width of high side
If VDD goes below the VDD supply under−voltage
lockout falling threshold, the FAULT output is switched on.
The FAULT output stays on until VDD rises above the VDD
supply under−voltage lockout rising threshold. After VDD
has risen above the threshold to enable normal operation, the
driver waits to receive an input signal on the LIN input
before enabling the driver for the HIN signal. The hysteresis
is approximately 200 mV.
IGBT.
Capacitance Calculation Formula:
CB = (QG + IDMAX * TONMAX)/(VBS − UVLO)
The relationship between TONMAX and CB becomes as
follows. CB is recommended to be approximately 3 times
the value calculated above. The recommended value of CB
is in the range of 1 to 47 mF, however, the value needs to be
verified prior to production. When not using the bootstrap
circuit, each high side driver power supply requires an
external independent power supply.
Overcurrent Protection
An over−current condition is detected if the voltage on the
ITRIP pin is larger than the reference voltage. There is a
blanking time of typically 350 ns to improve noise
immunity. After a shutdown propagation delay of typically
0.9 ms, the FAULT output is switched on. The FAULT output
is held on for 20 ms (minimum).
The over−current protection threshold should be set to be
equal or lower to 2 times the module rated current (Io).
An additional fuse is recommended to protect against
system level or abnormal over−current fault conditions.
Capacitors on High Voltage and VDD Supplies
Both the high voltage and VDD supplies require an
electrolytic capacitor and an additional high frequency
capacitor. The recommended value of the high frequency
capacitor is between 100 nF and 10 mF.
Figure 14. Bootstrap Capacitance vs. Tonmax
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10
NFAP1060L3TT
TEST CIRCUITS
Ices, IR(DB)
VBS=15V
9
ICE, IR
U+
13
10
V+
13
6
W+
13
2
U−
10
17
V−
6
W−
A
B
A
10
A
B
2
VBS=15V
5
6
19
21
VCE, VR
U+,V+,W+ : High side phase
U−,V−,W− : Low side phase
VBS=15V
1
2
U(DB)
V(DB)
W(DB)
VDD=15V
28
A
B
9
5
1
29,17,19,21
29
29
29
Figure 15. Test Circuit for ICE
VCE(sat) (Test by pulse)
VBS=15V
VBS=15V
VBS=15V
9
U+
13
10
20
V+
13
6
W+
13
2
U−
10
17
24
V−
6
W−
2
A
10
A
B
C
5
6
19
25
21
26
IC
V
22
23
1
VCE(sat)
2
VDD=15V
5V
28
C
B
29,17,19,21
Figure 16. Test Circuit for VCE(SAT)
VF (Test by pulse)
U+
V+
13
6
W+
13
2
U−
10
17
V−
6
W−
2
A
A
B
13
10
V
VF
IC
19
21
U(DB)
9
V(DB)
5
W(DB)
B
A
B
1
28
28
28
Figure 17. Test Circuit for VF
IQBS, IQDDL
ID
VBS U+
VBS V+
VBS W+
V
DD
A
A
A
B
9
5
6
1
2
28
29
10
VD*
B
Figure 18. Test Circuit for ID
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11
NFAP1060L3TT
SWITCHING TIME (The circuit is a representative
example of the lower side U phase.)
VBS =15V
VBS =15V
VBS =15V
9
10
A
C
U+
13
17
10
17
20
V+
13
19
6
W+
13
21
2
U−
13
17
13
10
24
V−
13
19
13
6
W−
13
21
13
2
5
6
A
B
C
D
E
CS
V
CC
1
2
D
B
VDD =15V
Input Signal
28
19
22
21
23
E
Io
29,17,19,21
25
26
Figure 19. Test Circuit for Switching Time
Input Signal
(0 to 5V)
90%
lo
10%
tON
tOFF
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP29, 44.0x20.9 FP−1
CASE 127FB
ISSUE A
DATE 14 JUN 2019
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXXXXXXXXXXXXXXX
ZZZATYWW
AT
Y
= Assembly & Test Location
= Year
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON01721H
SIP29, 44.0x20.9 FP−1
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