NFAQ1560R43T [ONSEMI]
Intelligent Power Module (IPM), 600V, 15A;型号: | NFAQ1560R43T |
厂家: | ONSEMI |
描述: | Intelligent Power Module (IPM), 600V, 15A |
文件: | 总15页 (文件大小:590K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Intelligent Power Module (IPM)
600 V, 15 A
NFAQ1560R43T
The NFAQ1560R43T is a fully−integrated inverter power stage
consisting of a high−voltage driver, six IGBTs (FS4 RC IGBT
technology) and a thermistor, suitable for driving permanent magnet
synchronous motors (PMSM), brushless−DC (BLDC) motors and AC
asynchronous motors. The IGBTs are configured in a 3−phase bridge
with separate emitter connections for the lower legs for maximum
flexibility in the choice of control algorithm. The power stage has
a full range of protection functions including cross−conduction
protection, external shutdown and under−voltage lockout functions.
An internal comparator and reference connected to the over−current
protection circuit allows the designer to set the over−current
protection level.
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DIP38 29.6x18.2
CASE 181AE
Features
MARKING DIAGRAM
• Three−phase 15 A/600 V IGBT Module with Integrated Drivers
• Compact 29.6 mm x 18.2 mm Dual In−Line Package
• Built−in Under Voltage Protection
• Cross−conduction Protection
• ITRIP Input to Shut Down All IGBTs
• Integrated Bootstrap Diodes and Resistors
• Thermistor for Substrate Temperature Measurement
• Shut Down Pin
• UL1557 Certification (File Number: E339285)
• This is a Pb−Free Device
NFAQ1560R43T
ZZZATYWW
NFAQ1560R43T = Specific Device Code
Typical Applications
• Industrial Pumps
• Industrial Fans
• Industrial Automation
• Home Appliances
ZZZ
A
T
= Assembly Lot Code
= Assembly Location
= Test Location
= Year
Y
WW
= Work Week
Device marking is on package top side
ORDERING INFORMATION
Shipping
(Qty / Packing)
HIN(U)
LIN(U)
HIN(V)
LIN(V)
HIN(W)
LIN(W)
HS1
LS1
HS2
LS2
HS3
LS3
Device
Package
HS1
LS1
HS2
LS2
HS3
LS3
NFAQ1560R43T
DIP38
(Pb-Free)
400 / Box
Three channel
half−bridge
driver
with
protection
circuits
Figure 1. Function Diagram
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
February, 2021 − Rev. 1
NFAQ1560R43T/D
NFAQ1560R43T
RC filtering for
HINxandLINx
not shown.
Recommended
in noisy
environments.
VPN
P:38
From Op amp
−
+
C1
CS
circuit
ITRIP:10
HV Ground
RSU
( )
HIN U :3
NU:17
NV:18
NW:19
From HV
Power
Source
( ) :4
HIN V
RSV
(
)
HIN W :5
( ):6
LIN U
RSW
( )
V
LIN
:7
(
)
LIN W :8
To Op−amp
circuit
Vctr
from external
regulator
RSD
RP
RTH
:
VB(U) 34
+
+
SD:11
FAULT:9
TH2:14
Controller
VS(U),U:32
:
VB(V) 28
= 15V
from external
regulator
VDD:2
VDD
VS(V),V:26
VB(W):22
Motor
RCLR
CCLR
CFOD:12
TH1:13
+
+
:
VS(W),W:20
VSS 1
LV Ground
Star connection to HV Ground
Figure 2. Application Schematic
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2
NFAQ1560R43T
Bootstrap
Bootstrap
Bootstrap
VB(U) (34)
VB(V) (28)
VB(W) (22)
P (38)
VDD (2)
VSS (1)
Sets latch time.
VS(W),W (20)
VS(V),V (26)
VS(U),U (32)
MΩ
For R=2
,
C=1nF, latch time
is 1.65ms (typical).
CFOD(12)
NU (17)
NV (18)
NW (19)
Level
Shifter
Level
Shifter
Level
Shifter
HIN(U) (3)
HIN(V) (4)
HIN(W) (5)
LIN(U) (6)
LIN(V) (7)
LIN(W) (8)
Logic
Logic
Logic
TH1 (13)
TH2 (14)
VDD
undervoltage
shutdown
VDD
FAULT (9)
ITRIP (10)
SD (11)
Over current
protection
Internal Voltage
reference
Shutdown
Figure 3. Simplified Block Diagram
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NFAQ1560R43T
PIN FUNCTION DESCRIPTION
Pin
1
Name
VSS
Description
Low−Side Common Supply Ground
2
VDD
Low−Side Bias Voltage for IC and IGBTs Driving
Signal Input for High−Side U Phase
3
HIN(U)
HIN(V)
HIN(W)
LIN(U)
LIN(V)
LIN(W)
FAULT
ITRIP
SD
4
Signal Input for High−Side V Phase
5
Signal Input for High−Side W Phase
6
Signal Input for Low−Side U Phase
7
Signal Input for Low−Side V Phase
8
Signal Input for Low−Side W Phase
9
Fault output
10
11
12
13
14
17
18
19
20
22
26
28
32
34
38
Input for Over Current Protection
Shut Down Input
CFOD
TH1
Capacitor and Resistor for Fault Output Duration Selection
Thermistor Bias Voltage
TH2
Series Resistor for Thermistor
NU
Negative DC−Link Input for U Phase
NV
Negative DC−Link Input for V Phase
NW
Negative DC−Link Input for W Phase
VS(W), W
VB(W)
VS(V), V
VB(V)
VS(U), U
VB(U)
P
High−Side Bias Voltage GND for W phase IGBT Driving, Output for W Phase
High−Side Bias Voltage for W phase IGBT Driving
High−Side Bias Voltage GND for V phase IGBT Driving, Output for V Phase
High−Side Bias Voltage for V phase IGBT Driving
High−Side Bias Voltage GND for U phase IGBT Driving, Output for U Phase
High−Side Bias Voltage for U phase IGBT Driving
Positive DC−Link Input
NOTE: Pins 15, 16, 21, 23, 24, 25, 27, 29, 30, 31, 33, 35, 36 and 37 are not present
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NFAQ1560R43T
ABSOLUTE MAXIMUM RATINGS at T = 25°C (Note 1)
C
Parameter
Supply Voltage
Symbol
Conditions
Rating
450
600
15
Unit
V
V
PN
P − NU, NV, NW, VPN (surge) < 500 V (Note 2)
P − U, V, W; U − NU; V − NV; W − NW
P, U, V, W, NU, NV, NW terminal current
P, U, V, W, NU, NV, NW terminal current,
Collector−Emitter Voltage
V
CES
V
Each IGBT Collector Current
I
C
A
7.5
A
T
T
T
T
= 100°C
C
C
C
C
Each IGBT Collector Current (Peak)
Corrector Dissipation
ICp
= 25°C, Under 1 ms Pulse Width
= 25°C, Per One Chip (IGBT Part)
= 25°C, Per One Chip (FRD Part)
30
50
A
W
W
V
P
C
26.5
High−Side Control Bias voltage
V
BS
VB(U) − VS(U), VB(V) − VS(V), VB(W) − VS(W)
−0.3 to +20.0
(Note 3)
Control Supply Voltage
Input Signal Voltage
V
VDD − VSS
−0.3 to +20.0
V
V
DD
V
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W) − VSS
−0.3 to V
IN
DD
FAULT Terminal Voltage
CFOD Terminal Voltage
SD Terminal Voltage
V
FAULT − VSS
CFOD − VSS
SD − VSS
−0.3 to V
−0.3 to V
−0.3 to V
V
V
FAULT
DD
DD
DD
V
CFOD
V
SD
V
Current Sensing Input Voltage
Operating Junction Temperature
Storage Temperature
V
ITRIP − VSS
−0.3 to +10.0
150
V
ITRIP
T
j
_C
_C
_C
Nm
Vrms
T
−40 to +125
−40 to +125
0.6
stg
Module Case Operation Temperature
Tightening Torque
T
c
MT
Case mounting screws
Isolation Voltage
V
50 Hz sine wave AC 1 minute (Note 4)
2000
iso
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters
2. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal.
3. VBS = VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W)
4. Test conditions : AC2500V, 1 s
RECOMMENDED OPERATING RANGES
Rating
Supply Voltage
Symbol
Conditions
P − NU, NV, NW
Min
0
Typ
280
15
Max
450
Unit
V
V
PN
V
BS
High−Side Control Bias
Voltage
VB(U) − VS(U), VB(V) − VS(V),
VB(W) − VS(W)
13.0
17.5
V
Control Supply Voltage
ON−state Input Voltage
OFF−state Input Voltage
PWM Frequency
V
VDD − VSS
14.0
3.0
0
15
−
16.5
5.0
0.3
20
−
V
V
DD
V
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W) − VSS
IN(ON)
V
−
V
IN(OFF)
f
1
−
kHz
ms
ms
Nm
PWM
Dead Time
DT
Turn−off to Turn−on (external)
ON and OFF
1
−
Allowable Input Pulse Width
Tightening Torque
PWIN
1
−
−
‘M3’ Type Screw
0.4
−
0.6
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NFAQ1560R43T
ELECTRICAL CHARACTERISTICS at T = 25 _C, V
(V , V ) = 15 V unless otherwise noted.
C
BIAS
BS
DD
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
POWER OUTPUT SECTION
Collector−Emitter Leakage Current
Collector−Emitter Saturation Voltage
V
= 600 V
I
−
−
−
−
−
−
−
−
100
2.5
−
mA
V
CE
CES
IN = 5 V, I = 15 A, T = 25 _C
V
1.8
1.4
2.0
1.6
−
C
j
CE(sat)
IN = 5 V, I = 7.5 A, T = 100 _C
V
C
j
IN = 0 V, I = −15 A, T = 25 _C
V
F
2.5
−
V
FWDi Forward Voltage
C
j
IN = 0 V, I = −7.5 A, T = 100 _C
V
C
j
Inverter IGBT Part (per 1/6 Module)
R
2.5
4.7
_C/W
_C/W
Junction to Case Thermal Resistance
th(j−c)Q
Inverter FRD Part (per 1/6 Module)
R
−
th(j−c)F
SWITCHING CHARACTER
t
−
−
−
−
−
−
−
−
−
−
0.4
0.5
1.1
1.2
−
ms
ms
mJ
mJ
mJ
mJ
mJ
mJ
mJ
ns
Switching Time
I
= 15 A, V = 300 V, T = 25_C,
ON
C
PN
j
Inductive Switching
t
OFF
Turn−on Switching Loss
Turn−off Switching Loss
Total Switching Loss
E
360
I
C
I
C
I
C
= 15 A, V = 300 V, T = 25_C
ON
PN
j
E
OFF
E
TOT
260
−
620
−
Turn−on Switching Loss
Turn−off Switching Loss
Total Switching Loss
E
180
−
= 7.5 A, V = 300 V, T = 100_C
ON
OFF
TOT
PN
j
E
E
E
180
−
360
−
Diode Reverse Recovery Energy
Diode Reverse Recovery Time
Reverse Bias Safe Operating Area
Short Circuit Safe Operating Area
DRIVER SECTION
110
−
= 7.5 A, V = 300 V, T = 100_C,
REC
PN
j
(di/dt set by internal driver)
t
120
−
RR
I
C
= 30 A, V = 450 V
RBSOA
Full Square
−
CE
V
= 400 V, T = 100_C
SCSOA
4
−
ms
CE
j
Quiescent VBS Supply Current
Quiescent VDD Supply Current
ON Threshold Voltage
V
V
= 15 V, HIN = 0 V, per driver
I
−
−
0.08
0.95
−
0.4
3.0
2.5
−
mA
mA
V
BS
QBS
= 15 V, LIN = 0 V, V − V
I
DD
DD
SS
QDD
V
IN(ON)
−
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W) − VSS
OFF Threshold Voltage
V
0.8
−
−
V
IN(OFF)
Logic 1 Input Current
V
V
= +3.3 V
= 0 V
I
660
−
900
3
mA
mA
W
IN
IN+
Logic 0 Input Current
I
−
IN
IN−
Bootstrap ON Resistance
FAULT Terminal Sink Current
Fault−Output Pulse Width
I
B
= 1 mA
RB
−
500
2
−
FAULT: ON / VFAULT = 0.1 V
IoSD
−
−
mA
ms
FAULT − VSS
t
1.1
1.65
2.2
FOD
From time fault condition clear
R = 2 MW, C = 1 nF
CFOD Threshold
CFOD − VSS
SD − VSS
V
−
−
8
−
2.5
−
V
V
CFOD
V
−
Shut Down Threshold
SD+
SD−
V
0.8
0.44
−
−
V
ITRIP Trip Level
ITRIP − VSS
V
0.49
1.1
350
11.1
10.9
0.2
0.54
−
V
ITRIP
ITRIP
ITRIP to Shutdown Propagation Delay
ITRIP Blanking Time
t
ms
ns
V
t
250
10.3
10.1
−
−
ITRIPBL
Reset Level
Detection Level
Hysteresis
UVBSR
UVBSD
UVBSH
11.9
11.7
−
High−Side Control Bias Voltage
Under−Voltage Protection
V
V
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NFAQ1560R43T
ELECTRICAL CHARACTERISTICS at T = 25 _C, V
(V , V ) = 15 V unless otherwise noted.
C
BIAS
BS
DD
Parameter
DRIVER SECTION
Supply Voltage Under−Voltage Protection
Test Conditions
Symbol
Min
Typ
Max
Unit
Reset Level
UVDDR
UVDDD
UVDDH
10.3
10.1
−
11.1
10.9
0.2
11.7
11.5
−
V
V
V
Detection Level
Hysteresis
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
TYPICAL CHARACTERISTICS
30
25
20
15
10
5
30
25
20
T = 25°C
J
T = 100°C
J
15
10
5
T = 100°C
J
T = 25°C
J
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
CE
, Collector−Emitter Voltage (V)
V , Forward Voltage (V)
F
Figure 4. VCE versus IC for Different Temperatures
(VDD = 15 V)
Figure 5. VF versus IF for Different Temperatures
1,400
1,400
1,200
1,000
800
V
PN
V
DD
= 300 V
= 15 V
V
PN
V
DD
= 300 V
= 15 V
1,200
1,000
800
600
400
200
0
T = 100°C
J
600
T = 100°C
J
400
T = 25°C
J
T = 25°C
J
200
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
I , Collector Current (A)
C
I , Collector Current (A)
C
Figure 6. EON versus IC for Different Temperatures
Figure 7. EOFF versus IC for Different Temperatures
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NFAQ1560R43T
TYPICAL CHARACTERISTICS (Continued)
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
0.000001 0.00001 0.0001
0.001
0.01
0.1
1
0.000001 0.00001 0.0001
0.001
0.01
0.1
1
ON−Pulse Width (s)
ON−Pulse Width (s)
Figure 9. Thermal Impedance Plot (FRD)
Figure 8. Thermal Impedance Plot (IGBT)
600
30
25
20
15
10
5
600
500
400
300
200
100
0
30
500
400
300
200
100
0
25
20
15
10
5
Vce
Ic
Ic
Vce
0
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Time (ms)
Time (ms)
Figure 11. Turn−off Waveform Tj = 1005C, VCC = 300 V
Figure 10. Turn−on Waveform Tj = 1005C, VCC = 300 V
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NFAQ1560R43T
APPLICATIONS INFORMATION
Input / Output Timing Chart
VBS undervoltage protection reset signal
HIN is disabled until LIN receives input (Note 5)
HIN
LIN
VDD undervoltage protection reset voltage (Note2)
VBS undervoltage protection reset voltage(Note3)
VDD
VB(U), VB(V), VB(W)
VIT w0.54V
(
)
Note4
ITRIP
VIT < 0.44V
FAULT driven output
(with pull−up)
SD driven input
(with pull−up)
Cross−conduction prevention period(Note1)
Upper IGBT
Gate Drive
Lower IGBT
Gate Drive
Automatic reset after protection(Fault−Output Pulse Width)
NOTES:
1. This section of the timing diagram shows the effect of cross−conduction prevention.
2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go
low, switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume.
3. This section shows that when the bootstrap voltage on VB(U) (VB(V), VB(W)) drops, the corresponding high side output
U (V, W) is switched off. When the voltage on VB(U) (VB(V), VB(W)) rises sufficiently, normal operation will resume.
4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBTs are turned off. Normal operation
resumes later after the over−current condition is removed.
5. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN
input before enabling the driver for the HIN signal.
Figure 12. Input / Output Timing Chart
Table 1. INPUT / OUTPUT LOGIC TABLE
INPUT
ITRIP
OUTPUT
Low side IGBT
HIN
H
LIN
L
SD
H
H
H
H
X
High side IGBT
ON (Note 5)
OFF
U,V,W
FAULT
OFF
OFF
OFF
OFF
ON
L
L
L
L
H
L
OFF
ON
P
L
H
L
NU,NV,NW
L
OFF
OFF
OFF
OFF
OFF
High Impedance
High Impedance
High Impedance
High Impedance
H
H
X
OFF
X
OFF
X
X
L
OFF
OFF
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NFAQ1560R43T
Table 2. THERMISTOR CHARACTERISTICS
Parameter
Resistance
Symbol
Condition
Min
99
Typ
100
5.4
Max
101
Unit
kW
kW
K
R
T
= 25_C
= 100_C
25
th
R
T
5.2
5.6
100
th
B−Constant (25 to 50_C)
B
4208
−40
4250
−
4293
+125
Temperature Range
_C
10000
1000
100
10
max
typ
min
1
−40 −30 −20 −10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
T , Thermistor Temperature (5C)
th
Figure 13. Thermistor Resistance versus Thermistor Temperature
6.0
5.0
4.0
3.0
2.0
1.0
0.0
max
typ
min
−40 −30 −20 −10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
T , Thermistor Temperature (5C)
th
Figure 14. Thermistor Voltage versus Thermistor Temperature
Conditions: RTH = 39 kW, Pull−up Voltage 5.0 V (see Figure 2)
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NFAQ1560R43T
FAULT Pin
Calculation of Bootstrap Capacitor Value
The bootstrap capacitor value CB is calculated using the
following approach. The following parameters influence the
choice of bootstrap capacitor:
• VBS: Bootstrap power supply.
15 V is recommended.
• QG: Total gate charge of IGBT at VBS = 15 V.
8 nC.
• UVLO: Falling threshold for UVLO.
Specified as 12 V.
• IDMAX: High side drive power dissipation.
Specified as 0.4 mA.
• TONMAX: Maximum ON pulse width of high side
IGBT.
The FAULT output is an open drain output requiring
a pull−up resistor. If the pull−up voltage is 5 V, use a pull−up
resistor with a value of 6.8 kW or higher. If the pull−up
voltage is 15 V, use a pull−up resistor with a value of 20 kW
or higher. The FAULT output is triggered if there is a VDD
undervoltage or an overcurrent condition.
Under−voltage Protection
If VDD goes below the VDD supply under−voltage
lockout falling threshold, the FAULT output is switched on.
The FAULT output stays on until VDD rises above the VDD
supply under−voltage lockout rising threshold. After VDD
has risen above the threshold to enable normal operation, the
driver waits to receive an input signal on the LIN input
before enabling the driver for the HIN signal.
Capacitance calculation formula:
Overcurrent Protection
CB = (QG + IDMAX * TONMAX)/(VBS − UVLO)
An over−current condition is detected if the voltage on the
ITRIP pin is larger than the reference voltage. There is a
blanking time of typically 350 ns to improve noise
immunity. After a shutdown propagation delay of typically
1.1 ms, the FAULT output is switched on. The FAULT output
is held on for a time determined by the resistor and capacitor
connected to the CFOD pin. If RCLR = 2 MW and CCLR =
1 nF, the FAULT output is switched on for 1.65 ms (typ.)
because the FAULT pin goes back to high impedance when
CFOD is higher than 8 V (typ.).
CB is recommended to be approximately 3 times the value
calculated above. The recommended value of CB is in the
range of 1 to 47 mF, however, the value needs to be verified
prior to production. When not using the bootstrap circuit,
each high side driver power supply requires an external
independent power supply.
The internal bootstrap circuit uses a MOSFET. The turn
on time of this MOSFET is synchronized with the turn on of
the low side IGBT. The bootstrap capacitor is charged by
turning on the low side IGBT.
The over−current protection threshold should be set to be
equal or lower to 2 times the module rated current (Io).
An additional fuse is recommended to protect against
system level or abnormal over−current fault conditions.
If the low side IGBT is held on for a long period of time
(more than one second for example), the bootstrap voltage
on the high side MOSFET will slowly discharge.
Capacitors on High Voltage and VDD Supplies
Both the high voltage and VDD supplies require an
electrolytic capacitor and an additional high frequency
capacitor. The recommended value of the high frequency
capacitor is between 100 nF and 10 mF.
100
10
1
SD Pin
The SD terminal pin is used to enable or shut down the
built−in driver. If the voltage on the SD pin rises above the
VSD+ voltage, the output drivers are enabled. If the voltage
on the SD pin falls below the VSD− voltage, the drivers are
disabled.
0.1
0.01
0.1
1
10
100
1000
Tonmax (ms)
Minimum Input Pulse Width
When input pulse width is less than 1 ms, an output may
not react to the pulse. (Both ON signal and OFF signal)
Figure 15. Bootstrap Capacitance versus Tonmax
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11
NFAQ1560R43T
TEST CIRCUITS
• ICES
34
32
ICE
VBS=15V
VBS=15V
VBS=15V
VDD=15V
U+
38
32
V+
38
26
W+
38
U−
32
17
V−
26
18
W−
20
A
A
A
B
28
26
20
19
VCE
U+, V+, W+ : High side phase
U−, V−, W− : Low side phase
22
20
2,9,11,12
B
1,10,17,18,19
Figure 16. Test Circuit for ICE
• VCE(sat) (Test by pulse)
U+
38
32
3
V+
38
26
4
W+
38
20
5
U−
32
17
6
V−
26
18
7
W−
20
19
8
34
VBS=15V
VBS=15V
VBS=15V
A
B
C
A
32
28
26
V
IC
22
20
VCE(sat)
2,9,11,12
VDD=15V
5V
C
B
1,10,17,18,19
Figure 17. Test Circuit for VCE(SAT)
• VF (Test by pulse)
U+
38
32
V+
W+
38
U−
32
17
V−
26
18
W−
20
A
B
38
26
A
20
19
V
VF
B
Figure 18. Test Circuit for VF
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12
NFAQ1560R43T
• RB (Test by pulse)
U+
2
V+
2
W+
2
A
B
A
B
C
34
6
28
7
22
8
V
IB
VB
2,9,11,12
VDD=15V
5V
(RB)
C
1,10,17,18,19
Figure 19. Test Circuit for RB
• IQBS, IQDD
VBS U+
VBS V+
28
VBS W+
22
V
DD
IQBS
A
B
34
32
2
A
A
A
B
VBSx=15V
26
20
1
IQDD
VDD=15V
2
9,11,12
1,10
Figure 20. Test Circuit for ID
• Switching Time (The circuit is a representative example of the Inverter Low side U phase.)
34
32
VBS=15V
VBS=15V
VBS=15V
VDD=15V
38
32
Input Signal
(0 to 5V)
28
26
CS
22
20
90%
lo
10%
2,9,11,12
6
17
Input Signal
tON
tOFF
Io
1,10,17,18,19
Figure 21. Test Circuit for Switching Time
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DIP38, 29.60x18.20x9.80, 1.00P (EP−5)
CASE 181AE
ISSUE B
DATE 26 APR 2023
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXXXXXXXX
ZZZATYWW
XXX = Specific Device Code
ZZZ = Assembly Lot Code
AT = Assembly & Test Location
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Y
= Year
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON28691H
DIP38, 29.60x18.20x9.80, 1.00P (EP−5)
PAGE 1 OF 1
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