NCV890131 [ONSEMI]
1.2 A, 2 MHz Automotive Buck Switching Regulator;
| 型号： | NCV890131 |
| 厂家： | 
ONSEMI |
| 描述： | 1.2 A, 2 MHz Automotive Buck Switching Regulator |
| 文件： | 总19页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV890131
1.2 A, 2 MHz Automotive
Buck Switching Regulator
The NCV890131 is a fixed−frequency, monolithic, Buck switching
regulator intended for Automotive, battery−connected applications
that must operate with up to a 36 V input supply. The regulator is
suitable for systems with low noise and small form factor
requirements often encountered in automotive driver information
systems. The NCV890131 is capable of converting the typical 4.5 V to
18 V automotive input voltage range to outputs as low as 3.3 V at a
constant switching frequency above the sensitive AM band,
eliminating the need for costly filters and EMI countermeasures. Two
pins are provided to synchronize switching to a clock, or to another
NCV890131. The NCV890131 also provides several protection
features expected in Automotive power supply systems such as current
limit, short circuit protection, and thermal shutdown. In addition, the
high switching frequency produces low output voltage ripple even
when using small inductor values and an all−ceramic output filter
capacitor − forming a space−efficient switching regulator solution.
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MARKING DIAGRAM
V8901
31
ALYWG
DFN10
G
CASE 485C
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
(Note: Microdot may be in either location)
Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
• Internal N−Channel Power Switch
• Low V Operation Down to 4.5 V
IN
• High V Operation to 36 V
IN
• Withstands Load Dump to 45 V
• 2 MHz Free−running Switching Frequency
• Low Shutdown Current
• Wettable Flanks − DFN
• NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP
Capable
• Auto−synchronizes with Other NCV890131 or to an
External Clock
• Logic level Enable Input Can be Directly Tied to
Battery
• 1.4 A (min) Cycle−by−Cycle Peak Current Limit
• These Devices are Pb−Free and are RoHS Compliant
• Short Circuit Protection enhanced by Frequency
Foldback
Applications
• Audio
•
1.75% Output Voltage Tolerance
• Output Voltage Adjustable Down to 0.8 V
• 1.4 Millisecond Internal Soft−Start
• Thermal Shutdown (TSD)
• Infotainment
• Safety − Vision Systems
• Instrumentation
CDRV
DBST
NCV890131
VIN
L1
VOUT
COUT
1
2
3
4
5
VIN
SW 10
CBST
CIN
SYNC
DFW
DRV
BST
9
8
7
6
SYNC IN
OUT
RFB1
SYNCO SYNCI
GND
EN
FB
EN
RFB2
COMP
RCOMP
CCOMP
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
February, 2015 − Rev. 3
NCV890131/D
NCV890131
CDRV
SW
DBST
VIN
VIN
CIN
L1
VOUT
DFW
3 V
Reg
CBST
COUT
Oscillator
DRV
BST
PWM
LOGIC
OFF
ON
SYNCO
SYNCI
Sync Out
Sync In
Sync
Out In
1.2 A
+
S
+
+
−
FB
GND
−
+
+
TSD
Soft−Start
RESET
COMP
VOLTAGES
MONITORS
RCOMP
CCOMP
EN
Enable
Figure 2. NCV890131 Block Diagram
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2
NCV890131
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 45
45
Unit
V
Min/Max Voltage VIN
Max Voltage VIN to SW
Min/Max Voltage SW
V
−0.7 to 40
−3.0
V
Min Voltage SW − 20ns
Min/Max Voltage BST
Min/Max Voltage BST to SW
Min/Max Voltage on EN
Min/Max Voltage COMP
Min/Max Voltage FB
V
−0.3 to 40
−0.3 to 3.6
−0.3 to 40
−0.3 to 2
−0.3 to 18
−0.3 to 3.6
−0.3 to 3.6
−0.3 to 6
50
V
V
V
V
Min/Max Voltage SYNCO
Min/Max Voltage DRV
Min/Max Voltage SYNCI
V
V
V
Thermal Resistance, 3x3 DFN Junction−to−Ambient*
Storage Temperature range
R
°C/W
°C
°C
q
JA
J
−55 to +150
−40 to +150
Operating Junction Temperature Range
T
ESD withstand Voltage
Human Body Model
Machine Model
Charge Device Model
V
ESD
2.0
200
>1.0
kV
V
kV
Moisture Sensitivity
MSL
Level 1
260
Peak Reflow Soldering Temperature
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
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3
NCV890131
SW
1
2
3
4
5
VIN
DRV
10
9
BST
8
SYNCI
FB
SYNCO
GND
7
COMP
EN
6
(Top View)
Figure 3. Pin Connections
PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
VIN
Description
1
2
3
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
Output voltage to provide a regulated voltage to the Power Switch gate driver.
DRV
SYNCO
Synchronization output. Turn−on of the Power Switch causes the SYNCO signal to fall. SYNCO rises
half a switching period later. Connecting to the SYNCI pin of another NCV890131 causes them to switch
out−of−phase
4
5
GND
EN
Battery return, and output voltage ground reference.
This TTL compatible Enable input allows the direct connection of Battery as the enable signal. Grounding
this input stops switching and reduces quiescent current draw to a minimum.
6
7
8
COMP
FB
Error Amplifier output, for tailoring transient response with external compensation components.
Feedback input pin to program output voltage, and detect pre−charged or shorted output conditions.
SYNCI
Synchronization input. Connecting an external clock to the SYNCI pin synchronizes switching to the ris-
ing edge of the SYNCI voltage.
9
BST
SW
Bootstrap input provides drive voltage higher than VIN to the N−channel Power Switch for optimum
switch R
and highest efficiency.
DS(on)
10
Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode to
this pin.
Exposed
Pad
Connect to Pin 4 (electrical ground) and to a low thermal resistance path to the ambient temperature
environment.
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4
NCV890131
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 28 V, V = 5 V, V
= V
+ 3.0 V, C
= 0.1 mF, Min/Max values are valid
IN
EN
BST
SW
DRV
for the temperature range −40°C ≤ T ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
QUIESCENT CURRENT
Symbol
Conditions
Min
Typ
Max
Unit
Quiescent Current, shutdown
Quiescent Current, enabled
UNDERVOLTAGE LOCKOUT − VIN (UVLO)
UVLO Start Threshold
UVLO Stop Threshold
UVLO Hysteresis
I
V
IN
= 13.2 V, V = 0 V, T = 25°C
10
mA
qSD
EN
J
I
V
IN
= 13.2 V
3.0
mA
qEN
V
V
V
rising
falling
4.1
3.9
0.1
4.5
4.4
0.2
V
V
V
UVLSTT
UVLSTP
UVLOHY
IN
V
IN
V
ENABLE (EN)
Logic Low
V
0.8
8.0
V
V
ENLO
Logic High
V
2.0
30
ENHI
Input Current
I
mA
EN
SOFT−START (SS)
Soft−Start Completion Time
VOLTAGE REFERENCE
FB Pin Voltage during regulation
ERROR AMPLIFIER
FB Bias Current
t
0.8
1.4
0.8
2.0
0.814
1.0
ms
V
SS
V
FBR
COMP shorted to FB
0.786
0.25
I
V
FB
= 0.8 V
mA
FBBIAS
Transconductance
V
= 1.3 V
IN
IN
mmho
COMP
g
4.5 V < V < 18 V
20 V < V < 28 V
0.6
0.3
1.0
0.5
1.5
0.75
m
g
m(HV)
Output Resistance
R
1.4
MW
mA
OUT
SOURCE
COMP Source Current Limit
I
V
FB
= 0.63 V, V
= 1.3 V
COMP
4.5 V < V < 18 V
75
40
IN
20 V < V < 28 V
IN
COMP Sink Current Limit
I
V
FB
= 0.97 V, V
= 1.3 V
mA
SINK
COMP
4.5 V < V < 18 V
75
40
IN
20 V < V < 28 V
IN
Minimum COMP voltage
OSCILLATOR
V
F
V
= 0.97 V
0.2
0.7
V
CMPMIN
FB
Frequency
F
4.5 < V < 18 V
20 V < V < 28 V
1.8
0.9
2.0
1.0
2.2
1.1
MHz
SW
SW(HV)
IN
IN
VIN FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
V
= 0.63 V
V
V
FB
V
IN
V
IN
rising
falling
V
V
18.4
18
20
19.8
FLDUP
FLDDN
Frequency Foldback Hysteresis
SYNCHRONIZATION
V
0.2
0.3
0.4
60
FLDHY
SYNCO Output Pulse Duty Ratio
SYNCO Output Pulse Falltime
SYNCO Output Pulse Risetime
SYNCI Input Resistance to ground
SYNCI Input High Threshold Voltage
SYNCI Input Low Threshold Voltage
SYNCI High Pulse Width
D
C
= 40 pF
40
%
ns
ns
kW
V
(SYNC)
LOAD
t
C
C
= 40 pF, 90% to 10%
= 40 pF, 10% to 90%
4
4
R(SYNC)
LOAD
LOAD
t
F(SYNC)
R
V
SYNCI
= 5.0 V
50
200
2.0
H(SYNC)
V
HSYNC
V
0.8
40
V
LSYNC
t
V
> max V
HSYNC
ns
HSYNCI
SYNC
1. Not tested in production. Limits are guaranteed by design.
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5
NCV890131
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 28 V, V = 5 V, V
= V
+ 3.0 V, C
= 0.1 mF, Min/Max values are valid
IN
EN
BST
SW
DRV
for the temperature range −40°C ≤ T ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
SYNCHRONIZATION
Symbol
Conditions
Min
Typ
Max
Unit
SYNCI Low Pulse Width
External Sync Frequency
Master Reassertion Time
t
V
< min V
LSYNC
40
ns
MHz
ns
LSYNCI
SYNC
F
1.8
2.5
SYNCI
t
Time from last rising SYNCI edge
to first un−synchronized turn−on.
650
I(SYNC)
VIN OVERVOLTAGE SHUTDOWN MONITOR
Overvoltage Stop Threshold
Overvoltage Start Threshold
Overvoltage Hysteresis
V
V
32.4
30
36
35.4
2.4
V
V
V
OVSTP
OVSTT
V
0.6
1.5
OVHY
SLOPE COMPENSATION
Ramp Slope (Note 1)
(With respect to switch current)
S
4.5 < V < 18 V
0.7
0.25
1.3
0.6
A/ms
ramp
IN
S
20 V < V < 28 V
ramp(HV)
IN
POWER SWITCH
ON Resistance
R
V
= V + 3.0 V
SW
650
10
mW
mA
ns
DSON
BST
Leakage current VIN to SW
Minimum ON Time
Minimum OFF Time
I
V
EN
= 0 V, V
= 0, V = 18 V
SW IN
LKSW
t
Measured at SW pin
45
70
ONMIN
t
Measured at SW pin
ns
OFFMIN
At F
= 2 MHz (normal)
30
50
SW
At F
= 500 kHz (max duty cycle)
30
70
SW
PEAK CURRENT LIMIT
Current Limit Threshold
I
1.4
1.55
1.7
A
LIM
SHORT CIRCUIT FREQUENCY FOLDBACK
Lowest Foldback Frequency
Lowest Foldback Frequency − High V
Hiccup Mode
F
V
V
= 0 V, 4.5 V < V < 18 V
400
200
24
500
250
32
600
300
40
kHz
SWAF
FB
IN
F
= 0 V, 20 V < V < 28 V
in
SWAFHV
FB IN
F
V
FB
= 0 V
SWHIC
GATE VOLTAGE SUPPLY (DRV pin)
Output Voltage
V
3.1
2.7
2.5
16
3.3
2.9
2.8
3.5
3.05
3.0
45
V
V
DRV
DRV POR Start Threshold
DRV POR Stop Threshold
DRV Current Limit
V
V
DRVSTT
DRVSTP
DRVLIM
V
I
V
DRV
= 0 V
mA
OUTPUT PRECHARGE DETECTOR
Threshold Voltage
V
SSEN
20
35
50
mV
THERMAL SHUTDOWN
Activation Temperature (Note 1)
Hysteresis (Note 1)
T
150
5
190
20
°C
°C
SD
T
HYS
1. Not tested in production. Limits are guaranteed by design.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NCV890131
TYPICAL CHARACTERISTICS CURVES
8
7
6
5
4
3
2
1
0
2.6
V
= 13.2 V
IN
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 4. Shutdown Quiescent Current vs.
Junction Temperature
Figure 5. Enabled Quiescent Current vs.
Junction Temperature
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 6. UVLO Start Threshold vs. Junction
Temperature
Figure 7. UVLO Stop Threshold vs. Junction
Temperature
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 8. Soft−Start Duration vs. Junction
Temperature
Figure 9. FB Regulation Voltage vs. Junction
Temperature
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7
NCV890131
TYPICAL CHARACTERISTICS CURVES
1.4
1.2
1.0
0.8
0.6
0.4
0.2
100
90
V
IN
= 4.5 V
80
V
= 4.5 V
IN
70
60
50
40
30
20
V
IN
= 28 V
V
IN
= 28 V
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 10. Error Amplifier Transconductance
vs. Junction Temperature
Figure 11. Error Amplifier Max Sourcing
Current vs. Junction Temperature
100
90
80
70
60
50
40
30
20
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
V
= 13.2 V
IN
V
= 4.5 V
IN
V
= 28 V
IN
V
= 28 V
IN
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 12. Error Amplifier Max Sinking Current
vs. Junction Temperature
Figure 13. Oscillator Frequency vs. Junction
Temperature
19.6
19.4
19.2
19.0
18.8
18.6
18.4
18.2
56
55
54
53
52
51
50
49
48
V
V
FLDUP
FLDDN
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 14. Rising Frequency Foldback
Threshold vs. Junction Temperature
Figure 15. SYNCO Pulse Duty Ratio vs.
Junction Temperature
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NCV890131
TYPICAL CHARACTERISTICS CURVES
160
140
120
100
80
900
800
700
600
500
400
300
200
100
0
60
40
−50
−25
0
25
50
75
100
125
150
150
150
−50
−25
0
25
50
75
100
125
15
T . JUNCTION TEMPERATURE (°C)
T . JUNCTION TEMPERATURE (°C)
J
J
Figure 16. SYNCI Input Resistance vs.
Junction Temperature
Figure 17. Power Switch RDS(on) vs. Junction
Temperature
80
75
70
65
60
55
50
45
40
75
70
65
60
55
50
45
40
35
−50
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 18. Minimum On Time vs. Junction
Temperature
Figure 19. Minimum Off Time vs. Junction
Temperature
1.70
1.65
1.60
1.55
1.50
1.45
1.40
600
V
= 4.5 V
IN
550
500
450
400
350
300
250
200
V
= 28 V
IN
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 20. Current Limit Threshold vs.
Junction Temperature
Figure 21. Short−Circuit Foldback Frequency
vs. Junction Temperature
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NCV890131
TYPICAL CHARACTERISTICS CURVES
40
38
36
34
32
30
28
26
24
3.50
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
I
= 0 mA
DRV
I
= 16 mA
DRV
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 22. Hiccup Mode Switching Frequency
vs. Junction Temperature
Figure 23. DRV Voltage vs. Junction
Temperature
3.1
3.0
2.9
2.8
2.7
2.6
2.5
30
29
28
27
26
25
24
23
22
21
V
V
DRVSTT
DRVSTP
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 24. DRV Reset Threshold vs. Junction
Temperature
Figure 25. DRV Current Limit vs. Junction
Temperature
55
50
45
40
35
30
25
20
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
Figure 26. Output Precharge Detector
Threshold vs. Junction Temperature
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NCV890131
GENERAL INFORMATION
INPUT VOLTAGE
SLOPE COMPENSATION
An Undervoltage Lockout (UVLO) circuit monitors the
input, and inhibits switching and resets the Soft−start circuit
if there is insufficient voltage for proper regulation. The
NCV890131 can regulate a 3.3 V output with input voltages
above 4.5 V and a 5.0 V output with an input above 6.5 V.
The NCV890131 automatically terminates switching if
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50%. The fixed amplitude of the slope
compensation signal requires the inductor to be greater than
a minimum value, depending on output voltage, in order to
avoid sub−harmonic oscillations. For 3.3 V and 5 V output
voltages, the recommended inductor value is 4.7 mH.
input voltage exceeds V
(see Figure 27), and
OVSTP
withstands input voltages up to 45 V.
To limit the power lost in generating the drive voltage for
the Power Switch, the switching frequency is reduced by a
SHORT CIRCUIT FREQUENCY FOLDBACK
During severe output overloads or short circuits, the
NCV890131 automatically reduces its switching frequency.
This creates duty cycles small enough to limit the peak
current in the power components, while maintaining the
ability to automatically reestablish the output voltage if the
overload is removed. If the current is still too high after the
switching frequency folds back to 500 kHz, the regulator
enters an auto−recovery burst mode that further reduces the
dissipated power.
factor of 2 when the input voltage exceeds the V
IN
Frequency Foldback threshold V
(see Figure 27).
FLDUP
Frequency reduction is automatically terminated when the
input voltage drops back below the V Frequency Foldback
IN
threshold V
.
FLDDN
Fsw
(MHz)
2
CURRENT LIMITING
Due to the ripple on the inductor current, the average
output current of a buck converter is lower than the peak
current setpoint of the regulator. Figure 28 shows − for a
4.7 mH inductor − how the variation of inductor peak current
with input voltage affects the maximum DC current the
NCV890131 can deliver to a load.
1
1.4
1.3
4
45
18 20
30
36
VIN (V)
Figure 27. NCV890131 Switching Frequency
Reduction at High Input Voltage
(3.3 V
)
OUT
1.2
1.1
1.0
0.9
0.8
0.7
0.6
ENABLE
(5 V
)
OUT
The NCV890131 is designed to accept either a logic level
signal or battery voltage as an Enable signal. EN low induces
a ’sleep mode’ which shuts off the regulator and minimizes
its supply current to a couple of mA typically (I ) by
qSD
disabling all functions. Upon enabling, voltage is
established at the DRV pin, followed by a soft−start of the
switching regulator output.
0
5
10
15
20
25
30
35
40
INPUT VOLTAGE (V)
SOFT−START
Figure 28. NCV890131 Load Current Capability
Upon being enabled or released from a fault condition,
and after the DRV voltage is established, a soft−start circuit
ramps the switching regulator error amplifier reference
voltage to the final value. During soft−start, the average
switching frequency is lower than its normal mode value
(typically 2 MHz) until the output voltage approaches
regulation.
with 4.7 mH Inductor
www.onsemi.com
11
NCV890131
SYNCHRONIZATION
does not arrive at the SYNCI pin within the Master
Reassertion Time, the NCV890131 controls its own
switching frequency, allowing uninterrupted operation in
the event that the clock (or controlling NCV890131) is
turned off.
If internal conditions or excessive input voltage cause an
NCV890131 to fold back its switching frequency, the main
oscillator switching frequency is no longer derived from the
frequency received at the SYNCI pin. Under these
conditions, the SYNCO pin is held low.
Two NCV890131 can be synchronized out−of−phase to
one another by connecting the SYNCO pin of one to the
SYNCI pin of the other (Figure 29). Any number of
NCV890131 can also be synchronized to an external clock
(Figure 30). If a part does not have its switching frequency
controlled by the SYNCI input, it drives the SYNCO pin low
when it turns on the power switch, and drives it high half a
switching period later. When the switching frequency is
controlled by the SYNCI input, the SYNCO pin is held low.
Synchronization starts within 2 ms of soft−start completion.
A rising edge at the SYNCI pin causes an NCV890131 to
immediately turn on the power switch. If another rising edge
An external pulldown resistor is not required at the
SYNCI pin if it is unconnected.
VIN
CDRV1
DBST1
NCV890131
CDRV2
VOUT1
COUT1
L1
DBST2
NCV890131
1 VIN
SW 10
CBS1T
CIN1
VOUT2
L2
DFW2
1
2
3
4
5
VIN
SW 10
2 DRV
3 SYNCO
4 GND
5 EN
BST
SYNCI
FB
9
8
7
6
DFW1
CBST2
CIN2
COUT2
RFB1
DRV
SYNCO
GND
EN
BST
SYNCI
FB
9
8
7
6
RFB1
Synchronization
COMP
RFB2
RCOMP1
EN2
COMP
RFB2
SYNC MASTER
CCOMP1
RCOMP2
CCOMP2
SYNC SLAVE
Figure 29. NCV890131s Synchronized to Each Other
Master Enabled by Battery
VIN
CDRV1
DBST1
NCV890131
CDR2V
VOUT1
COUT1
L1
DBST2
1 VIN
SW 10
CBS1T
NCV890131
VIN SW 10
CIN1
VOUT2
COUT2
L2
DFW1
1
2 DRV
3 SYNCO
4 GND
5 EN
BST 9
SYNCI 8
FB 7
CBST2
CIN2
RFB11
2
3
4
5
DRV
BST
SYNCI
FB
9
8
7
6
RFB21
DFW2
SYNCO
GND
EN
COMP
6
RFB12
RCOMP1
EN2
COMP
RFB22
RCOMP2
CCOMP1
Synchronization
CLK
CCOMP2
Figure 30. Both NCV890131s Synchronized to External Clock
#1 Enabled by Battery
www.onsemi.com
12
NCV890131
BOOTSTRAP
In order for the bootstrap capacitor to stay charged, the
Switch node needs to be pulled down to ground regularly. In
very light load condition, the NCV890131 skips switching
cycles to ensure the output voltage stays regulated. When the
skip cycle repetition frequency gets too low, the bootstrap
voltage collapses and the regulator stops switching.
Practically, this means that the NCV890131 needs a
minimum load to operate correctly. Figure 31 shows the
minimum current requirements for different input and
output voltages.
At the DRV pin an internal regulator provides a
ground−referenced voltage to an external capacitor (C ),
to allow fast recharge of the external bootstrap capacitor
DRV
(C ) used to supply power to the power switch gate driver.
BST
If the voltage at the DRV pin goes below the DRV UVLO
Threshold V
, switching is inhibited and the
DRVSTP
Soft−start circuit is reset, until the DRV pin voltage goes
back up above V
.
DRVSTT
50
40
30
20
16
14
12
L = 2.2 mH
L = 4.7 mH
10
8
6
L = 4.7 mH
4
10
0
L = 2.2 mH
2
0
4.2
5.2
6.2
7.2
8.2
9.2
4.2
4.7
5.2
5.7
6.2
6.7
7.2
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Minimum Load 5 V Out
Minimum Load 3.3 V Out
20
18
16
14
12
10
8
50
45
40
35
30
25
20
15
10
L = 2.2 mH
L = 2.2 mH
L = 4.7 mH
6
L = 4.7 mH
4
2
0
5
0
4.2
4.7
5.2
5.7
6.2
6.7
7.2
4.2
6.2
8.2
10.2
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Minimum Load 3.7 V Out
Minimum Load 5.5 V Out
Figure 31. Minimum Load Current with Different Input and Output Voltages
www.onsemi.com
13
NCV890131
7
OUTPUT PRECHARGE DETECTION
Prior to Soft−start, the FB pin is monitored to ensure the
SW voltage is low enough to have charged the external
V
OUT
= 5 V
6
5
4
3
2
bootstrap capacitor (C ). If the FB pin is higher than
BST
V
SSEN
, restart is delayed until the output has discharged.
Figure 32 shows the IC starts to switch after the voltage on
FB pin reaches VSSEN, even the EN pin is high. After the
IC is switching, the FB pin follows the soft starts reference
to reach the final set point.
1
0
EN
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
(A)
I
OUT
Time
Figure 33. Minimum Input Voltage vs. Output Current
EXPOSED PAD
FB
The exposed pad (EPAD) on the back of the package must
be electrically connected to the electrical ground (GND pin)
for proper, noise−free operation.
V
SSEN
Time
Time
DESIGN METHODOLOGY
The NCV890131 being a fixed−frequency regulator with
the switching element integrated, is optimized for one value
of inductor. This value is set to 4.7 mH, and the slope
compensation is adjusted for this inductor. The only
components left to be designed are the input and output
capacitor and the freewheeling diode. Please refer to the
design spreadsheet www.onsemi.com NCV890131 page
that helps with the calculation.
SW
Figure 32. Output Voltage Detection
THERMAL SHUTDOWN
Output capacitor:
The minimum output capacitor value can be calculated
based on the specification for output voltage ripple:
A thermal shutdown circuit inhibits switching, resets the
Soft−start circuit, and removes DRV voltage if internal
temperature exceeds a safe level. Switching is automatically
restored when temperature returns to a safe level.
DIL
(eq. 1)
COUTmin
+
8 @ DVOUT @ FSW
MINIMUM DROPOUT VOLTAGE
When operating at low input voltages, two parameters
play a major role in imposing a minimum voltage drop
across the regulator: the minimum off time (that sets the
maximum duty cycle), and the on state resistance.
When operating in continuous conduction mode (CCM),
the output voltage is equal to the input voltage multiplied by
the duty ratio. Because the NCV890131 needs a sufficient
bootstrap voltage to operate, its duty cycle cannot be 100%:
With
− DI the inductor ripple current:
L
V
OUT
@ ǒ1 *
L @ FSW
Ǔ
VOUT
V
IN
(eq. 2)
DIL +
− DV
the desired voltage ripple.
OUT
it needs a minimum off time (t
) to periodically re−fuel
OFFmin
However, the ESR of the output capacitor also contributes
to the output voltage ripple, so to comply with the
requirement, the ESR cannot exceed R
the bootstrap capacitor C . This imposes a maximum duty
BST
ratio D
= 1 − t
.F
, with the switching
MAX
OFFmin SW(min)
:
ESRmax
frequency being folded back down to F
= 500 kHz to
SW(min)
DVOUT @ L @ FSW
keep regulating at the lowest input voltage possible.
The drop due to the on−state resistance is simply the
RESRmax
+
(eq. 3)
V
OUT
ǒ1 *
Ǔ
VOUT
V
voltage drop across the Switch resistance R
at the
DSON
IN
given output current: V
= I
.R
.
SWdrop
OUT DSon
Finally, the output capacitor must be able to sustain the ac
current (or RMS ripple current):
Which leads to the maximum output voltage in low Vin
condition: V = D .V − V
OUT
MAX IN(min)
SWdrop
DIL
(eq. 4)
IOUTac
+
Ǹ
2 3
www.onsemi.com
14
NCV890131
Typically, with the recommended 4.7 mH inductor, two
ceramic capacitors of 10 mF each in parallel give very good
results.
Then, knowing the thermal resistance of the package and
the amount of heatsinking on the PCB, the temperature rise
corresponding to this power dissipation can be estimated.
Input capacitor:
Freewheeling diode:
The input capacitor must sustain the RMS input ripple
The diode must be chosen according to its maximum
current and voltage ratings, and to thermal considerations.
As far as max ratings are concerned, the maximum reverse
voltage the diode sees is the maximum input voltage (with
some margin in case of ringing on the Switch node), and the
maximum forward current the peak current limit of the
current I
:
INac
DIL
D
(eq. 7)
Ǹ
IINac
+
2
3
It can be designed in combination with an inductor to build
an input filter to filter out the ripple current in the source, in
order to reduce EMI conducted emissions.
For example, using a 4.7 mH input capacitor, it is easy to
calculate that an inductor of 200 nH will ensure that the
input filter has a cut−off frequency below 200 kHz (low
enough to attenuate the 2 MHz ripple).
NCV890131, I
.
LIM
The power dissipated in the diode is P
:
Dloss
VOUT
(eq. 5)
@ VF ) IDRMS @ RD
@ ǒ1 * Ǔ
PDloss + IOUT
VIN
with:
− I
Error Amplifier and Loop Transfer Function
the average (dc) output current
OUT
The error amplifier is a transconductance type amplifier.
The output voltage of the error amplifier controls the peak
inductor current at which the power switch shuts off. The
Current Mode control method employed allows the use of a
simple, type II compensation to optimize the dynamic
response according to system requirements.
− V the forward voltage of the diode
F
− I
the RMS current in the diode:
DRMS
2
DIL
2
(
)
1 * D ǒ
IOUT
(eq. 6)
Ǔ
IDRMS
+
)
Ǹ
12
− R the dynamic resistance of the diode (extracted from
D
Figure 34 shows the error amplifier with the
compensation components and the voltage feedback divider.
the V/I curve of the diode in its datasheet).
VOUT
RFB1
VCOMP
RCOMP
V
FB
V
RO
Cp
RFB2
g
m
* V
CCOMP
Vref
Figure 34. Feedback Compensator Network Model
The transfer function from VOUT to VCOMP is the
product of the feedback voltage divider and the error
amplifier.
1
wpl +
(eq. 11)
(eq. 12)
Ro @ CCOMP
1
wph +
RCOMP @ Cp
RFB2
RFB1 ) RFB2
Gdivider(s) +
(eq. 8)
(eq. 9)
The output resistor Ro of the error amplifier is 1.4 MW and
gm is 1 mA/V. The capacitor Cp is for rejecting noise at high
frequency and is integrated inside the IC with a value of
18 pF.
The power stage transfer function (from Vcomp to output)
is shown below:
s
1 )
wz
Gerramp(s) + gm @ Ro @
s
s
wph
ǒ1 ) Ǔǒ1 ) Ǔ
wpl
1
wz +
(eq. 10)
RCOMP @ CCOMP
s
1 )
Rload
Ri
wz
s
1
(eq. 13)
@ Fh(s)
Gps(s) +
@
@
Rload@Tsw
1 )
[
]
1 )
@ Mc @ (1 * D) * 0.5
wp
L
1
wp +
(eq. 14)
(eq. 15)
Resr @ Cout
Mc @ (1 * D) * 0.5
L @ Cout @ Fsw
1
wp +
)
Rload @ Cout
www.onsemi.com
15
NCV890131
where
The bode plots of the open loop transfer function will
show the gain and phase margin of the system. The
compensation network is designed to make sure the system
has enough phase margin and bandwidth.
Se
Sn
Mc + 1 )
(eq. 16)
(eq. 17)
Vin * Vout
Sn +
@ Ri
L
Design of the Compensation Network
Ri represents the equivalent sensing resistor which has a
value of 0.29 W, Se is the compensation slope which is
291.9 kV/S, Sn is the slope of the sensing resistor current
during on time. Fh(s) represents the sampling effect from the
current loop which has two poles at one half of the switching
frequency:
The function of the compensation network is to provide
enough phase margin at crossover frequency to stabilize the
system as well as to provide high gain at low frequency to
eliminate the steady state error of the output voltage. Please
refer to the design spreadsheet www.onsemi.com
NCV890131 page that helps with the calculation.
1
Fh(s) +
(eq. 18)
The design steps will be introduced through an example.
s
s2
1 )
)
wn2
Example:
wn@Qp
wn + p @ Fsw
Qp +
Vin = 15.5 V, Vout = 3.3 V, Rload = 2.75 W, Iout = 1.2 A,
L = 4.7 mH, Cout = 20 mF (Resr = 7 mW)
The reference voltage of the feedback signal is 0.8 V and
to meet the minimum load requirements, select RFB1 =
100 W, RFB2 = 31.6 W.
1
(eq. 19)
[
]
p @ Mc @ (1 * D) * 0.5
The total loop transfer function is the product of power
stage and feedback compensation network.
From the specification, the power stage transfer function can
be plotted as below:
Gloop(s) + Gdivider(s) @ Gerramp(s) @ Gps(s) (eq. 20)
90
180
45
90
180
20‧log Gps f
arg Gps f
‧
(
( m))
0
0
(m)
⎣
⎣
⎦
p
− 45
− 90
− 90
100
− 180
1⋅ 10
3
4
5
6
1⋅ 10
1⋅ 10
1⋅ 10
f
m
(Hz)
Figure 35. Power Stage Bode Plots
(eq. 21)
The crossover frequency is chosen to be Fc = 70 kHz, the
power stage gain at this frequency is −8 dB (0.398) from
calculation. Then the gain of the feedback compensation
network must be 8 dB. Next is to decide the locations of one
zero and one pole of the compensator. The zero is to provide
phase boost at the crossover frequency and the pole is to
reject the noise of high frequency. In this example, a zero is
placed at 1/10 of the crossover frequency and a pole is placed
at 1/5 of the switching frequency (Fsw = 2 MHz):
2
Fc
Ǹ
1 ) ǒ Ǔ
Fp
Fp @ gm
Vout
RCOMP +
@
@ Ǹ
|
|
(Fp * Fz) @ Gps(Fc) Vref
2
Fz
1 ) ǒ Ǔ
Fc
1
CCOMP +
(eq. 22)
(eq. 23)
2p @ Fz @ RCOMP
Fz = 7000 Hz, Fp = 400000 Hz,
RCOMP, CCOMP and Cp can be calculated from the
following equations:
1
Cp +
2p @ Fp @ RCOMP
Note: there is an 18 pF capacitor at the output of the OTA
integrated in the IC, and if a larger capacitor needs to be
used, subtract this value from the calculated Cp. Figure 36
shows Cp is split into two capacitors. Cint is the 18 pF in the
IC. Cext is the extra capacitor added outside the IC.
www.onsemi.com
16
NCV890131
From the calculation:
So the feedback compensation network is as below:
RCOMP = 10.6 KW, CCOMP = 2 nF, Cp = 37 pF
VOUT
RFB1
100 W
VCOMP
V
FB
RCOMP
V
18 pF
Cint
19 pF
Cext
10 KW
RO
RFB2
31.6 W
g *V
m
CCOMP
2 nF
Vref
0.8 V
Figure 36. Example of the Feedback Compensation Network
Figure 37 shows the bode plot of the OTA compensator
90
180
90
45
180
20‧log Gerr_amp
f
arg Gerr_amp
(
f
(
‧
m ))
0
0
(m )
⎦ ⎦
⎣
⎣
p
− 45
− 90
− 90
100
− 180
1⋅ 10
3
4
5
6
1⋅ 10
1⋅ 10
1⋅ 10
f
m
(Hz)
Figure 37. Bode Plot of the OTA Compensator
The total loop bode plot is as below:
90
180
90
45
180
20‧log Gloop
f
arg Gloop
(
f
(
‧
m ))
0
0
(m )
⎦ ⎦
⎣
⎣
p
− 45
− 90
− 90
100
− 180
1⋅ 10
3
4
5
6
1⋅ 10
1⋅ 10
1⋅ 10
f
m
(Hz)
Figure 38. Bode Plot of the Total Loop
The crossover frequency is at 70 KHz and phase margin is 75 degrees.
www.onsemi.com
17
NCV890131
PCB LAYOUT RECOMMENDATION
♦ Freewheeling diode ³ inductor ³ Output capacitor
³ return through ground
− Minimize the length of high impedance signals, and
route them far away from the power loops:
♦ Feedback trace
As with any switching power supplies, there are some
guidelines to follow to optimize the layout of the printed
circuit board for the NCV890131. However, because of the
high switching frequency extra care has to be taken.
− Minimize the area of the power current loops:
♦ Comp trace
♦ Input capacitor ³ NCV890131 switch ³ Inductor
³ output capacitor ³ return through Ground
ORDERING INFORMATION
†
Device
NCV890131MWTXG
Package
DFN10 with wettable flanks
Shipping
3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
18
NCV890131
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE B
EDGE OF PACKAGE
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
L1
E
DETAIL A
Bottom View
PIN 1
(Optional)
REFERENCE
EXPOSED Cu
2X
0.15
C
MOLD CMPD
TOP VIEW
MILLIMETERS
2X
0.15
C
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
A3
(A3)
DETAIL B
A3
b
D
D2 2.40
E
0.20 REF
0.10
0.08
C
C
0.18
0.30
A1
3.00 BSC
2.60
3.00 BSC
1.90
0.50 BSC
0.19 TYP
A
DETAIL B
Side View
(Optional)
SEATING
PLANE
10X
E2 1.70
e
K
L
SIDE VIEW
A1
C
0.35
0.45
0.03
L1 0.00
D2
e
DETAIL A
SOLDERING FOOTPRINT*
10X
L
1
5
2.6016
E2
10X
K
1.8508
3.3048
2.1746
10
6
10X b
0.10
0.05
C
C
A
B
BOTTOM VIEW
NOTE 3
10X
0.5651
10X
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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For additional information, please contact your local
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NCV890131/D
相关型号：
NCV8901AMNTXG
IC 1.7 A SWITCHING REGULATOR, 2200 kHz SWITCHING FREQ-MAX, PDSO8, 3 X 3 MM, 0.50 MM PITCH, LEAD FREE, DFN-8, Switching Regulator or Controller
ONSEMI
NCV8901MNTXG
IC 1.7 A SWITCHING REGULATOR, 2200 kHz SWITCHING FREQ-MAX, PDSO8, 3 X 3 MM, 0.50 MM PITCH, LEAD FREE, DFN-8, Switching Regulator or Controller
ONSEMI
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