NCV890200 [ONSEMI]
2 A, 2 MHz Automotive Buck Switching Regulator;
| 型号： | NCV890200 |
| 厂家： | 
ONSEMI |
| 描述： | 2 A, 2 MHz Automotive Buck Switching Regulator |
| 文件： | 总18页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV890200
2 A, 2 MHz Automotive
Buck Switching Regulator
The NCV890200 is a fixed−frequency, monolithic, Buck switching
regulator intended for Automotive, battery−connected applications
that must operate with up to a 36 V input supply. The regulator is
suitable for systems with low noise and small form factor
requirements often encountered in automotive driver information
systems. The NCV890200 is capable of converting the typical 4.5 V to
18 V automotive input voltage range to outputs as low as 3.3 V at a
constant switching frequency above the sensitive AM band,
eliminating the need for costly filters and EMI countermeasures. The
NCV890200 also provides several protection features expected in
Automotive power supply systems such as current limit, short circuit
protection, and thermal shutdown. In addition, the high switching
frequency produces low output voltage ripple even when using small
inductor values and an all−ceramic output filter capacitor − forming a
space−efficient switching regulator solution.
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MARKING
DIAGRAM
8
NCV890200
ALYWX
SOIC−8 EP
8
G
CASE 751AC
1
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
Features
• Internal N−Channel Power Switch
• Low V Operation Down to 4.5 V
IN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
• High V Operation to 36 V
IN
• Withstands Load Dump to 40 V
• 2 MHz Free−running Switching Frequency
• Logic level Enable Input Can be Directly Tied to Battery
• 2.2 A (min) Cycle−by−Cycle Peak Current Limit
• Short Circuit Protection enhanced by Frequency Foldback
•
1.75% Output Voltage Tolerance
• Output Voltage Adjustable Down to 0.8 V
• 1.4 Millisecond Internal Soft−Start
• Thermal Shutdown (TSD)
• These Devices are Pb−Free and are RoHS Compliant
Applications
• Low Shutdown Current
• Audio
• Infotainment
• Safety − Vision Systems
• Instrumentation
• NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP
Capable
CDRV
DBST
NCV890200
L1
VIN
VOUT
COUT
1
2
3
4
VIN
SW
BST
8
7
6
5
CBST
CIN
DFW
RFB1
DRV
GND
EN
FB
EN
COMP
RFB2
RCOMP
CCOMP
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
October, 2014 − Rev. 2
NCV890200/D
NCV890200
CDRV
SW
DBST
VIN
VIN
CIN
L1
3.3 V
Reg
DFW
CBST
COUT
Oscillator
DRV
BST
PWM
LOGIC
OFF
ON
2 A
+
S
+
+
−
FB
GND
−
+
+
TSD
Soft−Start
RESET
COMP
VOLTAGES
MONITORS
RCOMP
CCOMP
EN
Enable
Figure 2. NCV890200 Block Diagram
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2
NCV890200
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 40
40
Unit
V
Min/Max Voltage VIN
Max Voltage VIN to SW
Min/Max Voltage SW
Min Voltage SW − 20ns
Min/Max Voltage BST
Min/Max Voltage BST to SW
Min/Max Voltage on EN
Min/Max Voltage COMP
Min/Max Voltage FB
V
−0.7 to 40
−3.0
V
V
−0.3 to 40
−0.3 to 3.6
−0.3 to 40
−0.3 to 2
−0.3 to 18
−0.3 to 3.6
40
V
V
V
V
Min/Max Voltage DRV
V
Thermal Resistance, Junction−to−Ambient*
Storage Temperature range
R
°C/W
°C
°C
q
JA
J
−55 to +150
−40 to +150
Operating Junction Temperature Range
ESD withstand Voltage
T
Human Body Model
Machine Model
Charge Device Model
V
ESD
2.0
200
>1.0
kV
V
kV
Moisture Sensitivity
MSL
Level 2
260
Peak Reflow Soldering Temperature
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
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3
NCV890200
1
2
8
SW
VIN
DRV
GND
7
6
BST
FB
3
4
5
COMP
EN
(Top View)
Figure 3. Pin Connections
PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
VIN
Description
1
2
3
4
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
Output voltage to provide a regulated voltage to the Power Switch gate driver.
Battery return, and output voltage ground reference.
DRV
GND
EN
This TTL compatible Enable input allows the direct connection of Battery as the enable signal. Grounding
this input stops switching and reduces quiescent current draw to a minimum.
5
6
7
COMP
FB
Error Amplifier output, for tailoring transient response with external compensation components.
Feedback input pin to program output voltage, and detect pre−charged or shorted output conditions.
Bootstrap input provides drive voltage higher than VIN to the N−channel Power Switch for optimum
BST
switch R
and highest efficiency.
DS(on)
8
SW
Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode to
this pin.
Exposed Pad
Connect to Pin 3 (electrical ground) and to a low thermal resistance path to the ambient temperature
environment.
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4
NCV890200
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 28 V, V = 5 V, V
= V
+ 3.0 V, C
= 0.1 mF, Min/Max values are valid
IN
EN
BST
SW
DRV
for the temperature range −40°C ≤ T ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
QUIESCENT CURRENT
Symbol
Conditions
Min
Typ
Max
Unit
Quiescent Current, shutdown
Quiescent Current, enabled
UNDERVOLTAGE LOCKOUT − VIN (UVLO)
UVLO Start Threshold
UVLO Stop Threshold
UVLO Hysteresis
I
V
IN
= 13.2 V, V = 0 V, T = 25°C
5
3
mA
qSD
EN
J
I
V
IN
= 13.2 V
mA
qEN
V
V
V
rising
falling
4.1
3.9
0.1
4.5
4.4
0.2
V
V
V
UVLSTT
UVLSTP
UVLOHY
IN
V
IN
V
ENABLE (EN)
Logic Low
V
0.8
8
V
V
ENLO
Logic High
V
2
ENHI
Input Current
I
30
mA
EN
SOFT−START (SS)
Soft−Start Completion Time
VOLTAGE REFERENCE
FB Pin Voltage during regulation
ERROR AMPLIFIER
FB Bias Current
t
0.8
1.4
0.8
2.0
0.814
1
ms
V
SS
V
FBR
COMP shorted to FB
0.786
0.25
I
V
FB
= 0.8 V
mA
FBBIAS
Transconductance
V
= 1.3 V
IN
IN
mmho
COMP
g
4.5 V < V < 18 V
20 V < V < 28 V
0.6
0.3
1
0.5
1.5
0.75
m
g
m(HV)
Output Resistance
R
1.4
MW
mA
OUT
SOURCE
COMP Source Current Limit
I
V
FB
= 0.63 V, V
= 1.3 V
COMP
4.5 V < V < 18 V
75
40
IN
20 V < V < 28 V
IN
COMP Sink Current Limit
I
V
FB
= 0.97 V, V
= 1.3 V
mA
SINK
COMP
4.5 V < V < 18 V
75
40
IN
20 V < V < 28 V
IN
Minimum COMP voltage
OSCILLATOR
V
F
V
= 0.97 V
0.2
0.7
V
CMPMIN
FB
Frequency
F
4.5 < V < 18 V
20 V < V < 28 V
1.8
0.9
2.0
1.0
2.2
1.1
MHz
SW
SW(HV)
IN
IN
VIN FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
V
FB
= 0.63 V
V
V
IN
V
IN
rising
falling
V
V
18.4
18
20
19.8
FLDUP
FLDDN
Frequency Foldback Hysteresis
V
0.2
0.3
0.4
V
FLDHY
SLOPE COMPENSATION
Ramp Slope (Note 1)
(With respect to switch current)
S
4.5 < V < 18 V
0.7
0.25
1.3
0.6
A/ms
ramp
IN
S
20 V < V < 28 V
ramp(HV)
IN
1. Not tested in production. Limits are guaranteed by design.
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5
NCV890200
ELECTRICAL CHARACTERISTICS (V = 4.5 V to 28 V, V = 5 V, V
= V
+ 3.0 V, C
= 0.1 mF, Min/Max values are valid
IN
EN
BST
SW
DRV
for the temperature range −40°C ≤ T ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
POWER SWITCH
ON Resistance
R
V
= V + 3.0 V
SW
650
10
mW
mA
ns
DSON
BST
Leakage current VIN to SW
Minimum ON Time
I
V
EN
= 0 V, V
= 0, V = 18 V
SW IN
LKSW
t
Measured at SW pin
Measured at SW pin
45
70
ONMIN
Minimum OFF Time
t
ns
OFFMIN
At F
= 2 MHz (normal)
30
50
SW
At F
= 500 kHz (max duty cycle)
30
70
SW
PEAK CURRENT LIMIT
Current Limit Threshold
I
2.2
2.45
2.7
A
LIM
SHORT CIRCUIT FREQUENCY FOLDBACK
Lowest Foldback Frequency
Lowest Foldback Frequency − High V
Hiccup Mode
F
V
V
= 0 V, 4.5 V < V < 18 V
400
200
24
500
250
32
600
300
40
kHz
SWAF
FB
IN
F
= 0 V, 20 V < V < 28 V
in
SWAFHV
FB IN
F
V
FB
= 0 V
SWHIC
GATE VOLTAGE SUPPLY (DRV pin)
Output Voltage
V
3.1
2.7
2.5
16
3.3
2.9
2.8
3.5
3.05
3.0
45
V
V
DRV
DRV POR Start Threshold
DRV POR Stop Threshold
DRV Current Limit
V
V
DRVSTT
DRVSTP
DRVLIM
V
I
V
DRV
= 0 V
mA
OUTPUT PRECHARGE DETECTOR
Threshold Voltage
V
SSEN
20
35
50
mV
THERMAL SHUTDOWN
Activation Temperature (Note 1)
Hysteresis (Note 1)
T
150
5
190
20
°C
°C
SD
T
HYS
1. Not tested in production. Limits are guaranteed by design.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NCV890200
TYPICAL CHARACTERISTICS CURVES
8
7
6
5
4
3
2
1
0
2.6
V
= 13.2 V
IN
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 4. Shutdown Quiescent Current vs.
Junction Temperature
Figure 5. Enabled Quiescent Current vs.
Junction Temperature
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 6. UVLO Start Threshold vs. Junction
Temperature
Figure 7. UVLO Stop Threshold vs. Junction
Temperature
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 8. Soft−Start Duration vs. Junction
Temperature
Figure 9. FB Regulation Voltage vs. Junction
Temperature
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7
NCV890200
TYPICAL CHARACTERISTICS CURVES
1.4
1.2
1.0
0.8
0.6
0.4
0.2
100
90
V
IN
= 4.5 V
80
V
= 4.5 V
IN
70
60
50
40
30
20
V
IN
= 28 V
V
IN
= 28 V
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 10. Error Amplifier Transconductance
vs. Junction Temperature
Figure 11. Error Amplifier Max Sourcing
Current vs. Junction Temperature
100
90
80
70
60
50
40
30
20
2.2
V
IN
= 13.2 V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
V
= 4.5 V
IN
V
= 28 V
IN
V
IN
= 28 V
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 12. Error Amplifier Max Sinking Current
vs. Junction Temperature
Figure 13. Oscillator Frequency vs. Junction
Temperature
19.6
19.4
19.2
19.0
18.8
18.6
18.4
18.2
900
800
700
600
500
400
300
200
100
0
V
V
FLDUP
FLDDN
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
15
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 14. Rising Frequency Foldback
Threshold vs. Junction Temperature
Figure 15. Power Switch RDS(on) vs. Junction
Temperature
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8
NCV890200
TYPICAL CHARACTERISTICS CURVES
80
75
70
65
60
55
50
45
40
75
70
65
60
55
50
45
40
35
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 16. Minimum On Time vs. Junction
Temperature
Figure 17. Minimum Off Time vs. Junction
Temperature
2.90
2.80
2.70
2.60
2.50
2.40
2.30
2.20
2.10
2.00
600
V
= 4.5 V
IN
550
500
450
400
350
300
250
200
V
IN
= 28 V
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 18. Current Limit Threshold vs.
Junction Temperature
Figure 19. Short−Circuit Foldback Frequency
vs. Junction Temperature
40
38
36
34
32
30
28
26
24
3.50
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
I
= 0 mA
DRV
I
= 16 mA
DRV
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 20. Hiccup Mode Switching Frequency
vs. Junction Temperature
Figure 21. DRV Voltage vs. Junction
Temperature
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9
NCV890200
TYPICAL CHARACTERISTICS CURVES
3.1
3.0
2.9
2.8
2.7
2.6
2.5
30
29
28
27
V
V
DRVSTT
26
25
24
23
22
21
DRVSTP
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
T . JUNCTION TEMPERATURE (°C)
J
Figure 22. DRV Reset Threshold vs. Junction
Temperature
Figure 23. DRV Current Limit vs. Junction
Temperature
55
50
45
40
35
30
25
20
−50
−25
0
25
50
75
100
125
150
T . JUNCTION TEMPERATURE (°C)
J
Figure 24. Output Precharge Detector
Threshold vs. Junction Temperature
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10
NCV890200
GENERAL INFORMATION
INPUT VOLTAGE
SLOPE COMPENSATION
An Undervoltage Lockout (UVLO) circuit monitors the
input, and inhibits switching and resets the Soft−start circuit
if there is insufficient voltage for proper regulation. The
NCV890200 can regulate a 3.3 V output with input voltages
above 4.5 V and a 5.0 V output with an input above 6.5 V.
The NCV890200 withstands input voltages up to 40 V.
To limit the power lost in generating the drive voltage for
the Power Switch, the switching frequency is reduced by a
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50%. The fixed amplitude of the slope
compensation signal requires the inductor to be greater than
a minimum value, depending on output voltage, in order to
avoid sub−harmonic oscillations. For 3.3 V and 5 V output
voltages, the recommended inductor value is 4.7 mH.
factor of 2 when the input voltage exceeds the V
IN
SHORT CIRCUIT FREQUENCY FOLDBACK
Frequency Foldback threshold V
(see Figure 25).
FLDUP
During severe output overloads or short circuits, the
NCV890200 automatically reduces its switching frequency.
This creates duty cycles small enough to limit the peak
current in the power components, while maintaining the
ability to automatically reestablish the output voltage if the
overload is removed. If the current is still too high after the
switching frequency folds back to 500 kHz, the regulator
enters an auto−recovery burst mode that further reduces the
dissipated power.
Frequency reduction is automatically terminated when the
input voltage drops back below the V Frequency Foldback
IN
threshold V
.
FLDDN
Fsw
(MHz)
2
1
CURRENT LIMITING
Due to the ripple on the inductor current, the average
output current of a buck converter is lower than the peak
current setpoint of the regulator. Figure 26 shows − for a
4.7 mH inductor − how the variation of inductor peak current
with input voltage affects the maximum DC current the
NCV890200 can deliver to a load.
4
18 20
36
VIN (V)
2.3
2.2
Figure 25. NCV890200 Switching Frequency
Reduction at High Input Voltage
(3.3 V
)
OUT
2.1
2.0
1.9
1.8
1.7
1.6
(5 V
)
OUT
ENABLE
The NCV890200 is designed to accept either a logic level
signal or battery voltage as an Enable signal. EN low induces
a ‘sleep mode’ which shuts off the regulator and minimizes
its supply current to a couple of mA typically (I ) by
qSD
disabling all functions. Upon enabling, voltage is
established at the DRV pin, followed by a soft−start of the
switching regulator output.
0
5
10
15
20
25
30
35
40
SOFT−START
INPUT VOLTAGE (V)
Upon being enabled or released from a fault condition,
and after the DRV voltage is established, a soft−start circuit
ramps the switching regulator error amplifier reference
voltage to the final value. During soft−start, the average
switching frequency is lower than its normal mode value
(typically 2 MHz) until the output voltage approaches
regulation.
Figure 26. NCV890200 Load Current Capability
with 4.7 mH Inductor
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11
NCV890200
BOOTSTRAP
In order for the bootstrap capacitor to stay charged, the
Switch node needs to be pulled down to ground regularly. In
very light load condition, the NCV890200 skips switching
cycles to ensure the output voltage stays regulated. When the
skip cycle repetition frequency gets too low, the bootstrap
voltage collapses and the regulator stops switching.
Practically, this means that the NCV890200 needs a
minimum load to operate correctly. Figure 27 shows the
minimum current requirements for different input and
output voltages.
At the DRV pin an internal regulator provides a
ground−referenced voltage to an external capacitor (C ),
to allow fast recharge of the external bootstrap capacitor
DRV
(C ) used to supply power to the power switch gate driver.
BST
If the voltage at the DRV pin goes below the DRV UVLO
Threshold V
, switching is inhibited and the
DRVSTP
Soft−start circuit is reset, until the DRV pin voltage goes
back up above V
.
DRVSTT
50
40
30
20
16
14
12
L = 2.2 mH
L = 4.7 mH
10
8
6
L = 4.7 mH
4
10
0
L = 2.2 mH
2
0
4.2
5.2
6.2
7.2
8.2
9.2
4.2
4.7
5.2
5.7
6.2
6.7
7.2
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Minimum Load 5 V Out
Minimum Load 3.3 V Out
20
18
16
14
12
10
8
50
45
40
35
30
25
20
15
10
L = 2.2 mH
L = 2.2 mH
L = 4.7 mH
6
L = 4.7 mH
4
2
0
5
0
4.2
4.7
5.2
5.7
6.2
6.7
7.2
4.2
6.2
8.2
10.2
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Minimum Load 3.7 V Out
Minimum Load 5.5 V Out
Figure 27. Minimum Load Current with Different Input and Output Voltages
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NCV890200
OUTPUT PRECHARGE DETECTION
EXPOSED PAD
Prior to Soft−start, the FB pin is monitored to ensure the
SW voltage is low enough to have charged the external
The exposed pad (EPAD) on the back of the package must
be electrically connected to the electrical ground (GND pin)
for proper, noise−free operation.
bootstrap capacitor (C ). If the FB pin is higher than
BST
V
, restart is delayed until the output has discharged.
SSEN
DESIGN METHODOLOGY
Figure 28 shows the IC starts to switch after the voltage on
FB pin reaches VSSEN, even the EN pin is high. After the
IC is switching, the FB pin follows the soft starts reference
to reach the final set point.
The NCV890200 being a fixed−frequency regulator with
the switching element integrated, is optimized for one value
of inductor. This value is set to 4.7 mH, and the slope
compensation is adjusted for this inductor. The only
components left to be designed are the input and output
capacitor and the freewheeling diode. Please refer to the
design spreadsheet www.onsemi.com NCV890200 page
that helps with the calculation.
EN
Output capacitor:
The minimum output capacitor value can be calculated
based on the specification for output voltage ripple:
Time
FB
DIL
(eq. 1)
COUTmin
+
V
SSEN
8 @ DVOUT @ FSW
With
− DI the inductor ripple current:
Time
L
SW
V
OUT
@ ǒ1 *
L @ FSW
Ǔ
VOUT
V
IN
(eq. 2)
DIL +
Time
− DV
the desired voltage ripple.
Figure 28. Output Voltage Detection
OUT
However, the ESR of the output capacitor also contributes
to the output voltage ripple, so to comply with the
THERMAL SHUTDOWN
requirement, the ESR cannot exceed R
:
ESRmax
A thermal shutdown circuit inhibits switching, resets the
Soft−start circuit, and removes DRV voltage if internal
temperature exceeds a safe level. Switching is automatically
restored when temperature returns to a safe level.
DVOUT @ L @ FSW
RESRmax
+
(eq. 3)
V
OUT
ǒ1 *
Ǔ
VOUT
V
IN
Finally, the output capacitor must be able to sustain the ac
current (or RMS ripple current):
MINIMUM DROPOUT VOLTAGE
When operating at low input voltages, two parameters
play a major role in imposing a minimum voltage drop
across the regulator: the minimum off time (that sets the
maximum duty cycle), and the on state resistance.
When operating in continuous conduction mode (CCM),
the output voltage is equal to the input voltage multiplied by
the duty ratio. Because the NCV890200 needs a sufficient
bootstrap voltage to operate, its duty cycle cannot be 100%:
DIL
(eq. 4)
IOUTac
+
Ǹ
2 3
Typically, with the recommended 4.7 mH inductor, two
ceramic capacitors of 10 mF each in parallel give very good
results.
Freewheeling diode:
it needs a minimum off time (t
) to periodically re−fuel
OFFmin
The diode must be chosen according to its maximum
current and voltage ratings, and to thermal considerations.
As far as max ratings are concerned, the maximum reverse
voltage the diode sees is the maximum input voltage (with
some margin in case of ringing on the Switch node), and the
maximum forward current the peak current limit of the
the bootstrap capacitor C . This imposes a maximum duty
BST
ratio D
= 1 − t
.F
, with the switching
MAX
OFFmin SW(min)
frequency being folded back down to F
keep regulating at the lowest input voltage possible.
The drop due to the on−state resistance is simply the
= 500 kHz to
SW(min)
voltage drop across the Switch resistance R
at the
DSON
NCV890200, I
.
LIM
given output current: V
= I
.R
.
SWdrop
OUT DSon
The power dissipated in the diode is P
:
Dloss
Which leads to the maximum output voltage in low Vin
condition: V = D .V − V
VOUT
OUT
MAX IN(min)
SWdrop
(eq. 5)
@ VF ) IDRMS @ RD
@ ǒ1 * Ǔ
PDloss + IOUT
VIN
www.onsemi.com
13
NCV890200
with:
− I
It can be designed in combination with an inductor to build
an input filter to filter out the ripple current in the source, in
order to reduce EMI conducted emissions.
the average (dc) output current
OUT
− V the forward voltage of the diode
F
− I
the RMS current in the diode:
For example, using a 4.7 mH input capacitor, it is easy to
calculate that an inductor of 200 nH will ensure that the
input filter has a cut−off frequency below 200 kHz (low
enough to attenuate the 2 MHz ripple).
DRMS
2
DIL
2
(
)
1 * D ǒ
IOUT
(eq. 6)
Ǔ
IDRMS
+
)
Ǹ
12
− R the dynamic resistance of the diode (extracted from
D
Error Amplifier and Loop Transfer Function
the V/I curve of the diode in its datasheet).
The error amplifier is a transconductance type amplifier.
The output voltage of the error amplifier controls the peak
inductor current at which the power switch shuts off. The
Current Mode control method employed allows the use of a
simple, type II compensation to optimize the dynamic
response according to system requirements.
Then, knowing the thermal resistance of the package and
the amount of heatsinking on the PCB, the temperature rise
corresponding to this power dissipation can be estimated.
Input capacitor:
The input capacitor must sustain the RMS input ripple
Figure 29 shows the error amplifier with the
compensation components and the voltage feedback divider.
current I
:
INac
DIL
D
(eq. 7)
Ǹ
IINac
+
2
3
VOUT
RFB1
VCOMP
RCOMP
V
FB
V
RO
Cp
RFB2
g
m
* V
CCOMP
Vref
Figure 29. Feedback Compensator Network Model
The transfer function from VOUT to VCOMP is the
product of the feedback voltage divider and the error
amplifier.
1
wz +
(eq. 10)
(eq. 11)
(eq. 12)
RCOMP @ CCOMP
1
wpl +
Ro @ CCOMP
RFB2
RFB1 ) RFB2
Gdivider(s) +
(eq. 8)
(eq. 9)
1
wph +
s
1 )
wz
RCOMP @ Cp
Gerramp(s) + gm @ Ro @
The output resistor Ro of the error amplifier is 1.4 MW and
gm is 1 mA/V. The capacitor Cp is for rejecting noise at high
frequency and is integrated inside the IC with a value of
18 pF.
s
s
wph
ǒ1 ) Ǔǒ1 ) Ǔ
wpl
The power stage transfer function (from Vcomp to output)
is shown below:
s
1 )
Rload
Ri
wz
1
(eq. 13)
@ Fh(s)
Gps(s) +
@
@
Rload@Tsw
s
[
]
1 )
@ Mc @ (1 * D) * 0.5
ǒ1 ) wpǓ
L
1
wz +
(eq. 14)
(eq. 15)
Resr @ Cout
Mc @ (1 * D) * 0.5
L @ Cout @ Fsw
1
wp +
)
Rload @ Cout
www.onsemi.com
14
NCV890200
where
The bode plots of the open loop transfer function will
show the gain and phase margin of the system. The
compensation network is designed to make sure the system
has enough phase margin and bandwidth.
Se
Sn
Mc + 1 )
(eq. 16)
(eq. 17)
Vin * Vout
Sn +
@ Ri
L
Design of the Compensation Network
Ri represents the equivalent sensing resistor which has a
value of 0.183 W, Se is the compensation slope which is
183 kV/S, Sn is the slope of the sensing resistor current
during on time. Fh(s) represents the sampling effect from the
current loop which has two poles at one half of the switching
frequency:
The function of the compensation network is to provide
enough phase margin at crossover frequency to stabilize the
system as well as to provide high gain at low frequency to
eliminate the steady state error of the output voltage. Please
refer to the design spreadsheet www.onsemi.com
NCV890200 page that helps with the calculation.
1
Fh(s) +
(eq. 18)
The design steps will be introduced through an example.
s
s2
1 )
)
wn2
Example:
wn@Qp
wn + p @ Fsw
Qp +
Vin = 15.5 V, Vout = 3.3 V, Rload = 1.65 W, Iout = 2 A, L =
4.7 mH, Cout = 20 mF (Resr = 7 mW)
The reference voltage of the feedback signal is 0.8 V and
to meet the minimum load requirements, select RFB1 =
100 W, RFB2 = 31.6 W.
1
(eq. 19)
[
]
p @ Mc @ (1 * D) * 0.5
The total loop transfer function is the product of power
stage and feedback compensation network.
From the specification, the power stage transfer function can
be plotted as below:
Gloop(s) + Gdivider(s) @ Gerramp(s) @ Gps(s) (eq. 20)
90
180
45
90
180
20 x log Gps f
arg Gps f
x
p
(
( m))
0
0
(m)
⎦ ⎦
⎣
⎣
− 45
− 90
− 180
1⋅ 10
− 90
100
3
4
5
6
1⋅ 10
1⋅ 10
1⋅ 10
f
m
(Hz)
Figure 30. Power Stage Bode Plots
(eq. 21)
The crossover frequency is chosen to be Fc = 70 kHz, the
power stage gain at this frequency is −4 dB (0.634) from
calculation. Then the gain of the feedback compensation
network must be 4 dB. Next is to decide the locations of one
zero and one pole of the compensator. The zero is to provide
phase boost at the crossover frequency and the pole is to
reject the noise of high frequency. In this example, a zero is
placed at 1/10 of the crossover frequency and a pole is placed
at 1/5 of the switching frequency (Fsw = 2 MHz):
2
Fc
Ǹ
1 ) ǒ Ǔ
Fp
Fp @ gm
Vout
RCOMP +
@
@ Ǹ
|
|
(Fp * Fz) @ Gps(Fc) Vref
2
Fz
1 ) ǒ Ǔ
Fc
1
CCOMP +
(eq. 22)
(eq. 23)
2p @ Fz @ RCOMP
Fz = 7000 Hz, Fp = 400000 Hz,
RCOMP, CCOMP and Cp can be calculated from the
following equations:
1
Cp +
2p @ Fp @ RCOMP
Note: there is an 18 pF capacitor at the output of the OTA
integrated in the IC, and if a larger capacitor needs to be
used, subtract this value from the calculated Cp. Figure 31
shows Cp is split into two capacitors. Cint is the 18 pF in the
IC. Cext is the extra capacitor added outside the IC.
www.onsemi.com
15
NCV890200
From the calculation:
RCOMP = 6.6 KW, CCOMP = 3.4 nF, Cp = 48 pF
So the feedback compensation network is as below:
VOUT
RFB1
100 W
VCOMP
V
FB
RCOMP
V
18 pF
30 pF
Cext
6.6 KW
RO
RFB2
31.6 W
g *V
m
Cint
CCOMP
3.4 nF
Vref
0.8 V
Figure 31. Example of the Feedback Compensation Network
Figure 32 shows the bode plot of the OTA compensator
90
180
90
45
180
20 x log Gerr_amp
f
arg Gerr_amp
(
f
x
( m ))
0
0
(m )
⎦ ⎦
⎣
⎣
p
− 45
− 90
− 90
100
− 180
1⋅ 10
3
4
5
6
1⋅ 10
1⋅ 10
1⋅ 10
f
m
(Hz)
Figure 32. Bode Plot of the OTA Compensator
The total loop bode plot is as below:
90
180
45
90
180
20 x log Gloop f
arg Gloop f
‧
(
( m))
0
0
(m)
⎦ ⎦
⎣
⎣
p
− 45
− 90
− 180
− 90
100
3
4
5
6
1⋅ 10
1⋅ 10
m
1⋅ 10
1⋅ 10
f
(Hz)
Figure 33. Bode Plot of the Total Loop
The crossover frequency is at 70 KHz and phase margin is 75 degrees.
www.onsemi.com
16
NCV890200
PCB LAYOUT RECOMMENDATION
♦ Freewheeling diode ³ inductor ³ Output capacitor
³ return through ground
− Minimize the length of high impedance signals, and
route them far away from the power loops:
♦ Feedback trace
As with any switching power supplies, there are some
guidelines to follow to optimize the layout of the printed
circuit board for the NCV890200. However, because of the
high switching frequency extra care has to be taken.
− Minimize the area of the power current loops:
♦ Comp trace
♦ Input capacitor ³ NCV890200 switch ³ Inductor
³ output capacitor ³ return through Ground
ORDERING INFORMATION
†
Device
NCV890200PDR2G
Package
Shipping
SOIC−8 EP
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
17
NCV890200
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE B
2 X
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
0.10
C A-B
D
DETAIL A
D
A
8
EXPOSED
PAD
F
5
5
8
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
G
E1
E
2 X
MILLIMETERS
DIM MIN
MAX
1.75
0.10
1.65
0.51
0.48
0.25
0.23
h
0.10 C D
2 X
A
A1
A2
b
b1
c
1.35
0.00
1.35
0.31
0.28
0.17
0.17
1
e
4
4
1
0.20
C
PIN ONE
LOCATION
BOTTOM VIEW
8 X b
A
A
B
0.25
C A-B D
END VIEW
c
c1
D
TOP VIEW
4.90 BSC
E
E1
e
6.00 BSC
3.90 BSC
1.27 BSC
H
A
0.10
C
A2
L
0.40
1.27
8 X
(b)
b1
L1
F
1.04 REF
2.24
GAUGE
PLANE
0.10
C
3.20
2.51
0.50
8
G
h
1.55
0.25
0
SEATING
PLANE
L
q
0.25
q
_
_
c1
SECTION A−A
(L1)
A1
SIDE VIEW
C
DETAIL A
SOLDERING FOOTPRINT
2.72
0.107
1.52
0.060
Exposed
Pad
4.0
0.155
2.03
0.08
7.0
0.275
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
ON Semiconductor and the
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NCV890200/D
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