NCV7344MW3R2G [ONSEMI]
High Speed Low Power CAN, CAN FD Transceiver;
| 型号： | NCV7344MW3R2G |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Low Power CAN, CAN FD Transceiver 电信 电信集成电路 |
| 文件： | 总12页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7344
High Speed Low Power
CAN, CAN FD Transceiver
Description
The NCV7344 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7344 is an addition to the CAN high−speed transceiver
family complementing NCV734x CAN stand−alone transceivers and
previous generations such as AMIS42665, AMIS3066x, etc.
The NCV7344 guarantees additional timing parameters to ensure
robust communication at data rates beyond 1 Mbps to cope with CAN
flexible data rate requirements (CAN FD). These features make the
NCV7344 an excellent choice for all types of HS−CAN networks, in
nodes that require a low−power mode with wake−up capability via the
CAN bus.
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MARKING
DIAGRAM
1
NV7344−x
ALYW G
G
SOIC−8
D SUFFIX
CASE 751AZ
1
1
Features
1
NV7344−x
ALYWG
G
• Compatible with ISO 11898−2:2016
• Specification for Loop Delay Symmetry up to 5 Mbps
DFN8
MW SUFFIX
CASE 506BW
• V pin on NCV7344−3 Version Allowing Direct Interfacing with
IO
NV7344−x = Specific Device Code
3 V to 5 V Microcontrollers
x = 0 or 3
• Very Low Current Standby Mode with Wake−up via the Bus
A
L
Y
W
G
= Assembly Location
= Wafer Lot
• Low Electromagnetic Emission (EME) and High Electromagnetic
= Year
Immunity
= Work Week
= Pb−Free Package
• Very Low EME without Common−mode (CM) Choke
• No Disturbance of the Bus Lines with an Un−powered Node
(Note: Microdot may be in either location)
• Transmit Data (TxD) Dominant Timeout Function
• Under All Supply Conditions the Chip Behaves Predictably
• Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses
• Thermal Protection
• Bus Pins Short Circuit Proof to Supply Voltage and Ground
• Bus Pins Protected Against Transients in an Automotive
Environment
PIN ASSIGNMENT
TxD
STB
CANH
CANL
NC
GND
V
CC
RxD
(−0)
V
IO (−3)
• These are Pb−free Devices
NCV7344D1x
(Top View)
Quality
• Wettable Flank Package for Enhanced Optical Inspection
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
TxD
GND
STB
CANH
CANL
EP Flag
V
CC
RxD
NC
(−0)
V
IO (−3)
NCV7344MWx
(Top View)
Typical Applications
• Automotive
• Industrial Networks
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
February, 2017 − Rev. 1
NCV7344/D
NCV7344
BLOCK DIAGRAM
VCC
NC
3
5
VCC
NCV7344−0
CANH
CANL
7
Thermal
shutdown
1
TxD
STB
Timer
VCC
6
8
Driver control
Mode &
Wake−up
control
4
2
Wake−up
RxD
COMP
Filter
GND
COMP
Figure 1. NCV7344−0 Block Diagram
VCC
V
IO
3
5
V
IO
NCV7344−3
CANH
CANL
7
Thermal
shutdown
1
TxD
STB
Timer
V
IO
6
8
Mode &
Driver control
Wake−up
control
4
2
Wake−up
RxD
COMP
COMP
Filter
GND
Figure 2. NCV7344−3 Block Diagram
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2
NCV7344
TYPICAL APPLICATION
VBAT
IN
OUT
5V −reg
VCC
NC
5
VCC
3
RLT = 60 W
CANH
STB
8
7
CAN
BUS
Micro−
controller
TxD
RxD
1
4
CANL
RLT = 60 W
6
2
GND
GND
Figure 3. Application Diagram NCV7344−0
VBAT
IN
IN
OUT
5V −reg
OUT
3V −reg
VIO
VCC
5
3
RLT = 60 W
CANH
7
STB
TxD
RxD
8
1
4
CAN
BUS
Micro−
controller
CANL
LT = 60 W
6
R
2
GND
GND
Figure 4. Application Diagram NCV7344−3
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
Name
TxD
Description
Transmit data input; low input Ù dominant driver; internal pull−up current
2
GND
Ground
3
V
CC
Supply voltage
4
RxD
NC
Receive data output; dominant transmitter Ù low output
Not connected. On NCV7344−0 only
Digital Input / Output pins and other functions supply voltage. On NCV7344−3 only
5
5
V
IO
6
7
8
CANL
CANH
STB
Low−level CAN bus line (low in dominant mode)
High−level CAN bus line (high in dominant mode)
Standby mode control input; internal pull−up current
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3
NCV7344
FUNCTIONAL DESCRIPTION
Operating Modes
Overtemperature Detection
NCV7344 provides two modes of operation as illustrated
in Table 2. These modes are selectable through pin STB.
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 170°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
Table 2. OPERATING MODES
Pin STB
Mode
Pin RxD
Low
Normal
Low when bus
dominant
High when bus
recessive
High
Standby
Follows the bus
when wake−up
detected
High when no
wake−up re-
quest detected
TxD Dominant Timeout Function
A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
internal timer value t
, the transmitter is disabled,
dom(TxD)
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are biased to ground and supply current is reduced to a
minimum, typically 10 mA. When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
This TxD dominant timeout time t
the minimum possible bit rate to 12 kbps.
defines
dom(TxD)
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit
to either positive or negative supply voltage, although
power dissipation increases during this fault condition.
Undervoltage on VCC pin prevents the chip sending data
on the bus when there is not enough VCC supply voltage.
After supply is recovered TxD pin must be first released to
high to allow sending dominant bits again. Recovery time
from undervoltage detection is equal to td(stb−nm) time.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 7). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
VCC supply be removed.
a time period of t
, the RxD pin is driven low by the
wake_filt
transceiver (following the bus) to inform the controller of
the wake−up request.
Wake−up
When a valid wake−up pattern (phase in order
dominant – recessive – dominant) is detected during the
standby mode the RxD pin follows the bus. Minimum length
of each phase is t
– see Figure 5.
wake_filt
Pattern must be received within t
to be recognized
wake_to
as valid wake−up otherwise internal logic is reset.
twake_filt
twake_filt
twake_filt
VIO Supply Pin
The V pin (available only on NCV7344−3 version)
should be connected to microcontroller supply pin. By using
IO
CANH
CANL
V
supply pin shared with microcontroller the I/O levels
IO
between microcontroller and transceiver are properly
t
t
dwakedr
< twake_to
dwakerd
adjusted. See Figure 4. Pin V also provides the internal
IO
supply voltage for low−power differential receiver of the
transceiver. This allows detection of wake−up request even
RxDC
Figure 5. NCV7344 Wake−up Behavior
when there is no supply voltage on pin V
.
CC
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4
NCV7344
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (pin 2). Positive
currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current
is flowing out of the pin.
ABSOLUTE MAXIMUM RATINGS
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage V , V
Conditions
Min
−0.3
−42
−42
−42
−0.3
−8
Max
+6
Unit
V
V
SUP
CC
IO
V
CANH
DC voltage at pin CANH
0 < V < 5.25 V; no time limit
+42
+42
+42
+6
V
CC
V
DC voltage at pin CANL
0 < V < 5.25 V; no time limit
V
CANL
CANH−CANL
CC
V
DC voltage between CANH and CANL
DC voltage at pin TxD, RxD, STB
V
V
I/O
V
V
Electrostatic discharge voltage at all pins,
Component HBM
(Note 1)
(Note 2)
(Note 3)
+8
kV
esdHBM
V
Electrostatic discharge voltage at all pins,
Component CDM
−750
−8
+750
+8
V
esdCDM
V
Electrostatic discharge voltage at pins CANH and
CANL, System HBM (Note 4)
kV
esdIEC
V
Voltage transients, pins CANH, CANL. According
test pulses 1
test pulses 2a
test pulses 3a
test pulses 3b
(Note 5)
−100
V
V
schaff
to ISO7637−3, Class C (Note 4)
+75
−150
V
+100
150
V
Latch−up
Static latch−up at all pins
Storage temperature
mA
°C
°C
T
−55
−40
+150
+170
stg
T
J
Maximum junction temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
2. Standardized charged device model ESD pulses when tested according to AEC−Q100−011
3. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF
capacitor through a 330 W resistor referenced to GND.
4. Results were verified by external test house.
5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
Table 4. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
Thermal characteristics, SOIC−8 (Note 6)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 7)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 8)
R
R
131
81
°C/W
°C/W
q
JA
JA
q
Thermal characteristics, DFN8 (Note 6)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 7)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 8)
R
R
125
58
°C/W
°C/W
q
JA
JA
q
6. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
7. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
8. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
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5
NCV7344
ELECTRICAL CHARACTERISTICS
Table 5. ELECTRICAL CHARACTERISTICS
V
= 4.75 V to 5.25 V; V = 2.8 to 5.25 V; T = −40 to +150°C; R = 60 W, C = 100 pF, C not used unless specified otherwise.
CC
IO
J
LT
LT
1
Symbol
SUPPLY (Pin V
Parameter
Conditions
Min
Typ
Max
Unit
)
CC
V
I
Power supply voltage
Supply current
(Note 9)
4.75
20
2
5
45
5
5.25
70
V
mA
mA
mA
V
CC
Dominant; V
= Low
CC
TxD
TxD
Recessive; V
= High
10
I
Supply current in standby mode
Standby undervoltage detection V pin
T ≤ 100°C, (Note 10)
−
10
4
15
CCS
J
V
3.5
2.0
4.3
2.6
UVD(VCC)(stby)
UVD(VCC)(swoff)
CC
V
Switch−off undervoltage detection V pin
2.3
V
CC
V
IO
SUPPLY VOLTAGE (Pin V ) Only for NCV7344−3 version
IO
V
Supply voltage on pin V
2.8
−
−
−
5.5
11
V
IO
IO
I
Supply current on pin V in standby mode
T ≤ 100°C, (Note 10)
mA
mA
mA
IOS
IO
J
I
Supply current on pin V in standby mode
T ≤ 100°C, (Note 10)
J
−
0
4.0
0.9
0.58
2.6
CCS
CC
I
Supply current on pin V during normal mode
Dominant; V
= Low
= Low
0.45
0.32
2.0
0.65
0.43
2.3
IONM
IO
TxD
Recessive; V
TxD
V
Undervoltage detection voltage on V pin
V
UVDVIO
IO
TRANSMITTER DATA INPUT (Pin TxD)
V
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
Output recessive
Output dominant
2.0
−
−
−
−
V
IH
V
0.8
+5
V
IL
I
IH
V
TxD
= V /V
CC IO
−5
0
mA
mA
pF
I
IL
V
TxD
= 0 V
−300
−
−150
5
−75
10
C
(Note 10)
i
TRANSMITTER MODE SELECT (Pin STB)
V
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
Standby mode
Normal mode
2.0
−
−
−
0
−
5
−
V
IH
V
0.8
+1
−1
10
V
IL
I
IH
V
STB
= V /V
CC IO
−1
−15
−
mA
mA
pF
I
IL
V
STB
= 0 V
C
(Note 10)
i
RECEIVER DATA OUTPUT (Pin RxD)
I
High−level output current
Normal mode
= V /V – 0.4 V
−8
−3
−1
mA
mA
OH
V
RxD
CC IO
I
Low−level output current
V
RxD
= 0.4 V
1
6
12
OL
BUS LINES (Pins CANH and CANL)
I
Recessive output current at pins CANH and
CANL
−27 V < V
, V < +32 V;
CANL
−5
−5
−
+5
+5
mA
o(rec)
CANH
Normal mode
I
LI
Input leakage current
0 W < R(V to GND) < 1 MW
0
mA
CC
V
CANL
= V
= 5 V
CANH
V
Recessive output voltage at pin CANH
Recessive output voltage at pin CANL
Recessive output voltage at pin CANH
Recessive output voltage at pin CANL
Differential bus output voltage
Normal mode, V
Normal mode, V
= High
2.0
2.0
2.5
2.5
0
3.0
3.0
0.1
0.1
0.2
V
V
V
V
V
o(rec) (CANH)
TxD
V
= High
o(rec) (CANL)
TxD
V
Standby mode
Standby mode
Standby mode
−0.1
−0.1
−0.2
o(off) (CANH)
V
0
o(off) (CANL)
V
0
o(off (diff)
(V
− V
)
CANH
CANL
V
Dominant output voltage at pin CANH
Dominant output voltage at pin CANL
Differential bus output voltage
V
V
= 0 V; t < t
dom(TxD);
2.75
0.5
3.5
1.5
4.5
2.25
3.0
V
V
V
o(dom) (CANH)
TxD
50 W < R < 65 W
LT
V
= 0 V; t < t
dom(TxD);
o(dom) (CANL)
TxD
50 W < R < 65 W
LT
V
V
= 0 V; dominant;
1.5
2.25
o(dom) (diff)
TxD
(V
− V
)
45 W < R < 65 W
LT
CANH
CANL
9. In the range of 4.5 V to 4.75V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification.
10.Values based on design and characterization, not tested in production
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NCV7344
Table 5. ELECTRICAL CHARACTERISTICS
V
= 4.75 V to 5.25 V; V = 2.8 to 5.25 V; T = −40 to +150°C; R = 60 W, C = 100 pF, C not used unless specified otherwise.
CC
IO
J
LT
LT
1
Symbol
BUS LINES (Pins CANH and CANL)
Differential bus output voltage during
Parameter
Conditions
Min
Typ
Max
Unit
V
R
= 2.24 kW (Note 10)
LT
1.5
−50
0.9
−
0
5.0
+50
1.1
V
o(dom) (diff)_arb
arbitration (V + V
)
CANH
CANL
V
Differential bus output voltage
(V − V
V
= High; recessive; no load
mV
o(rec) (diff)
TxD
)
CANL
CANH
V
Dominant output voltage driver symmetry
(V + V
R
= 60 W; C = 4.7 nF;
1.0
−70
70
−
V
CC
o(dom) (sym)
o(sc) (CANH)
LT
1
)
CANL
TxD = square wave up to 1 MHz
CANH
I
Short circuit output current at pin CANH
V
CANH
= −3 V; V
= Low
−100
−115
−40
115
mA
mA
V
TxD
< +18 V
−3 V < V
CANH
I
Short circuit output current at pin CANL
V
CANL
= 36 V; V
= Low
40
−115
100
115
o(sc) (CANL)
TxD
< +18 V
−3 V < V
CANL
V
Differential receiver threshold voltage in
normal mode
−12 V < V
−12 V < V
< +12 V;
< +12 V
0.5
0.4
15
0.9
1.05
37
i(diff) (th)_NORM
CANL
CANH
V
Differential receiver threshold voltage in
standby mode
−12 V < V
−12 V < V
< +12 V;
< +12 V
−
V
i(diff) (th)_STDBY
CANL
CANH
R
Common−mode input resistance at pin CANH
−2 V < V
< +7 V;
< +7 V
26
26
0
kW
kW
%
i(cm) (CANH)
CANH
CANL
−2 V < V
R
Common−mode input resistance at pin CANL
−2 V < V
< +7 V;
< +7 V
15
37
i(cm) (CANL)
CANH
CANL
−2 V < V
R
Matching between pin CANH and pin CANL
common mode input resistance
V
= V
= +5 V
−1
+1
i(cm) (m)
CANH
CANL
R
Differential input resistance
Input capacitance at pin CANH
Input capacitance at pin CANL
Differential input capacitance
25
−
50
7.5
75
20
20
10
kW
pF
pF
pF
i(diff)
C
V
TxD
V
TxD
V
TxD
= High; (Note 10)
= High; (Note 10)
= High; (Note 10)
i(CANH)
C
−
7.5
i(CANL)
C
−
3.75
i(diff)
TIMING CHARACTERISTICS (see Figures 6 and 8)
t
t
Delay TxD to bus active
Delay TxD to bus inactive
Delay bus active to RxD
Delay bus inactive to RxD
−
−
75
85
−
−
ns
ns
ns
ns
ns
d(TxD−BUSon)
d(TxD−BUSoff)
d(BUSon−RxD)
d(BUSoff−RxD)
t
t
−
24
−
−
32
−
t
Propagation delay TxD to RxD dominant to
recessive transition
50
100
210
pd_dr
t
Propagation delay TxD to RxD recessive to
dominant transition
50
120
210
ns
pd_rd
t
Delay standby mode to normal mode
5
11
−
20
5
ms
ms
ms
d(stb−nm)
t
Filter time for wake−up via bus
0.5
0.5
wake_filt
t
Delay to flag wake event
(recessive to dominant transitions)
Valid bus wake−up event
Valid bus wake−up event
Standby mode
2.6
6
dwakerd
t
Delay to flag wake event
(dominant to recessive transitions)
0.5
2.6
6
ms
dwakedr
t
Bus time for wake−up timeout
TxD dominant time for timeout
Bit time on RxD pin
1
−
−
−
−
10
10
ms
ms
ns
wake_to
t
V
TxD
= Low; Normal mode
1
dom(TxD)
t
t
t
t
= 500 ns
400
120
435
550
220
530
Bit(RxD)
Bit(TxD)
= 200 ns
= 500 ns
ns
Bit(TxD)
Bit(TxD)
t
Bit time on bus (CANH – CANL pin)
ns
Bit(Vi(diff))
−
−
t
= 200 ns
155
210
ns
Bit(TxD)
Receiver timing symmetry
Rec = Bit(RxD) − Bit(Vi(diff))
Dt
Rec
t
t
= 500 ns
= 200 ns
−65
−45
−
−
+40
+15
ns
ns
Bit(TxD)
Dt
t
t
Bit(TxD)
THERMAL SHUTDOWN
Shutdown junction temperature
T
J(sd)
Junction temperature rising
160
180
200
°C
9. In the range of 4.5 V to 4.75V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification.
10.Values based on design and characterization, not tested in production
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NCV7344
MEASUREMENT SETUPS AND DEFINITIONS
0.7·VCC
*
TxD
0.3·VCC
*
0.3·VCC
tpd_rd
*
tbit(TxD)
td(TxD−BUSon)
5·tbit(TxD)
td(BUSon−RxD)
900mV
Vi(diff)= VCANH−VCANL
500mV
tbit(Vi(diff))
td(TxD−BUSoff)
tpd_dr
0.7·VCC
*
RxD
0.3·VCC
*
*On NCV7344−3 V is replaced by V
Edge length below 10 ns
CC
IO
tbit(RxD)
Figure 6. Transceiver Timing Diagram
+5 V
100nF
V
IO
VCC
3
5
CANH
7
TxD
RxD
1
4
1nF
Transient
Generator
1nF
6
CANL
GND
8
2
15pF
STB
Figure 7. Test Circuit for Automotive Transients
+5 V
100 nF
VCC
V
IO
3
5
CANH
7
TxD
1
RLT/2
CLT
100 pF
C1
RxD
4
RLT/2
6
CANL
2x 30 W
8
2
15 pF
STB
GND
Figure 8. Test Circuit for Timing Characteristics
www.onsemi.com
8
NCV7344
Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table
ISO 11898−2:2016 Specification
NCV7344
Datasheet
Parameter
Dominant output characteristics
Notation
Symbol
Single ended voltage on CAN_H
V
V
o(dom)(CANH)
CAN_H
Single ended voltage on CAN_L
V
CAN_L
V
o(dom)(CANL)
Differential voltage on normal bus load
Differential voltage on effective resistance during arbitration
Differential voltage on extended bus load range (optional)
Driver symmetry
V
Diff
V
Diff
V
Diff
V
o(dom)(diff)
V
o(dom)(diff)_arb
V
o(dom)(diff)
Driver symmetry
V
V
SYM
o(dom)(sym)
I
o(SC)(CANH)
Driver output current
Absolute current on CAN_H
I
CAN_H
Absolute current on CAN_L
I
I
o(SC)(CANL)
CAN_L
Receiver output characteristics, bus biasing active
Single ended output voltage on CAN_H
Single ended output voltage on CAN_L
Differential output voltage
V
V
o(rec)(CANH)
CAN_H
V
V
o(rec)(CANL)
CAN_L
V
Diff
V
o(rec)(diff)
Receiver output characteristics, bus biasing inactive
Single ended output voltage on CAN_H
Single ended output voltage on CAN_L
Differential output voltage
V
V
o(off)(CANH)
CAN_H
V
V
o(off)(CANL)
CAN_L
V
Diff
V
o(off)(dif)
Optional transmit dominant timeout
Transmit dominant timeout, long
t
t
T
dom(TxD)
dom
Transmit dominant timeout, short
NA
dom
Static receiver input characteristics, bus biasing active
Recessive state differential input voltage range
Dominant state differential input voltage range
Static receiver input characteristics, bus biasing inactive
Recessive state differential input voltage range
Dominant state differential input voltage range
Receiver input resistance
V
V
V
V
Diff
i(diff)(th)_NORM
Diff
i(diff)(th)_NORM
V
V
V
V
Diff
i(diff)(th)_STDBY
Diff
i(diff)(th)_STDBY
Differential internal resistance
R
R
Diff
i(diff)
R
i(cm)(CANH)
R
Single ended internal resistance
R
CAN_H
R
CAN_L
i(cm)(CANL)
Receiver input resistance matching
Matching a of internal resistance
Implementation loop delay requirement
Loop delay
m
R
i(cm)(m)
R
t
t
Loop
pd_rd
t
pd_dr
Optional implementation data signal timing requirements for use with bit rates above 1 Mbit/s and up to 2 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s
Received recessive bit width @ 2 Mbit/s
t
t
Bit(Vi(diff))
Bit(Bus)
t
t
Bit(RxD)
Bit(RXD)
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9
NCV7344
Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table
Parameter
Notation
Dt
Symbol
Receiver timing symmetry @ 2 Mbit/s
D
tRec
Rec
Optional implementation data signal timing requirements for use with bit rates above 2 Mbit/s and up to 5 Mbit/s
Transmitted recessive bit width @ 5 Mbit/s
Transmitted recessive bit width @ 5 Mbit/s
Received recessive bit width @ 5 Mbit/s
t
t
Bit(Vi(diff))
Bit(Bus)
t
t
Bit(RxD)
Bit(RXD)
Dt
Rec
Dt
Rec
Maximum ratings of V
, V and V
CAN_L Diff
CAN_H
Maximum rating V
V
Diff
V
CANH−CANL
Diff
General maximum rating V
and V
V
V
CANH
CAN_H
CAN_L
CAN_H
V
CAN_L
V
CANL
Optional: Extended maximum rating V
and V
V
NA
CAN_H
CAN_L
CAN_H
V
CAN_L
Maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
I
I
LI
CAN_H
CAN_L
I
Bus biasing control timings
CAN activity filter time, long
t
t
t
wake_filt
Filter
CAN activity filter time, short
NA
Filter
Wake−up timeout, short
t
t
t
wake_to
Wake
Wake
Wake−up timeout, long
t
wake_to
Timeout for bus inactivity (Required for selective wake−up implementation only)
Bus Bias reaction time (Required for selective wake−up implementation only)
t
NA
Silence
t
NA
Bias
DEVICE ORDERING INFORMATION
†
Part Number
Description
Temperature Range
Package
Shipping
NCV7344D10R2G
High Speed Low Power CAN, CANFD
Transceiver
SOIC 150 8 GREEN (Matte
Sn, JEDEC MS−012)
(Pb−Free)
3000 / Tape
& Reel
−40°C to +125°C
NCV7344D13R2G
NCV7344MW0R2G
NCV7344MW3R2G
High Speed Low Power CAN, CANFD
Transceiver with V pin
IO
High Speed Low Power CAN, CANFD
Transceiver
DFN 8
Wettable Flank
(Pb−Free)
3000 / Tape
& Reel
−40°C to +150°C
High Speed Low Power CAN, CANFD
Transceiver with V pin
IO
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
NCV7344
PACKAGE DIMENSIONS
SOIC−8
CASE 751AZ
ISSUE B
NOTES 4&5
0.10 C D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
455CHAMFER
D
h
NOTE 6
D
A
2X
H
8
5
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS
SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES
NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.
5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT
TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER
MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.
6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.
7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.
0.10 C D
NOTES 4&5
E
E1
L2
SEATING
L
C
PLANE
DETAIL A
1
4
0.20 C D
8X b
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
B
M
0.25
C A-B D
NOTE 6
MILLIMETERS
TOP VIEW
NOTES 3&7
DIM MIN
MAX
1.75
0.25
---
DETAIL A
A
A1
A2
b
---
0.10
1.25
0.31
0.10
A2
NOcTE 7
0.10 C
0.51
0.25
c
D
4.90 BSC
A
E
6.00 BSC
3.90 BSC
1.27 BSC
e
END VIEW
SEATING
PLANE
E1
e
C
A1
SIDE VIEW
NOTE 8
h
0.25
0.40
0.41
1.27
L
RECOMMENDED
0.25 BSC
L2
SOLDERING FOOTPRINT*
8X
0.76
8X
1.52
7.00
1
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
NCV7344
PACKAGE DIMENSIONS
DFN8, 3x3, 0.65P
CASE 506BW
ISSUE O
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
MILLIMETERS
PIN ONE
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
REFERENCE
2X
A
EXPOSED Cu
MOLD CMPD
0.10
C
A3
b
0.20 REF
0.25
0.35
D
2X
0.10
C
C
D2 2.30
E
E2 1.55
e
K
L
TOP VIEW
DETAIL B
A
C
DETAIL B
(A3)
OPTIONAL
0.05
CONSTRUCTIONS
L1 0.00
0.05
C
NOTE 4
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
A1
SIDE VIEW
D2
DETAIL A
8X
0.62
2.50
1
4
8X
L
E2
3.30
1.75
8X
K
8
5
1
8X b
08.4X0
e/2
0.10 C A B
0.65
PITCH
e
DIMENSIONS: MILLIMETERS
NOTE 3
C
0.05
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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