NCV7349 [ONSEMI]
High Speed Low Power CAN Transceiver;
| 型号： | NCV7349 |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Low Power CAN Transceiver |
| 文件： | 总12页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7349
High Speed Low Power CAN
Transceiver
Description
The NCV7349 CAN transceiver is the interface between
a controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7349 is a new addition to the CAN high−speed transceiver
family complementing NCV734x CAN family and previous generations
of CAN transceivers such as AMIS42665, AMIS3066x, etc.
Due to the wide common−mode voltage range of the receiver inputs
and other design features, the NCV7349 is able to reach outstanding
levels of electromagnetic susceptibility (EMS). Similarly, very low
electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
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MARKING
DIAGRAM
8
8
NV7349−x
ALYW G
G
1
SOIC−8
CASE 751AZ
1
Features
NV7349−x = Specific Device Code
x = 0 or 3
• Compatible with the ISO 11898−5 Standard
• High Speed (up to 1 Mbps)
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
• V Pin on NCV7349−3 Version Allowing Direct Interfacing with
IO
3 V to 5 V Microcontrollers
• Very Low Current Standby Mode with Wake−up via the Bus
• Low Electromagnetic Emission (EME) and Extremely High
Electromagnetic Immunity
(Note: Microdot may be in either location)
PIN ASSIGNMENT
• Very Low EME without Common−mode (CM) Choke
• No Disturbance of the Bus Lines with an Un−powered Node
• Transmit Data (TxD) Dominant Time−out Function
• Under All Supply Conditions the Chip Behaves Predictably
• Very High ESD Robustness of Bus Pins, >10 kV System ESD Pulses
• Thermal Protection
• Bus Pins Short Circuit Proof to Supply Voltage and Ground
• Bus Pins Protected Against Transients in an Automotive
• These are Pb−Free Devices
8
7
6
5
1
2
3
4
TxD
STB
CANH
CANL
NC
GND
V
CC
RxD
NCV7349D10R2G
(Top View)
Quality
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
8
7
6
5
1
2
3
4
TxD
STB
GND
CANH
CANL
Typical Applications
• Automotive
• Industrial Networks
V
CC
V
IO
RxD
NCV7349D13R2G
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
December, 2014 − Rev. 1
NCV7349/D
NCV7349
Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES
Symbol
Parameter
Power supply voltage
Conditions
Min
Max
Unit
V
CC
(Note 1)
4.75
(4.5)
5.25
(5.5)
V
V
Undervoltage detection voltage on pin Vcc
DC voltage at pin CANH
2
4
V
V
V
V
UV
V
CANH
0 < V < 5.5 V; no time limit
−50
−50
−
+50
+50
+58
CC
V
CANL
DC voltage at pin CANL
0 < V < 5.5 V; no time limit
CC
V
DC voltage at pin CANH and CANL during load
dump condition
0 < V < 5.5 V, less than one second
CANH,Lmax
CC
V
Electrostatic discharge voltage
IEC 61000−4−2 at pins CANH and CANL
−15
1.5
15
3
kV
V
ESD
V
Differential bus output voltage in dominant state
Input common−mode range for comparator
45 W < R < 65 W
O(dif)(bus_dom)
LT
CM−range
Guaranteed differential receiver thresh-
old and leakage current
−35
+35
V
C
Load capacitance on IC outputs
Propagation delay (NCV7349−0 version)
Propagation delay (NCV7349−3 version)
Junction temperature
−
−
15
pF
ns
ns
°C
load
pd0
pd3
t
t
See Figure 7
See Figure 7
245
250
150
−
T
−40
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. In the range of 4.5 V to 4.75 V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification.
BLOCK DIAGRAM
V
CC
V
IO
(*)
3
5
V
V
NCV7349
IO
7
Thermal
CANH
shutdown
1
8
TxD
STB
Timer
IO
6
Mode &
Wake−up
control
Driver control
CANL
4
2
Wake−up
Filter
RxD
COMP
COMP
GND
*On NCV7349−0 version pin 5 is not connected. V supply is provided by V
.
IO
CC
Figure 1. Block Diagram
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2
NCV7349
TYPICAL APPLICATION
VBAT
OUT
IN
5 V − reg
V
CC
V
CC
NC
5
3
R
= 60 W
LT
STB
TxD
RxD
7
8
1
4
CANH
CAN
BUS
Micro−
controller
CANL
6
R
= 60 W
LT
2
GND
GND
Figure 2. Application Diagram, NCV7349−0
VBAT
OUT
IN
IN
5 V − reg
OUT
3 V − reg
V
IO
V
CC
5
3
R
= 60 W
LT
STB
TxD
RxD
7
8
1
4
CANH
CAN
BUS
Micro−
controller
CANL
6
R
= 60 W
LT
2
GND
GND
Figure 3. Application Diagram, NCV7349−3
Table 2. PIN FUNCTION DESCRIPTION
Pin
1
Name
TxD
Description
Transmit data input; low input Ù Driving dominant on bus; internal pull−up current
2
GND
Ground
3
V
CC
Supply voltage
4
RxD
NC
Receive data output; bus in dominant Ù low output
5
5
Not connected. On NCV7349−0 only.
V
IO
Input / Output pins supply voltage. On NCV7349−3 only
6
7
8
CANL
CANH
STB
Low−level CAN bus line (low in dominant mode)
High−level CAN bus line (high in dominant mode)
Standby mode control input; internal pull−up current
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3
NCV7349
FUNCTIONAL DESCRIPTION
Standby Mode
NCV7349 has two versions which differ from each other
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10 mA. When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
only by function of pin 5.
NCV7349−0: Pin 5 is not connected. (see Figure 2)
NCV7349−3: Pin 5 is V pin, which is supply pin for
transceiver digital inputs/output (supplying pins TxD, RxD,
IO
STB) The V pin should be connected to microcontroller
IO
supply pin. By using V
supply pin shared with
IO
microcontroller the I/O levels between microcontroller and
transceiver are properly adjusted. This adjustment allows in
applications with microcontroller supply down to 3 V to
easy communicate with the transceiver. (See Figure 3)
a time period of t
, the RxD pin is driven low by the
wake
transceiver to inform the controller of the wake−up request.
VIO Supply pin
The V pin available only on NCV7349−3 version
should be connected to microcontroller supply pin. By using
IO
Operating Modes
NCV7349 provides two modes of operation as illustrated
in Table 3. These modes are selectable through pin STB.
V
supply pin shared with microcontroller the I/O levels
IO
between microcontroller and transceiver are properly
adjusted. See Figure 3. Pin V on NCV7349−3 does not
IO
Table 3. OPERATING MODES
provide the internal supply voltage for low−power
differential receiver of the transceiver. Detection of
wake−up request is not possible when there is no supply
Pin RxD
Pin
STB
Low
High
Low
High
Mode
Normal
Standby
voltage on pin V
.
Bus dominant
Bus recessive
CC
Wake−up request
detected
No wake−up
request detected
Wake−up
When a valid wake−up (dominant state longer than t
)
wake
is received during the standby mode the RxD pin is driven
low. The wake−up detection is not latched: RxD returns to
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
High state after t
when the bus signal is released back
dwakedr
to recessive – see Figure 4.
>t
Wake
<t
Wake
CANH
CANL
STB
RxD1
t
dwakedr
t
dwakerd
t
Wake(RxD)
normal
standby
time
Figure 4. NCV7349 Wake−up Behavior
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4
NCV7349
Over−temperature Detection
Fail Safe Features
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 170°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
Undervoltage on V pin prevents the chip sending data
CC
on the bus when there is not enough V supply voltage.
CC
After supply is recovered TxD pin must be first released to
high to allow sending dominant bits again. Recovery time
from undervoltage detection is equal to t
time.
d(stb−nm)
V
supply dropping below V
undervoltage
IO
UVDVIO
TxD Dominant Time−out Function
detection level will cause the transmitter to disengage from
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
the bus (no bus loading) until the V voltage recovers
(NCV7349−3 version only).
IO
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 7). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
internal timer value t
, the transmitter is disabled,
dom(TxD)
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
V
IO
supply be removed.
This TxD dominant time−out time (t
minimum possible bit rate to 15 kbps.
) defines the
dom(TxD)
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5
NCV7349
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
ABSOLUTE MAXIMUM RATINGS
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min.
−0.3
−50
Max.
+6
Unit
V
V
SUP
Supply voltage V , V
CC IO
V
CANH
DC voltage at pin CANH
0 < V < 5.5 V; no time limit
+50
+50
6
V
CC
V
CANL
DC voltage at pin CANL
0 < V < 5.5 V; no time limit
−50
V
CC
V
IO
DC voltage at pin TxD, RxD, STB
Electrostatic discharge voltage at all pins
−0.3
V
V
esd
(Note 2)
(Note 3)
−6
500
6
500
kV
V
Electrostatic discharge voltage at CANH and CANL pins
Transient voltage
(Note 4)
(Note 5)
(Note 6)
−10
10
kV
V
V
−150
100
schaff
Latch−up
Static latch−up at all pins
150
mA
°C
°C
°C
T
Storage temperature
−55
−40
−40
+150
+125
+170
stg
T
A
Ambient temperature
T
J
Maximum junction temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
3. Standardized charged device model ESD pulses when tested according to ESD−STM5.3.1−1999.
4. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor
referenced to GND.
5. Pulses 1, 2a, 3a and 3b according to ISO 7637 part 3. Indicative values based on structural similarity to NCV7340 where results were verified
by external test house.
6. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
Table 5. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Free air
Value
125
75
Unit
K/W
K/W
R
Thermal Resistance Junction−to−Air, 1S0P PCB (Note 7)
Thermal Resistance Junction−to−Air, 2S2P PCB (Note 8)
q
q
JA_1
JA_2
R
Free air
7. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage
8. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage
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6
NCV7349
ELECTRICAL CHARACTERISTICS
Table 6. CHARACTERISTICS (V = 4.75 V to 5.25 V; V = 2.8 V to 5.5 V (NCV7349−3 only); T = −40 to +150°C; R = 60 W
CC
IO
J
LT
unless specified otherwise. On chip versions without V pin, reference voltage for all digital inputs and outputs is V instead of V .)
IO
CC
IO
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY (Pin V
)
CC
I
Supply current
Dominant; V
Recessive; V
= 0 V
−
48
6
75
10
mA
CC
TxD
= V
IO
TxD
I
Supply current in standby mode
T ≤ 100°C, (Note 9)
J
−
2
10
3
15
4
mA
CCS
V
Undervoltage detection voltage on V
pin
V
UVDVCC
CC
SUPPLY (pin V ) on NCV7349−3 Version Only
IO
V
Supply voltage on pin V
2.8
−
−
1
5.5
−
V
IO
IO
I
Supply current on pin V in standby
Standby mode
mA
IOS
IO
mode
I
Supply current on pin V in normal
mode
Dominant; V = 0 V
TxD
−
−
−
1
0.2
mA
V
IONM
IO
Recessive; V
= V
TxD
IO
For V ≤ V
IO
CC
V
Undervoltage detection voltage on V
pin
1.3
2.7
UVDVIO
IO
TRANSMITTER DATA INPUT (Pin TxD)
V
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
Output recessive
Output dominant
2.0
−0.3
−5
−
−
V
V
IH
IO
V
+0.8
+5
−
V
IL
I
IH
V
TxD
V
TxD
= V
IO
0
mA
mA
pF
I
IL
= 0 V
−350
−
−200
5
C
(Note 9)
10
i
TRANSMITTER MODE SELECT (Pin STB)
V
High−level input voltage
Low−level input voltage
High−level input current
Standby mode
Normal mode
2.0
−0.3
−5
−
−
V
V
IH
IO
V
+0.8
+5
V
IL
I
IH
V
STB
V
STB
V
STB
= V
IO
0
mA
mA
mA
pF
I
I
Low−level input current, NCV7349−0
Low−level input current, NCV7349−3
Input capacitance
= 0 V
= 0 V
−10
−40
−
−4
−20
5
−1
IL0
IL3
−4
C
(Note 9)
10
i
RECEIVER DATA OUTPUT (Pin RxD)
I
High−level output current
Normal mode, V
0.4 V
= V –
IO
−1
−0.4
6
−0.1
12
mA
OH
RxD
I
Low−level output current
V
RxD
= 0.4 V
1.6
mA
V
OL
V
High−level output voltage,
Standby mode, I
= −100 mA
V
− 1.1
V
− 0.7
V
− 0.4
OH
RxD
CC
CC
CC
Weaker RxD pin in Standby mode is on
NCV7349−0 version only
BUS LINES (Pins CANH and CANL)
Recessive bus voltage on pins CANH
V
V
= V ; no load;
2.0
−100
−2.5
−2.5
2.5
3.0
100
+2.5
+2.5
V
o(reces) (norm)
TxD
IO
and CANL
normal mode
V
Recessive bus voltage on pins CANH
and CANL
V
TxD
= V ; no load;
0
−
−
mV
mA
mA
o(reces) (stby)
IO
standby mode
−35 V < V < +35 V;
CANH
I
Recessive output current at pin CANH
o(reces) (CANH)
0 V < V < 5.25 V
CC
I
Recessive output current at pin CANL
−35 V < V
< +35 V;
o(reces) (CANL)
CANL
0 V < V < 5.25 V
CC
9. Values based on design and characterization, not tested in production
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NCV7349
Table 6. CHARACTERISTICS (V = 4.75 V to 5.25 V; V = 2.8 V to 5.5 V (NCV7349−3 only); T = −40 to +150°C; R = 60 W
CC
IO
J
LT
unless specified otherwise. On chip versions without V pin, reference voltage for all digital inputs and outputs is V instead of V .)
IO
CC
IO
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BUS LINES (Pins CANH and CANL)
I
Input leakage current to pin CANH
Input leakage current to pin CANL
0 W < R(V to GND) < 1 MW
−10
−10
0
0
10
10
mA
mA
LI(CANH)
CC
V
CANL
= V
= 5 V
CANH
I
0 W < R(V to GND) < 1 MW
CC
LI(CANL)
V
V
V
V
= V
= 5 V
CANL
CANH
V
Dominant output voltage at pin CANH
Dominant output voltage at pin CANL
Differential bus output voltage
= 0 V
= 0 V
3.0
0.5
1.5
3.6
1.4
4.25
1.75
3.0
V
V
V
o(dom) (CANH)
TxD
TxD
TxD
V
o(dom) (CANL)
V
= 0 V; dominant;
2.25
o(dif) (bus_dom)
(V
CANH
− V
)
45 W < R < 65 W
CANL
LT
V
Differential bus output voltage
(V − V
V
TxD
= V ; recessive; no load
−120
0
+50
mV
o(dif) (bus_rec)
IO
)
CANL
CANH
I
Short circuit output current at pin CANH
Short circuit output current at pin CANL
V
V
= 0 V; V = 0 V
TxD
−100
45
−70
70
−45
100
0.7
mA
mA
V
o(sc) (CANH)
CANH
I
= 36 V; V
= 0 V
o(sc) (CANL)
CANL
TxD
V
Differential receiver threshold voltage –
Dominant to Recessive (see Figure 6)
−2 V < V
−2 V < V
< +7 V;
< +7 V
0.5
0.6
i(dif)R (th)
CANL
CANH
V
Differential receiver threshold voltage –
Recessive to Dominant (see Figure 6)
−2 V < V
−2 V < V
< +7 V;
< +7 V
0.7
0.4
0.6
0.5
100
0.4
15
0.8
−
0.9
0.8
1
V
V
i(dif)D (th)
CANL
CANH
V
V
Differential receiver threshold voltage –
Dominant to Recessive (see Figure 6)
−35 V < V
−35 V < V
< +35 V;
< +35 V
ihcmR(dif) (th)
CANL
CANH
Differential receiver threshold voltage –
Recessive to Dominant (see Figure 6)
−35 V < V
−35 V < V
< +35 V;
< +35 V
−
V
ihcmD(dif) (th)
CANL
CANH
V
Differential receiver threshold voltage –
Both transitions (see Figure 6)
−12 V < V
−12 V < V
< +12 V;
< +12 V
−
0.9
300
1.15
37
V
ihcmD12(dif) (th)
CANL
CANH
V
Differential receiver input voltage hys-
teresis
−2 V < V
−2 V < V
< +7 V;
< +7 V
200
0.8
26
26
0
mV
V
i(dif) (hys)
CANL
CANH
V
Differential receiver threshold voltage
in standby mode
−12 V < V
−12 V < V
< +12 V;
< +12 V
i(dif)
(th)_STDBY
CANL
CANH
R
Common−mode input resistance at pin
CANH
kW
kW
%
i(cm) (CANH)
R
Common−mode input resistance at pin
CANL
15
37
i(cm) (CANL)
R
Matching between pin CANH and pin
CANL common mode input resistance
V
CANH
= V
CANL
−3
+3
i(cm) (m)
R
Differential input resistance
Input capacitance at pin CANH
Input capacitance at pin CANL
Differential input capacitance
25
−
50
−
75
30
30
10
kW
pF
pF
pF
i(dif)
C
V
TxD
V
TxD
V
TxD
= V ; (Note 9)
IO
i(CANH)
C
= V ; (Note 9)
−
−
i(CANL)
IO
C
= V ; (Note 9)
−
3.75
i(dif)
IO
THERMAL SHUTDOWN
Shutdown junction temperature
TIMING CHARACTERISTICS (see Figure 5 and Figure 8)
T
J(sd)
Junction temperature rising
150
170
185
°C
t
Delay TxD to bus active
C = 100 pF between CANH to
CANL
−
−
50
60
−
−
ns
ns
d(TxD−BUSon)
i
t
Delay TxD to bus inactive
C = 100 pF between CANH to
i
d(TxD−BUSoff)
CANL
t
t
Delay bus active to RxD
Delay bus inactive to RxD
C
C
= 15 pF
= 15 pF
−
−
60
60
−
−
ns
ns
d(BUSon−RxD)
RxD
RxD
d(BUSoff−RxD)
9. Values based on design and characterization, not tested in production
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NCV7349
Table 6. CHARACTERISTICS (V = 4.75 V to 5.25 V; V = 2.8 V to 5.5 V (NCV7349−3 only); T = −40 to +150°C; R = 60 W
CC
IO
J
LT
unless specified otherwise. On chip versions without V pin, reference voltage for all digital inputs and outputs is V instead of V .)
IO
CC
IO
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TIMING CHARACTERISTICS (see Figure 5 and Figure 8)
t
pd
Propagation delay TxD to RxD
(NCV7349−0 version)
C = 100 pF between CANH to
CANL
−
−
125
130
245
250
ns
ns
i
Propagation delay TxD to RxD
(NCV7349−3 version)
C = 100 pF between CANH to
i
CANL
t
Delay standby mode to normal mode
Dominant time for wake−up via bus
5
0.5
1
8
20
5
ms
ms
ms
d(stb−nm)
t
2.5
4.5
wake
t
t
Delay to flag wake event (recessive to
dominant transitions) (See Figure 4)
Valid bus wake−up event,
10
dwakerd
C
= 15 pF
RxD
Delay to flag wake event (dominant to
recessive transitions) (See Figure 4)
Valid bus wake−up event,
= 15 pF
0.5
0.5
1.2
3.3
−
7
−
4
ms
ms
dwakedr
C
RxD
t
Minimum pulse width on RxD
(See Figure 4)
5 ms t
, C
= 15 pF
wake(RxD)
WAKE
RxD
t
TxD dominant time for time−out
V
TxD
= 0 V
2.6
ms
dom(TxD)
9. Values based on design and characterization, not tested in production
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
MEASUREMENT SETUPS AND DEFINITIONS
recessive
TxD
recessive
50%
dominant
50%
CANH
CANL
0.9 V
V
V
=
i(dif)
0.5 V
− V
CANH
CANL
0.7 x V (*)
CC
RxD
0.3 x V (*)
CC
t
t
d(TxD−BUSon)
d(TxD−BUSoff)
t
d(BUSoff−RXD)
t
d(BUSon−RXD)
t
pd
t
pd
*On NCV7349−3 V is replaced by V
CC
IO
Figure 5. Transceiver Timing Diagram
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9
NCV7349
V
RxD
High
Low
Hysteresis
V
0.9
Figure 6. Hysteresis of the Receiver
0.5
i(dif)(hys)
+5 V
100 nF
V
CC
3
CANH
7
5
6
TxD
RxD
1 nF
1
4
Transient
Generator
1 nF
CANL
8
2
GND
STB
15 pF
Figure 7. Test Circuit for Automotive Transients
+5 V
100 nF
TxD
V
CC
3
CANH
7
5
6
1
4
R
LT
C
LT
100 pF
60 W
RxD
CANL
8
2
STB
GND
15 pF
Figure 8. Test Circuit for Timing Characteristics
DEVICE ORDERING INFORMATION
Temperature
Range
†
Part Number
Description
Package
Shipping
NCV7349D10R2G
High Speed Low Power CAN Transceiver
for the Japanese Market
SOIC 150 8 GREEN
(Matte Sn, JEDEC
MS−012)
3000 / Tape &
Reel
−40°C to +125°C
NCV7349D13R2G
High Speed Low Power CAN Transceiver
(Pb−Free)
for the Japanese Market with V pin
IO
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
NCV7349
PACKAGE DIMENSIONS
SOIC 8
CASE 751AZ
ISSUE A
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11
NCV7349
ON Semiconductor and the
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NCV7349/D
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