NCV4269AD250G [ONSEMI]
5.0 V Micropower 150 mA LDO Linear Regulator with DELAY, Adjustable RESET, and Sense Output; 5.0 V微150毫安LDO线性稳压器与延迟,可调复位和检测输出型号: | NCV4269AD250G |
厂家: | ONSEMI |
描述: | 5.0 V Micropower 150 mA LDO Linear Regulator with DELAY, Adjustable RESET, and Sense Output |
文件: | 总17页 (文件大小:207K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCV4269A
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output
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MARKING
The NCV4269A is a 5.0 V precision micropower voltage regulator
with an output current capability of 150 mA.
DIAGRAMS
The output voltage is accurate within 2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 240 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.
8
SO−8
D SUFFIX
CASE 751
4269A5
ALYW
8
1
G
1
8
SO−8
EXPOSED PAD
PD SUFFIX
4269A5
ALYW
G
8
The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
1
CASE 751AC
1
14
SO−14
D SUFFIX
CASE 751A
The reset threshold voltage can be decreased by the connection of an
NCV4269A5G
AWLYWW
external resistor divider to the R
lead. The regulator is protected
ADJ
14
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.
1
1
20
20
SO−20
DW SUFFIX
CASE 751D
NCV4269A5
AWLYYWWG
Features
• 5.0 V 2.0% Output
• Low 240 mA Quiescent Current
1
1
• Active Reset Output Low Down to V = 1.0 V
Q
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
• Adjustable Reset Threshold
• 150 mA Output Current Capability
• Fault Protection
G, G
= Pb Free
♦ +60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
♦ Thermal Overload
• Early Warning through SI/SO Leads
• Internally Fused Leads in SO−14 and SO−20 Packages
• Integrated Pullup Resistor at Logic Outputs (To Use External
Resistors, Select the NCV4279A)
• Very Low Dropout Voltage
• Electrical Parameters Guaranteed Over Entire Temperature Range
• NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
December, 2009 − Rev. 1
NCV4269A/D
NCV4269A
I
Q
Error
Amplifier
Current and
Reference
and Trim
R
SO
Saturation
Control
R
RO
RO
D
or
Reference
SO
R
ADJ
+
−
SI
GND
Figure 1. Block Diagram
PIN CONNECTIONS
1
20
R
SI
ADJ
D
NC
1
14
I
R
SI
ADJ
1
8
NC
GND
GND
GND
GND
NC
Q
D
I
I
Q
GND
GND
GND
GND
GND
RO
GND
GND
GND
Q
SI
SO
RO
GND
GND
GND
GND
R
ADJ
D
NC
NC
RO
SO
SO
SO−8
SO−14
SO−20L
PACKAGE PIN DESCRIPTION
Package Pin Number
Pin
Symbol
SO−8 SO−8 EP
SO−14
SO−20L
Function
Reset Threshold Adjust; if not used to connect to GND.
3
4
5
3
4
5
1
2
1
2
R
ADJ
D
Reset Delay; To Set Time Delay, Connect to GND with Capacitor
Ground
3, 4, 5, 6,
10, 11, 12
4, 5, 6, 7, 14,
15, 16, 17
GND
−
−
−
3, 8, 9, 13, 18
10
NC
RO
No connection to these pins from the IC.
6
6
7
Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor
to Q. Leave Open if Not Used.
7
7
8
11
SO
Sense Output; This Open−Collector Output is Internally Pulled Up by
20 kW pullup resistor to Q. If not used, keep open.
8
1
2
−
8
1
9
13
14
−
12
19
20
−
Q
I
5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.
Input; Connect to GND Directly at the IC with a Ceramic Capacitor.
Sense Input; If not used, Connect to Q.
2
SI
EPAD
EPAD
Connect to ground potential or leave unconnected
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NCV4269A
MAXIMUM RATINGS (T = −40°C to 150°C)
J
Parameter
Symbol
Min
Max
Unit
Input to Regulator
V
I
−40
45
V
I
I
Internally Limited Internally Limited
Input Transient to Regulator
Sense Input
V
−
60
V
I
V
−40
−1
45
1
V
mA
SI
SI
I
Reset Threshold Adjust
Reset Delay
V
−0.3
−10
7
V
RADJ
RADJ
I
10
mA
V
−0.3
7
V
D
I
Internally Limited Internally Limited
D
Ground
I
50
−
mA
V
q
Reset Output
V
RO
RO
−0.3
7
I
Internally Limited Internally Limited
Sense Output
V
−0.3
7
V
SO
SO
I
Internally Limited Internally Limited
Regulated Output
V
Q
−0.5
−10
7.0
−
V
mA
Q
I
Junction Temperature
Storage Temperature
T
STG
−
−50
150
150
°C
°C
J
T
Input Voltage Operating Range
Junction Temperature Operating Range
V
J
−
−40
45
150
V
°C
I
T
LEAD TEMPERATURE SOLDERING AND MSL
Parameter
Symbol
MSL
Value
MSL, 20−Lead LS Temperature 265°C Peak (Note 3)
3
1
2
MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 3)
MSL, 8−Lead EP, LS Temperature 260°C
MSL
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 4.0 kV per AEC−Q100−002.
Machine Model (MM) ≤ 200 V per AEC−Q100−003.
2. Latchup Current Maximum Rating: ≤ 150 mA per AEC−Q100−004.
3. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.
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3
NCV4269A
THERMAL CHARACTERISTICS
Characteristic
Test Conditions (Typical Values)
Unit
SO−8 Package (Note 4)
Junction−to−Pin 4 ( Y − JL4, Y
)
53.8
°C/W
°C/W
L4
Junction−to−Ambient Thermal Resistance (R , q
)
)
170.9
q
JA JA
SO−8 EP Package (Note 4)
Junction−to−Pin 8 ( Y − JL8, Y
)
23.7
71.4
7.7
°C/W
°C/W
°C/W
L8
Junction−to−Ambient Thermal Resistance (R , q
q
JA JA
Junction−to−Pad ( Y − JPad)
SO−14 Package (Note 4)
Junction−to−Pin 4 ( Y − JL4, Y
)
18.4
°C/W
°C/W
L4
Junction−to−Ambient Thermal Resistance (R , q
)
)
111.6
q
JA JA
SO−20 Package (Note 4)
Junction−to−Pin 4 ( Y − JL4, Y
)
21.8
95.3
°C/W
°C/W
L4
Junction−to−Ambient Thermal Resistance (R , q
q
JA JA
2
4. 2 oz copper, 50 mm copper area, 1.5 mm thick FR4
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NCV4269A
ELECTRICAL CHARACTERISTICS (T = −40°C ≤ T ≤ 125°C, V = 13.5 V unless otherwise specified)
J
J
I
Characteristic
REGULATOR
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
Current Limit
V
1 mA v I v 100 mA 6 V v V v 16 V
4.90
150
−
5.00
200
190
250
2.0
5.10
500
250
450
3.0
0.5
20
V
Q
Q
I
I
Q
−
mA
mA
mA
mA
V
Current Consumption; I = I – I
I
I
= 1 mA, RO, SO High
= 10 mA, RO, SO High
= 50 mA, RO, SO High
q
I
Q
Q
Q
q
q
q
Q
Current Consumption; I = I – I
I
I
I
I
−
q
I
Q
Current Consumption; I = I – I
−
q
I
Q
Dropout Voltage
Load Regulation
Line Regulation
V
dr
V = 5 V, I = 100 mA
−
0.25
10
I
Q
DV
DV
I
Q
= 5 mA to 100 mA
−
mV
mV
Q
V = 6 V to 26 V I = 1 mA
−
10
30
Q
I
Q
RESET GENERATOR
Reset Switching Threshold
V
−
4.50
1.26
10
−
4.65
1.35
20
4.80
1.44
40
V
V
RT
Reset Adjust Switching Threshold
Reset Pullup Resistance
Reset Output Saturation Voltage
Upper Delay Switching Threshold
Lower Delay Switching Threshold
Saturation Voltage on Delay Capacitor
Charge Current
V
V
> 3.5 V
RADJ,TH
Q
R
−
kW
V
SO,INT
RO,SAT
V
V
Q
< V , R
0.1
1.8
0.45
−
0.4
2.2
0.60
0.1
9.5
−
RT RO, INT
V
UD
−
1.4
0.3
−
V
V
−
V
LD
V
D,SAT
V
< V
RT
V
Q
I
V
= 1 V
3.0
17
−
6.5
28
mA
ms
ms
D,C
D
Delay Time L ³ H
t
C
C
= 100 nF
= 100 nF
d
D
D
Delay Time H ³ L
t
3.15
−
RR
INPUT VOLTAGE SENSE
Sense Threshold High
V
−
−
1.24
1.16
−
1.31
1.20
0.1
1.38
1.28
0.4
V
V
SI,High
Sense Threshold Low
V
SI,Low
Sense Output Saturation Voltage
Sense Resistor Pullup
V
V
SI
< 1.20 V; V > 3 V; R
V
SO,Low
Q
SO
R
−
−
10
20
40
kW
mA
SO,INT
Sense Input Current
I
SI
−1.0
0.1
1.0
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5
NCV4269A
I
I
I
Q
I
Q
C
I
C
Q
22 mF
R
1000 mF
ADJ1
470 nF
I
SI
I
RADJ
SI
D
RADJ
V
Q
GND
RO
SO
V
I
I
D
I
q
V
RO
V
SO
V
SI
V
RADJ
V
D
C
R
D
ADJ2
100 nF
Figure 2. Measuring Circuit
V
I
t
t
< t
RR
V
Q
V
RT
dV
dt
I
C
D
D
+
V
D
V
UD
V
LD
t
t
t
d
RR
V
RO
V
RO,SAT
t
Power−on−Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Overload
at Output
Figure 3. Reset Timing Diagram
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NCV4269A
Sense Input Voltage
V
SI,High
V
SI,Low
t
Sense Output Voltage
High
Low
t
Figure 4. Sense Timing Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
16
3.2
V = 13.5 V
V = 13.5 V
I
14
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
I
V
D
= 1.0 V
12
10
8
V
UD
6
4
V
LD
2
0
−40
0
40
80
120
160
−40
0
40
80
120
160
T , (°C)
J
T , (°C)
J
Figure 5. Charge Current ID,C vs. Temperature TJ
Figure 6. Switching Voltage VUD and VLD vs.
Temperature TJ
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NCV4269A
TYPICAL PERFORMANCE CHARACTERISTICS
500
400
300
200
100
0
1.7
1.6
1.5
1.4
T = 125°C
J
T = 25°C
J
1.3
1.2
1.1
1.0
0.9
T = −40°C
J
−40
0
30
60
90
I , (mA)
120
150
180
0
40
80
120
160
T , (°C)
J
Q
Figure 8. Reset Adjust Switching Threshold,
RADJ,TH vs. Temperature TJ
Figure 7. Drop Voltage Vdr vs. Output Current IQ
V
35
30
25
20
15
10
5
12
10
8
6
R = 50 W
L
R = 33 W
L
R = 100 W
L
4
R = 200 W
L
R = 50 W
L
2
0
0
0
0
10
20
30
40
50
2
4
6
8
10
V , (V)
I
V , (V)
I
Figure 10. Output Voltage VQ vs. Input Voltage VI
Figure 9. Current Consumption Iq vs. Input
Voltage VI
1.6
1.5
1.4
1.3
1.2
1.1
1.0
5.2
5.1
5.0
4.9
4.8
4.7
4.6
V = 13.5 V
I
V = 13.5 V
I
V
SI, High
V
SI, Low
−40
0
40
80
120
160
−40
0
40
80
120
160
T , (°C)
J
T , (°C)
J
Figure 11. Sense Threshold VSI vs. Temperature TJ
Figure 12. Output Voltage VQ vs. Temperature TJ
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NCV4269A
TYPICAL PERFORMANCE CHARACTERISTICS
350
300
250
200
150
100
50
12
V = 13.5 V
T = 25°C
J
I
10
8
T = 25°C
J
T = 125°C
J
6
4
2
0
0
0
10
20
30
40
50
0
20
40
60
I , (mA)
80
100
120
V , (V)
I
Q
Figure 13. Output Current Limit IQ vs. Input
Voltage VI
Figure 14. Current Consumption Iq vs. Output
Current IQ
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
7
6
5
4
3
2
1
0
T = 125°C
J
V = 13.5 V
T = 25°C
J
I
I
= 100 mA
Q
I
I
= 50 mA
= 10 mA
Q
Q
0
10
20
30
40
50
6
8
10
12 14
16
18
20 22
24 26
V , (V)
I
I , (mA)
Q
Figure 15. Current Consumption Iq vs.
Output Current IQ
Figure 16. Quiescent Current Iq vs.
Input Voltage VI
250
200
150
100
50
100
10
1
T = 25°C
J
Unstable Region
I
= 100 mA
Q
Stable Region for
2.2 mF to 10 mF
0.1
6
8
10
12 14
16 18
20 22
24 26
0
25
50
75
100
125
150
V , (V)
I
OUTPUT CURRENT IN MILLIAMPS
Figure 18. Output Stability, Capacitance ESR
vs. Output Load Current
Figure 17. Quiescent Current Iq vs. Input Voltage VI
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NCV4269A
TYPICAL THERMAL CHARACTERISTICS
200
180
160
140
120
100
80
60
40
20
0
0
100
200
300
400
500
600
700
2
COPPER HEAT−SPREADER AREA (mm )
SO−8 Std Package NCV4269A, 1.0 oz
SO−8 Std Package NCV4269A, 2.0 oz
SO−14 w/6 Thermal Leads NCV4269A, 1.0 oz
SO−14 w/6 Thermal Leads NCV4269A, 2.0 oz
SO−20 w/8 Thermal Leads NCV4269A, 1.0 oz
SO−20 w/8 Thermal Leads NCV4269A, 2.0 oz
Figure 19. Junction−to−Ambient Thermal Resistance (qJA) vs. Heat Spreader Area
1000
100
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (s)
2
Single Pulse (SO−8 Std Package) PCB = 50 mm , 2.0 oz
Single Pulse (SO−8 EP Package)
2
Single Pulse (SO−14 w/6 Thermal Leads) PCB = 50 mm , 2.0 oz
2
Single Pulse (SO−20 w/8 Thermal Leads) PCB = 50 mm , 2.0 oz
YLA (SO−8)
YLA (SO−14)
YLA (SO−20)
Figure 20. R(t) vs. Pulse Time
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NCV4269A
APPLICATION DESCRIPTION
OUTPUT REGULATOR
If the reset adjust option is not needed, the R
pin
ADJ
The output is controlled by a precision trimmed reference.
The PNP output has base drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor C ) on the reset output lead RO. The delay lead D
D
provides charge current I
(typically 6.5 mA) to the
D,C
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
external delay capacitor C during the following times:
D
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
generated as the IC powers up. After the output voltage V
Q
increases above the reset threshold voltage V , the delay
RT
timer D is started. When the voltage on the delay timer V
D
passes V , the reset signal RO goes high. A discharge of
discharge when the regulation (V , reset
UD
RT
the delay timer V is started when V drops and stays below
threshold voltage) has been violated. When the
D
Q
the reset threshold voltage V . When the voltage of the
delay capacitor discharges to V , the reset signal
RT
LD
delay timer V drops below the lower threshold voltage V
RO pulls low.
D
LD
the reset output voltage V is brought low to reset the
RO
SETTING THE DELAY TIME
processor.
The delay time is set by the delay capacitor C and the
D
The reset output RO is an open collector NPN transistor
with an internal 20 kW pullup resistor connected to the
output Q, controlled by a low voltage detection circuit. The
circuit is functionally independent of the rest of the IC,
charge current I . The time is measured by the delay
D
capacitor voltage charging from the low level of V
to
DSAT
the higher level V . The time delay follows the equation:
UD
+ [C (V * V
UD
(eq. 2)
t
d
)]ńI
D, SAT D, C
D
thereby guaranteeing that RO is valid for V as low as 1.0 V.
Q
Example:
Using C = 100 nF.
Use the typical value for V
Use the typical value for V = 1.8 V.
Use the typical value for Delay Charge Current I = 6.5 mA.
RESET ADJUST (RADJ
The reset threshold V can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin R
)
D
RT
= 0.1 V.
D,SAT
UD
,
ADJ
D
as shown in Figure 21. The resistor divider keeps the voltage
above the V (typical 1.35 V) for the desired input
(eq. 3)
t
d
+ [100 nF(1.8 * 0.1 V)]ń6.5 mA + 26.2 ms
RADJ,TH
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
V
RT
+ V
@ (R
) R
)ńR
ADJ2 ADJ2
(eq. 1)
RADJ, TH
ADJ1
V
BAT
I
Q
V
DD
C **
10 mF
(2.2 mF)
R
R
Q
ADJ1
ADJ2
C *
0.1 mF
I
R
ADJ
NCV4269A
R
R
SI1
SI2
D
SI
C
D
RO
I/O
SO
I/O
GND
*C required if regulator is located far from the power supply filter.
I
** C − minimum cap required for stability is 2.2 mF while higher over/under−shoots may be
Q
expected. Cap must operate at minimum temperature expected.
Figure 21. Application Diagram
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NCV4269A
SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE
MONITOR
(−25°C to −40°C), both the value and ESR of the capacitor
will vary considerably. The capacitor manufacturer’s data
sheet usually provides this information.
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal
(Figure 4). The output is from an open collector driver with
an internal 20 kW pull up resistor to output Q. The reset signal
typically turns the microprocessor off instantaneously. This
can cause unpredictable results with the microprocessor. The
signal received from the SO pin will allow the microprocessor
time to complete its present task before shutting down. This
function is performed by a comparator referenced to the band
gap voltage. The actual trip point can be programmed
externally using a resistor divider to the input monitor SI
The 10 mF output capacitor C shown in Figure 21 should
Q
work for most applications; however, it is not necessarily the
optimized solution. Stability is guaranteed at C is min
Q
2.2 mF and max ESR is 10 W. There is no min ESR limit
which was proved with MURATA’s ceramic caps
GRM31MR71A225KA01 (2.2 mF, 10 V, X7R, 1206) and
GRM31CR71A106KA01 (10 mF, 10 V, X7R, 1206) directly
soldered between output and ground pins.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 21) is:
(Figure 21). The values for R and R are selected for a
SI1
SI2
typical threshold of 1.20 V on the SI Pin.
SIGNAL OUTPUT
Figure 22 shows the SO Monitor timing waveforms as a
result of the circuit depicted in Figure 21. As the output
P
+ [V
I(max)
* V
]I
) V
I
(eq. 4)
D(max)
Q(min) Q(max)
I(max) q
where:
V
V
I
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the application,
I(max)
Q(min)
Q(max)
voltage (V ) falls, the monitor threshold (V
), is
Q
SI,Low
crossed. This causes the voltage on the SO output to go low
sending a warning signal to the microprocessor that a reset
and I is the quiescent current the regulator consumes at
q
signal may occur in a short period of time. T
is the
WARNING
I
.
Q(max)
time the microprocessor has to complete the function it is
currently working on and get ready for the reset
shutdown signal. When the voltage on the SO goes low and
the RO stays high the current consumption is typically
560 mA at 1 mA load current.
Once the value of P
is known, the maximum
D(max)
permissible value of R
can be calculated:
qJA
= (150°C – T ) / P
D
R
(eq. 5)
q
JA
A
The value of R
can then be compared with those in the
qJA
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
V
Q
R
qJA
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required. The current
SI
V
flow
and
voltages
are
shown
in
the
SI,Low
Measurement Circuit Diagram.
HEATSINKS
V
RO
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
SO
T
WARNING
determine the value of R
:
qJA
Figure 22. SO Warning Waveform Time Diagram
R
+ R
) R
) R
qCS qSA
(eq. 6)
qJA
qJC
where:
STABILITY CONSIDERATIONS
R
qJC
R
qCS
R
qSA
= the junction−to−case thermal resistance,
= the case−to−heat sink thermal resistance, and
= the heat sink−to−ambient thermal resistance.
The input capacitor C in Figure 21 is necessary for
I
compensating input line reactance. Possible oscillations caused
by input inductance and input capacitance can be damped by
using a resistor of approximately 1.0 W in series with C
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. The
aluminum electrolytic capacitor is the least expensive
solution, but, if the circuit operates at low temperatures
R
qJC
appears in the package section of the data sheet. Like
I.
R
qJA
, it too is a function of package type. R
and R
are
qCS
qSA
functions of the package type, heatsink and the interface
between them. These values appear in data sheets of
heatsink manufacturers. Thermal, mounting, and
heatsinking considerations are discussed in the
ON Semiconductor application note AN1040/D, available
on the ON Semiconductor website.
http://onsemi.com
12
NCV4269A
ORDERING INFORMATION
Device
†
Output Voltage
Package
Shipping
NCV4269AD150G
SO−8
98 Units/Rail
2500 Tape & Reel
98 Units/Rail
(Pb−Free)
NCV4269AD150R2G
NCV4269APD50G
NCV4269APD50R2G
NCV4269AD250G
SO−8
(Pb−Free)
SO−8 EP
(Pb−Free)
SO−8 EP
(Pb−Free)
2500 Tape & Reel
55 Units/Rail
5.0 V
SO−14
(Pb−Free)
NCV4269AD250R2G
NCV4269ADW50G
NCV4269ADW50R2G
SO−14
2500 Tape & Reel
38 Units/Rail
(Pb−Free)
SO−20L
(Pb−Free)
SO−20L
(Pb−Free)
1000 Tape & Reel
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
13
NCV4269A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
14
NCV4269A
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC−01
ISSUE B
2 X
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
0.10
C A-B
D
DETAIL A
D
A
8
EXPOSED
PAD
F
5
5
8
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
G
E1
E
2 X
MILLIMETERS
DIM MIN
MAX
1.75
0.10
1.65
0.51
0.48
0.25
0.23
h
0.10 C D
2 X
A
A1
A2
b
b1
c
1.35
0.00
1.35
0.31
0.28
0.17
0.17
1
e
4
4
1
0.20
C
PIN ONE
LOCATION
BOTTOM VIEW
8 X b
0.25 C A-B D
A
A
B
END VIEW
c
c1
D
TOP VIEW
4.90 BSC
E
E1
e
6.00 BSC
3.90 BSC
1.27 BSC
H
A
0.10
C
A2
L
L1
F
0.40
1.04 REF
2.24
1.27
8 X
(b)
b1
GAUGE
PLANE
0.10
C
3.20
2.51
0.50
8
G
h
1.55
0.25
0
SEATING
PLANE
L
q
0.25
q
_
_
c1
SECTION A−A
(L1)
DETAIL A
A1
SIDE VIEW
C
SOLDERING FOOTPRINT*
2.72
0.107
1.52
0.060
Exposed
Pad
4.0
0.155
2.03
0.08
7.0
0.275
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
NCV4269A
PACKAGE DIMENSIONS
SO−14
CASE 751A−03
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
8.75
4.00
1.75
0.49
1.25
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
_
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
0.337
0.150
0.054
0.014
0.016
−T−
SEATING
PLANE
J
M
G
J
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T B
A
K
M
P
R
_
_
_
_
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
http://onsemi.com
16
NCV4269A
PACKAGE DIMENSIONS
SO−20 WB
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
C
T
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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