NCP81074BMNTBG [ONSEMI]
High Speed Low-Side MOSFET Driver;
| 型号： | NCP81074BMNTBG |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Low-Side MOSFET Driver 栅 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总12页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81074A, NCP81074B
Single Channel 10A High
Speed Low-Side MOSFET
Driver
The NCP81074 is a single channel, low−side MOSFET driver. It is
capable of providing large peak currents into capacitive loads. This
driver can deliver a 7 A peak current at the Miller plateau region to
help reduce the Miller effect during MOSFETs switching transitions.
It exhibits a split output configuration allowing the user to control the
turn on and turn off slew rates. This part is available in SOIC−8 and
DFN8 2x2 mm packages.
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MARKING
DIAGRAMS
1
DFN8
MN SUFFIX
CASE 506AA
XXMG
G
Features
1
• High Current Drive Capability 10 A
• TTL/CMOS Compatible Inputs Independent of Supply Voltage
• High Reverse Current Capability (10 A) Peak
XX = Specific Device Code
M
= Date Code
G
= Pb−Free Device
(Note: Microdot may be in either location)
• 4 ns Typical Rise and 4 ns Typical Fall Times with 1.8 nF Load
• Fast Propagation Delay Times of 15 ns with Input Falling and 15 ns
with Input Rising
8
XXXXXX
AYWW
SOIC−8
CASE 751
8
• Input Voltage Range from 4.5 V to 20 V
1
G
• Split Output Configuration
1
• Dual Input Design Offering Drive Flexibility
XXXXXX = Specific Device Code
A
Y
WW
G
= Assembly Location
= Year
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
= Work Week
= Pb−Free Package
Applications
• Server Power
• Telecommunication, Datacenter Power
• Synchronous Rectifier
• Switch Mode Power Supply
• DC/DC Converter
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
• Power Factor Correction
• Motor Drive
• Renewable Energy, Solar Inverter
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
November, 2015 − Rev. 3
NCP81074/D
NCP81074A, NCP81074B
ORDERING INFORMATION
Temperature
Range (5C)
†
Device
Marking
Input Type
Package Type
Shipping
NCP81074AMNTBG
−40 to +140
CL
Fixed Digital Threshold
DFN8 2x2
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
NCP81074BMNTBG
NCP81074ADR2G
NCP81074BDR2G
−40 to +140
−40 to +140
−40 to +140
CM
VDD Based Threshold
Fixed Digital Threshold
VDD Based Threshold
DFN8 2x2
(Pb−Free)
NCP81074A
NCP81074B
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
BLOCK DIAGRAM
Figure 1. NCP81074 Block Diagram
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2
NCP81074A, NCP81074B
PIN DESCRIPTION
Pin No.
Symbol
Description
1
IN+
Non−Inverting Input which has logic compatible threshold and hysteresis. If not used, this pin should be
connected to either VDD or GND. It should not be left unconnected.
2
3
4
5
6
7
8
GND
GND
OUTL
OUTH
VDD
Common ground. This ground should be connected very closely to the source of the power MOSFET.
Common ground. This ground should be connected very closely to the source of the power MOSFET.
Sink pin. Connect to Gate of MOSFET.
Source Pin. Connect to Gate of MOSFET.
Power Supply Input Pin.
VDD
Power supply Input Pin.
Inverting Input which has logic compatible threshold and hysteresis. If not used, this pin should be connect-
ed to either VDD or GND. It should not be left unconnected
IN−
Figure 2. TYPICAL APPLICATION CIRCUIT
ABSOLUTE MAXIMUM RATINGS
Value
Min
Max
Parameter
Unit
Supply Voltage
VDD
−0.3
24
V
Output Current (DC)
Iout_dc
0.6
10
A
A
Reverse Current (Pulse<1 ms)
Output Current (Pulse<0.5 ms)
Input Voltage
10
24
Iout_pulse
IN+, IN−
A
−6
V
Output Voltages
OUTH, OUTL
OUTH, OUTL
−0.3
−3.0
−40
−65
VDD + 0.3
VDD + 3.0
150
V
Output Voltages (Pulse<0.5 ms)
Junction Operation Temperature
Storage Temperature
V
T
J
°C
T
stg
160
Electrostatic Discharge
Human body model, HBM
Charge device model, CDM
4000
1000
500
V
OUT Latch−up Protection
mA
Moisture Sensitivity Level (MSL)
MSL1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCP81074A, NCP81074B
RECOMMENDED OPERATING CONDITIONS
Parameter
Rating
Unit
VDD supply Voltage
4.5 to 20
V
IN+, IN− input voltages
Junction Temperature Range
−5 to 20
V
−40 to +140
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 1. THERMAL INFORMATION
Package
DFN−8 2x2
SOIC−8
Theta JA (5C/W)
Theta JC (5C/W)
80.3
11.9
115
50
Table 2. ELECTRICAL CHARACTERISTICS (Note 1) (Typical values: VDD =12V, 1uF from VDD to GND,TA = TJ =
−405C to 1405C, typical at TAMB = 255C, unless otherwise specified)
Parameter
SYMBOL
Test Conditions
MIN
TYP
MAX
Unit
SUPPLY VOLTAGE
VDD Under Voltage Lockout (rising)
VDD Under Voltage Lockout (Falling)
VDD Under Voltage Lockout (hysteresis)
Operating Current (no switching)
V
VDD rising
VDD falling
3.7
3.4
3.9
3.6
300
1.2
10
4.1
3.8
V
V
CCR
V
CCF
CCH
V
mV
mA
ms
I
2
DD
VDD Under Voltage Lockout to Output
Delay (Note 1)
VDD rising
INPUTS
NCP81074A High Threshold
NCP81074A Low Threshold
V
Input rising from logic low
Input falling from logic high
1.9
1.1
2.1
1.3
2.3
1.5
V
V
thH
V
thL
Input Signal
Hysteresis
VIN_HYS
0.8
V
V
V
Input rising from logic low
(VDD = 8 V to 12 V)
VDD
−3.5
VDD
−3.1
VDD
−2.7
NCP81074B High Threshold
NCP81074B Low Threshold
V
thH
Input falling from logic high
(VDD = 8 V to 12 V)
GND
+2.6
GND
+2.9
GND
+3.2
V
thL
IN− Pull−up Resistor
IN+ Pull−Down Resistor
OUTPUTS
R
R
200
200
kW
kW
in−
in+
Output Resistance High
Output Resistance Low
R
IOUT = −10 mA
IOUT = +10 mA
0.4
0.4
0.8
0.8
W
W
OH
R
OL
OUT = GND
200 ns Pulse
(2)
Peak Source Current
I
I
10
7
A
A
A
A
Source
OUT = 5.0 V
200 ns Pulse
(2)
Miller Plateau Source Current
Source
OUT = VDD
200 ns Pulse
(2)
Peak Sink Current
I
I
10
7
Sink
OUT = 5.0 V
200 ns Pulse
(2)
Miller Plateau Sink Current
Sink
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4
NCP81074A, NCP81074B
Table 2. ELECTRICAL CHARACTERISTICS (Note 1) (Typical values: VDD =12V, 1uF from VDD to GND,TA = TJ =
−405C to 1405C, typical at TAMB = 255C, unless otherwise specified)
Parameter
SYMBOL
Test Conditions
MIN
TYP
MAX
Unit
SWITCHING CHARACTERISTICS
Propagation Delay Time Low to High, IN
Rising (IN to OUT) (Note 2)
t
t
C
C
= 1.8 nF
= 1.8 nF
15
15
27
27
ns
ns
d1
Load
Load
Propagation Delay Time High to Low, IN
Falling (IN to OUT) (Note 2)
d2
Rise Time (Note 2)
Fall Time (Note 2)
t
C
C
= 1.8 nF
= 1.8 nF
4
4
7
7
ns
ns
r
Load
Load
t
f
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. All Limits are 100% tested at TAMB = 25 °C and guaranteed across temperature by design and statistical analysis.
2. Guaranteed by characterization. *See timing Waveforms.
Table 3. LOGIC TRUTH TABLE
OUT
(OUTH & OUTL CONNECTED
TOGETHER)
IN+
L
IN−
L
OUTH
HIGH−Z
HIGH−Z
H
OUTL
L
L
L
L
H
L
HIGH−Z
L
H
L
H
L
H
H
HIGH−Z
Figure 3. Non−inverting Input Driver Operation
Figure 4. Inverting Input Driver Operation
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5
NCP81074A, NCP81074B
TYPICAL CHARACTERISTICS
250
200
150
100
100
10 nF
10 nF
90
80
70
60
4.7 nF
4.7 nF
50
40
2.2 nF
30
2.2 nF
1 nF
470 pF
50
0
20
10
1 nF
470 pF
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
SWITCHING FREQUENCY (kHz)
0
200 400 600 800 1000 1200 1400 16001800 2000
SWITCHING FREQUENCY (kHz)
Figure 5. Supply Current vs. Switching
Frequency, VDD = 12 V
Figure 6. Supply Current vs. Switching
Frequency, VDD = 4.5 V
5.00
4.75
4.50
4.25
4.00
3.75
3.50
8.0
7.5
20 V
20 V
7.0
6.5
6.0
5.5
5.0
5 V
15 V
10 V
15 V
5 V
10 V
3.25
3.00
4.5
4.0
−60 −40 −20
0
20 40 60 80 100 120 140 160
−60 −40 −20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Fall Time vs. Temperature
Figure 8. Rise Time vs. Temperature
Cload = 1.8 nF
C
LOAD = 1.8 nF
18
17
16
15
14
13
12
16
15
14
13
12
11
10
9
C
C
C
C
= 1 nF
C
C
C
C
= 1 nF
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 2.2 nF
= 4.7 nF
= 10 nF
= 2.2 nF
= 4.7 nF
= 10 nF
11
10
8
7
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
V
DD
, SUPPLY VOLTAGE (V)
V
DD
, SUPPLY VOLTAGE (V)
Figure 9. Propagation Delay TD1 vs. Supply
Voltage
Figure 10. Propagation Delay TD2 vs. Supply
Voltage
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6
NCP81074A, NCP81074B
TYPICAL CHARACTERISTICS
200
180
160
140
120
100
80
200
180
160
140
120
100
80
2 MHz
1 MHz
60
60
40
40
20
0
20
0
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 11. Supply Current vs. Supply Voltage
LOAD = 2.2 nF
Figure 12. Supply Current vs. Supply Voltage
CLOAD = 4.7 nF
C
16
14
20
18
16
14
12
10
8
Test Conditions:
T = 25°C
1 ms Positive Pulse
Test Conditions:
T = 25°C
J
J
1 ms Positive Pulse
Fsw = 1 kHz
12
10
8
Fsw = 1 kHz
6
4
6
4
2
0
2
0
−3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
−2.5
−2.0
−1.5
−1.0
−0.5
0
OUT H − VDD (V)
OUT L (V)
Figure 13. Reverse Current, PMOS(on), PMOS(off)
Figure 14. Reverse Current, PMOS(off), PMOS(on)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
IN+ = VDD
GND and VDD
IN− = VDD
0.2
0
0
5
10
15
20
25
SUPPLY VOLTAGE (V)
Figure 15. Supply Current vs. Supply Voltage
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7
NCP81074A, NCP81074B
BENCH WAVEFORMS − Non−Inverting Input
Figure 16. Rise Time with 1.8 nF Load
Figure 17. Fall Time with 1.8 nF Load
Figure 18. Propagation Delays with 1.8 nF Load
Figure 19. Propagation Delays with 1.8 nF Load
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8
NCP81074A, NCP81074B
BENCH WAVEFORMS − Inverting Input
Figure 20. Rise Time with 1.8 nF Load
Figure 21. Fall Time with 1.8 nF Load
Figure 22. Propagation Delays with 1.8 nF Load
Figure 23. Propagation Delays with 1.8 nF Load
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9
NCP81074A, NCP81074B
PCB LAYOUT RECOMMENDATION
Proper component placement is extremely important in
high peak currents during the turn−on transition of the
MOSFET. Using a low ESL chip capacitor is highly
recommended.
high current, fast switching applications to provide
appropriate device operation and design robustness. The
NCP81074 gate driver exhibits a powerful output stage
enabling large peak currents with fast rise and fall times.
Eventhough the NCP81074 provides a split output
configuration for slew rate control, a proper PCB layout is
crucial to ensure maximum performance. The following
circuit layout guidelines are strongly recommended when
designing with the NCP81074.
• Place the driver close to the power MOSFET in order to
have a low impedance path between the output pins and
the gate. Keep the traces short and wide to minimize the
parasitic inductance and accommodate for high peak
currents.
• Keep a tight turn−on turn−off current loop paths to
minimize parastic inductance. High di/dt will induce
voltage spikes on the output pin and the MOSFET gate.
Parallel the source and return signals taking advantage
of flux cancellation.
• Since the NCP81074 is a 2x2mm package driving high
peak currents into capacitive loads, adding a shielding
ground plane helps in power dissipation and noise
blocking. The ground plane should not be a current
carrying path to any of the current loops.
• Any unused pin, should be pulled to either rail
depending on the functionality of the pin to avoid any
malfunction on the output. Please refer to the pin
description table for more information.
• Place the decoupling capacitor close to the gate drive
IC. Placing the VDD capacitor close to the pin and
ground improves noise filtering. This capacitor supplies
Figure 24.
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10
NCP81074A, NCP81074B
PACKAGE DIMENSIONS
DFN8 2x2
CASE 506AA
ISSUE E
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
MILLIMETERS
2X
0.15
C
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
EXPOSED Cu
MOLD CMPD
2X
0.15
C
TOP VIEW
0.20
0.30
D
2.00 BSC
D2
E
E2
e
K
L
L1
1.10
2.00 BSC
0.70
0.50 BSC
0.30 REF
0.25
−−−
1.30
A
C
DETAIL B
0.10
0.08
C
C
DETAIL B
0.90
OPTIONAL
CONSTRUCTION
0.35
0.10
(A3)
A1
NOTE 4
SEATING
PLANE
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
8X
0.50
D2
8X
L
1.30
4
1
8
PACKAGE
OUTLINE
E2
0.90
2.30
5
K
8X b
e/2
1
0.10 C A B
e
8X
0.30
0.50
PITCH
NOTE 3
C
0.05
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
NCP81074A, NCP81074B
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
SOLDERING FOOTPRINT*
0.25 (0.010)
Z
Y
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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NCP81074/D
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