NCP81075DR2G [ONSEMI]
High Performance Dual MOSFET Gate Driver;
| 型号： | NCP81075DR2G |
| 厂家： | 
ONSEMI |
| 描述： | High Performance Dual MOSFET Gate Driver 栅 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总13页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81075
High Performance Dual
MOSFET Gate Driver
Introduction
The NCP81075 is a high performance dual MOSFET gate driver
optimized to drive the gates of both high and low side power
MOSFETs in a synchronous buck converter. The NCP81075 uses an
on−chip bootstrap diode to eliminate the external discrete diode. A
high floating top driver design can accommodate HB voltage as high
as 180 V. The low−side and high−side are independently controlled
and match to 4 ns between the turn−on and turn−off of each other.
Independent Under−Voltage lockout is provided for the high side and
low side driver forcing the output low when the drive voltage is below
a specific threshold.
www.onsemi.com
8
1
1
1
SOIC−8 NB
DFN8
WDFN10
CASE 751−07
CASE 506CY CASE 511CE
Features
MARKING DIAGRAMS
• Drives Two N-Channel MOSFETs in High-Side and Low-Side
Configuration
• Floating Top Driver Accommodates Boost Voltage up to 180 V
8
NCP
81075
ALYWG
G
NCP81075
ALYWG
G
• Switching Frequency up to 1 MHz
• 20 ns Propagation Delay Times
• 4 A Sink, 4 A Source Output Currents
• 8 ns Rise / 7 ns Fall Times with 1000 pF Load
• UVLO Protection
1
NCP81075 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Specified from −40°C to 140°C
• Offered in SOIC−8 (D), DFN8 (MN), WDFN10 (MT)
Packages
(Note: Microdot may be in either location)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PINOUT DIAGRAMS
Applications
VDD 1
HB 2
10 LO
VDD 1
8 LO
• Telecom and Datacom
9 VSS
HB 2
HO 3
HS 4
7 VSS
6 LI
• Isolated Non−Isolated Power Supply Architectures
• Class D Audio Amplifiers
HO 3
HS 4
NC 5
8 LI
7 HI
6 NC
5 HI
• Two Switch and Active Clamp Forward Converters
SOIC/DFN8
WDFN10
Simplified Application Diagram
NCP81075
(top views)
VDD
VDD
HB
HO
ORDERING INFORMATION
VIN
HI
LI
†
Device
Package
Shipping
PWM
CONTROLLER
NCP81075
VOUT
HS
LO
NCP81075DR2G
NCP81075MNTXG
NCP81075MTTXG
SOIC8
(Pb−Free)
2500 /
Tape & Reel
DFN8
(Pb−Free)
4000 /
Tape & Reel
VSS
WDFN10
(Pb−Free)
4000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
October, 2017 − Rev. 1
NCP81075/D
NCP81075
Table 1. PIN DESCRIPTION
Pin No.
Pin No.
Symbol
Description
SOIC/DFN8
WDFN10
1
2
3
4
5
6
7
8
−
1
2
VDD
HB
HO
HS
HI
Positive Supply to the Lower Gate Driver
High Side Bootstrap Supply
High Side Output
3
4
High−Side Source
7
High−Side Input
8
LI
Low−Side Input
9
VSS
LO
NC
Negative Supply Return
Low−Side Output
10
5,6
No Connect
Table 2. MAXIMUM RATINGS
Parameter
Value
Units
VDD
−0.3 to 24
V
V
V
V
HB
−0.3 to 200
V
HO
DC
V
– 0.3 to V + 0.3
HS HB
Repetitive Pulse < 100 ns
V − 2 to V + 0.3, (V − V < 24)
HS HB HB HS
V
V
DC
DC
−20 to 200 − VDD
−0.3 to VDD + 0.3
−2 to VDD + 0.3
−10 to 24
V
V
HS
LO
Repetitive pulse < 100 ns
V
, V
V
V
HI
LI
V
−0.3 to 24
−40 to 170
−65 to 150
+300
HB − HS
Operating Junction Temperature Range, T
°C
°C
°C
V
J
Storage Temperature, T
STG
Lead Temperature (Soldering, 10 sec)
HBM
CDM
1000
2000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V – V should be in the range of −0.3 V to +20 V.
HB
HS
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameter
Min
8.5
Nom
Max
20
Units
V
DD
V
HS
V
HB
Supply Voltage Range
Voltage on HS (DC)
Voltage on HB
12
V
−10
180 − VDD
V
+ 8,
V
+ 20,
HS
HS
V
DD
− 1
180
Voltage Slew Rate on HS
50
V / ns
°C
T
J
Operating Junction Temperature Range
−40
− 0.3
+140
V
HO
V
HS
V
V
+ 0.3
V
HB
DD
V
LO
−0.3
+ 0.3
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
2
NCP81075
ABSOLUTE MAXIMUM RATINGS
Table 4. ELECTRICAL/THERMAL INFORMATION (All signals referenced to GND unless noted otherwise, Note 2)
Thermal Characteristic
SOIC
41
DFN8
36
DFN10
35
Unit
°C/W
q
q
q
q
Junction to Ambient thermal resistance
JA
Junction to case (Top) thermal resistance
50
42
32
JC(top)
Junction to Board thermal resistance
10
19.1
4
12
JB
Junction to case (Bottom) thermal resistance
Junction to top characterization parameter
Junction to board characterization parameter
1.5
3.1
10
1.3
JC(Bottom)
y
y
0.6
19.3
1
0.2
JT
JB
12.2
Moisture Sensitivity Level (MSL)
QFN Package
2. This data was taken using the JEDEC proposed High−K Test PCB.
Table 5. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: T = T = −40°C to 140°C; VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO
A
J
Parameter
Test Condition
Min
Typ
Max
Units
SUPPLY CURRENTS
I
VDD quiescent current
VDD operating current
V
= V = 0
0.85
7.3
1.8
15
11
mA
DD
LI
HI
I
f = 500 kHz, C
f = 300 kHz, C
= 0
= 0
DDO
LOAD
4.9
LOAD
I
Boot voltage quiescent current
Boot voltage operating current
V
= V = 0 V
0.92
6.55
4.5
1.8
12
7.0
25
HB
LI
HI
I
f = 500 kHz, C
f = 300 kHz, C
= 0
= 0
HBO
LOAD
LOAD
I
HB to V quiescent current
V
HS
= V = 110 V
5.0
mA
HBS
SS
HB
I
HB to V operating current
f = 500 kHz, C = 0
LOAD
0.1
mA
HBSO
SS
INPUT
V
, V
, V
Input rising threshold
Input falling threshold
Input Pulldown Resistance
2.7
100
6.2
5.5
V
kW
V
HIH
LIH
V
0.8
HIL
LIL
R
170
350
IN
UNDERVOLTAGE PROTECTION (UVLO)
VDD rising threshold
7.1
0.58
6.5
8.0
7.5
VDD threshold hysteresis
VHB rising threshold
VHB threshold hysteresis
BOOTSTRAP DIODE
0.5
V
Low−current forward voltage
High−current forward voltage
Dynamic resistance, DVF/DI
I
I
I
− HB = 100 mA
0.59
0.85
0.94
0.95
1.1
V
W
V
A
F
VDD
VDD
VDD
V
FI
− HB = 100 mA
R
− HB = 100 mA and 80 mA
2.0
D
LO GATE DRIVER
V
Low level output voltage
High level output voltage
Peak pull−up current
I
I
= 100 mA
0.1
0.15
4
0.40
0.40
LOL
LOH
LO
V
= −100 mA, V
= V − V
LO
LOH DD LO
V
V
= 0 V
LO
LO
Peak pull−down current
= 12 V
4
www.onsemi.com
3
NCP81075
Table 5. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: T = T = −40°C to 140°C; VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO
A
J
Parameter
Test Condition
Min
Typ
Max
Units
HO GATE DRIVER
V
Low level output voltage
High level output voltage
Peak pull−up current
I
I
= 100 mA
0.1
0.15
4
0.40
0.40
V
A
HOL
HOH
HO
V
= −100 mA, V
= V – V
HOH HB HO
HO
V
= 0 V
LO
LO
Peak pull−down current
V
= 12 V
4
PROPAGATION DELAYS
t
V
LI
V
HI
V
LI
V
HI
falling to V falling
C
C
C
C
C
C
C
C
= 0 (−40 to 125°C)
= 0 (−40 to 140°C)
= 0 (−40 to 125°C)
= 0 (−40 to 140°C)
= 0 (−40 to 125°C)
= 0 (−40 to 140°C)
= 0 (−40 to 125°C)
= 0 (−40 to 140°C)
20
20
20
20
20
20
20
20
45
50
45
50
45
50
45
50
ns
DLFF
LO
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
t
falling to V falling
DHFF
DLRR
HO
t
rising to V rising
LO
t
rising to V rising
DHRR
HO
DELAY MATCHING
tMON
LI ON, HI OFF
LI OFF, HI ON
3.5
3.5
14
14
ns
tMOFF
OUTPUT RISE AND FALL TIME
t
LO, HO
C
C
C
C
= 1000 pF
= 1000 pF
= 0.1 mF
8
7
ns
R
LOAD
LOAD
LOAD
LOAD
t
LO, HO
F
t
R
LO, HO (3 V to 9 V)
LO, HO (3 V to 9 V)
0.2
0.25
0.55
0.45
ms
t
= 0.1 mF
F
MISCELLANEOUS
t
Minimum input pulse width that
changes the output
30
50
ns
1
t
2
Bootstrap diode turn−off time
I = 100 mA, I
= −100 mA
F
REV
(Notes 3 and 4)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values for T = 25°C
A
4. I : Forward current applied to bootstrap diode, I
: Reverse current applied to bootstrap diode.
REV
F
www.onsemi.com
4
NCP81075
Internal Block Diagram
Figure 1. Internal Block Diagram
Timing Diagrams
VDD / VHB-VHS
UVLO
Thresholds
LI
Delay ~ 40us
LO
HI
Delay ~ 40us
HO
Note: If HI is set and the High−Side driver (VHB−VHS) crosses its UVLO threshold
100ns after the VDD UVLO then a rising edge on HI is required to pull HO High.
Figure 2. UVLO
www.onsemi.com
5
NCP81075
LI
HI
LO
TMOFF
TON
HO
Figure 3. TMON and TMOFF
90%
10%
HI, LI
TDLRR
TDHRR
90%
TDLFF
TDHFF
10%
HO, LO
Figure 4. Propagation Delays
LOGIC TABLE
HI
L
LI
HO
LO
L
L
H
L
L
L
L
H
L
H
H
H
H
H
H
www.onsemi.com
6
NCP81075
PINOUT DIAGRAMS
DFN8
1
2
3
4
8
7
6
5
LO
VSS
LI
VDD
HB
GND
Pad
HO
HS
HI
WDFN10
1
10
LO
VDD
2
3
9
8
HB
HO
VSS
LI
GND
Pad
HS
NC
4
5
7
6
HI
NC
SOIC 8
8
7
6
1
2
3
LO
VDD
HB
HO
VSS
LI
HS
5
HI
4
Note: The V Pin and the GND Pad are internally connected.
SS
Figure 5. NCP81075 Top View
www.onsemi.com
7
NCP81075
TYPICAL CHARACTERISTICS
4
3
4.0
3.5
3.0
2.5
TmOFF
2
1
0
HI ; LI = High
2.0
I(HB)
−1
−2
−3
1.5
Input Current
1.0
TmON
0.5
0
−4
−5
−50 −25
0
25
50
75 100 125 150
8
10
12
14
16
18
20
22
24
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 6. Delay Matching vs. Temperature
Figure 7. Quiescent Current vs. Supply
Voltage High
1.6
1.4
1.2
1.0
0.8
0.6
0.4
3.0
2.5
2.0
1.5
1.0
Rising
Falling
HI ; LI = GND
I(HB)
I(VDD)
0.5
0
0.2
0
8
10
12
14
16
18
20
22
24
−50 −25
0
25
50
75 100 125 150
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 8. Quiescent Current vs. Supply
Voltage Low
Figure 9. Input Threshold vs. Temperature
1.99
1.98
1.97
1.96
1.95
1.94
1.93
1.92
1.91
4.0
3.5
3.0
2.5
2.0
1.5
1.0
Rising
Falling
T = 25°C
0.5
0
1.90
1.89
Sink Current
2
Source Current
10 12
8
10
12
14
16
18
20
22
24
0
4
6
8
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 10. Input Threshold vs. Supply Voltage
Figure 11. Output Current vs. Output Voltage
www.onsemi.com
8
NCP81075
TYPICAL CHARACTERISTICS
22.5
22.0
21.5
21.0
25
20
15
10
Falling
Rising
Falling Edge
Rising Edge
20.5
5
0
20.0
19.5
8
10
12
14
16
18
20
22
24
−50 −25
0
25
50
75 100 125 150
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 12. Propagation Delay vs. Supply
Voltage
Figure 13. Propagation Delay vs. Temperature
1000
100
10
10
9
I(VDD)
8
I(HB)
7
6
1
5
4
0.1
3
2
0.01
1
0
0.001
10 110 210 310 410 510 610 710 810 910 1010
FREQUENCY (kHz)
0.50
0.60
0.70
0.80
0.90
DIODE VOLTAGE (V)
Figure 14. Operating Current vs. Frequency
Figure 15. Diode Current vs. Diode Voltage
www.onsemi.com
9
NCP81075
APPLICATION INFORMATION
The NCP81075 is a high performance dual MOSFET gate
the HS Pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VDD again. The high−side driver’s
output is in phase with the HI input. When the driver is
disabled, the high side gate is held low.
The external BST resistor, which connects HB pin and
BST cap, should avoid excessive resistance. NCP81075
has high−side UVLO protection based on the voltage across
HB and HS pins. High resistance on HB pin may falsely
trigger UVLO protection at the moment when high−side
MOSFET is turning on.
driver optimized for driving the gates of both high side and
low side power MOSFETs in a synchronous buck converter
topology. A high and a Low input signals are all that is
required to properly drive the high side and low side
MOSFETs.
Low−Side Driver
The low side driver is designed to drive low RDS
ON
N−channel MOSFETs. The typical output resistances for the
driver are 1.5 ohms for sourcing and 1 ohm for sinking gate
current. Due to the parasitic inductances of the packages,
drive circuits and the nonlinearity of the MOSFETs output
resistances the recorded peak current is close to 4 A.
The low output resistances allow the driver to have 8 ns
rise and 7 ns fall times into a 1 nF load. When the driver is
enabled, the driver’s output is in phase with LI. When the
NCP81075 is disabled, the low side gate is held low.
UVLO (Under Voltage Lockout)
The bias supplies of the high−side and low−side drivers
have UVLO protection. The VDD UVLO disables both
drivers when the VDD voltage crosses the specified
threshold. The typical rising threshold is 7.1 V with 0.58 V
hysteresis. The VHB UVLO disables only the high−side
driver when the VHB to VHS is below the specified
threshold. The typical VHB UVLO rising threshold is 6.5 V
with 0.5 V hysteresis. The designer must take into account
a 40 ms delay before the output channels can react to a logic
input. (Refer to the UVLO Timing Diagram).
High−Side Driver
The high side driver is designed to drive a floating low
RDS N−channel MOSFET. The output resistances for the
ON
driver are 1.5 ohms for sourcing and 1 ohm for sinking gate
current. The bias voltage for the high side driver is realized
by an external bootstrap supply circuit which is connected
between the HB and HS Pins.
The bootstrap circuit comprises only of the bootstrap
capacitor since the bootstrap diode is internal. When the
NCP81075 is starting up, the HS Pin is at ground, the
bootstrap capacitor will charge up to VDD through the
internal diode. When the HI goes high, the high side driver
will begin to turn the high side MOSFET On by pulling
charge out of the bootstrap capacitor. As the external
MOSFET turns ON, the HS Pin will rise up to VIN, forcing
Input Stages
The input stage of the NCP81075 is TTL compatible. The
logic rising threshold level is 2.4 V and the logic falling
threshold is 1.6 V.
Layout Guidelines
Gate drivers experience high di/dt during the switching
transitions. So, the inductance at the gate drive traces must
be minimized to avoid excessive ringing on the switch node.
Gate drive traces should be kept as short and wide (> 20 mil)
as practical. The input capacitor must be placed as close as
possible to the IC. Connect the VSS pin of the NCP81075 as
close as possible to the source of the lower MOSFET. The
use of vias is highly desirable to maximize thermal
conduction away from driver.
the HB Pin to VIN + V
which is enough gate to source
BstCap
voltage to hold the switch On. To complete the cycle, the
MOSFET is switched OFF by pulling the gate down to the
voltage at the HS Pin. When the low side MOSFET turns On,
www.onsemi.com
10
NCP81075
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
NCP81075
PACKAGE DIMENSIONS
DFN8, 4x4, 0.8P
CASE 506CY
ISSUE O
NOTES:
A
B
D
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
L
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
PIN ONE
REFERENCE
E
OPTIONAL
CONSTRUCTIONS
2X
MILLIMETERS
0.15
C
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
2X
0.15
C
TOP VIEW
A3
b
0.20 REF
0.25
0.35
D
4.00 BSC
EXPOSED Cu
MOLD CMPD
DETAIL B
D2 3.28
3.48
0.10
0.08
C
C
E
4.00 BSC
2.55
0.80 BSC
E2 2.35
e
K
L
L1
A
0.375 REF
8X
DETAIL B
(A3)
0.30
−−−
0.50
0.15
ALTERNATE
NOTE 4
A1
SEATING
PLANE
CONSTRUCTION
C
SIDE VIEW
D2
8X L
DETAIL A
1
4
RECOMMENDED
SOLDERING FOOTPRINT*
8X
0.63
3.58
E2
8
5
K
8X b
e
M
0.10
C A B
e/2
2.65
4.30
M
NOTE 3
C
0.05
PACKAGE
OUTLINE
BOTTOM VIEW
8X
0.40
0.80
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
12
NCP81075
PACKAGE DIMENSIONS
WDFN10 4x4, 0.8P
CASE 511CE
ISSUE O
NOTES:
B
E
A
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END
OF TERMINAL LEAD AT EDGE OF PACKAGE.
6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL B
ALTERNATE CONSTRUCTION IS NOT APPLICABLE.
L
L
L1
PIN ONE
REFERENCE
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
2X
MILLIMETERS
DIM MIN
MAX
0.80
0.05
0.10
0.10
C
A
A1
A3
b
0.70
0.00
0.20 REF
A3
2X
C
EXPOSED Cu
MOLD CMPD
TOP VIEW
0.25
0.35
D
4.00 BSC
D2
E
E2
e
K
L
2.90
4.00 BSC
2.50
0.80 BSC
0.30 REF
0.30
0.00
3.10
DETAIL B
0.10
C
C
A
C
2.70
A1
10X
DETAIL B
ALTERNATE
CONSTRUCTIONS
0.50
0.15
0.08
A3
L1
SEATING
PLANE
A1
NOTE 4
SIDE VIEW
D2
DETAIL A
10X L
RECOMMENDED
MOUNTING FOOTPRINT
1
5
10X
0.60
3.20
E2
4.30
2.76
PACKAGE
OUTLINE
K
10
6
10X
b
e
1
0.10 C A B
10X
0.42
0.80
PITCH
0.05
C
NOTE 3
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP81075/D
◊
相关型号：
©2020 ICPDF网 联系我们和版权申明